Microprocessors and Microsystems最新文献_第4页

Polynomial formal verification parameterized by cutwidth properties of a circuit using Boolean satisfiability 用布尔可满足性参数化电路宽度特性的多项式形式验证

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-11-01 Epub Date: 2025-09-02 DOI: 10.1016/j.micpro.2025.105199

Luca Müller , Rolf Drechsler

Verification is an essential step in the design process of microprocessors. A complete coverage can only be ensured by formal methods, which tend to have exponential runtimes in the general case. Polynomial Formal Verification addresses this issue, opening a research field focused on providing formal methods which can ensure 100% correctness along with predictable and manageable time and space complexity. In this work, two SAT-based verification approaches in the field of PFV are presented. For both the verification of the cutwidth decomposition on the Circuit-CNF and the verification of the cutwidth decomposition on the Circuit-AIG, it is proven that their time complexity is parameterized by their respective cutwidth. This enables the definition of a class of circuits with constant cutwidth, for which verification can be ensured in linear time. After the theoretical considerations, both approaches are experimentally evaluated on the case study of adder circuits, underlining the established theoretical bounds. Finally, both approaches are compared and their significance in the research filed of PFV are stated.

验证是微处理器设计过程中必不可少的一步。完整的覆盖只能通过形式化方法来保证，而形式化方法在一般情况下往往具有指数级的运行时间。多项式形式验证解决了这个问题，打开了一个研究领域，专注于提供可以确保100%正确性以及可预测和可管理的时间和空间复杂性的形式化方法。在这项工作中，提出了两种基于sat的PFV领域验证方法。对Circuit-CNF上的宽度分解的验证和Circuit-AIG上的宽度分解的验证，证明了它们的时间复杂度是由各自的宽度参数化的。这样就可以定义一类具有恒定切割宽度的电路，并确保在线性时间内对其进行验证。在理论考虑之后，两种方法都在加法器电路的案例研究中进行了实验评估，强调了已建立的理论界限。最后，对两种方法进行了比较，并指出了它们在PFV研究领域的意义。

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引用次数: 0

Time-predictable warp scheduling in a GPU GPU中可预测时间的翘曲调度

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-11-01 Epub Date: 2025-09-25 DOI: 10.1016/j.micpro.2025.105203

Noïc Crouzet, Thomas Carle, Christine Rochange

This paper presents architectural design solutions aimed at improving the timing predictability of GPU pipelines, with a particular focus on the behavior of hardware schedulers in the fetch and issue stages. We argue that without coordination between these schedulers at each cycle, the timing behavior of the GPU is unpredictable. We show how coordination can be enforced and prove that our solution achieves a predictable behavior. We have implemented it in a modified version of the open-source Vortex GPU, synthesized for an AMD Xilinx FPGA. We evaluate the overhead of the approach both in terms of FPGA resources and execution time.

本文提出了旨在提高GPU管道的时间可预测性的架构设计解决方案，特别关注硬件调度器在获取和发布阶段的行为。我们认为，如果在每个周期中这些调度器之间没有协调，GPU的定时行为是不可预测的。我们将展示如何执行协调，并证明我们的解决方案实现了可预测的行为。我们已经在开源Vortex GPU的修改版本中实现了它，该GPU是为AMD Xilinx FPGA合成的。我们从FPGA资源和执行时间两方面评估了该方法的开销。

引用次数: 0

Analog to digital memory modeling for test 模拟到数字存储器建模测试

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-11-01 Epub Date: 2025-08-19 DOI: 10.1016/j.micpro.2025.105189

Dorian Ronga , Gianmarco Mongelli , Eric Faehn , Patrick Girard , Arnaud Virazel

Memory testing is crucial as memories play an ever-increasing important role in modern computing systems, to which a memory malfunction can lead to a system failure. Memory testing is commonly addressed by a functional testing approach that consists in verifying the manufactured memory function. Functional testing focuses on identifying memory functional failure mechanisms, which are modeled by Functional Fault Models (FFM), and for which dedicated test algorithms are developed to ensure their detection. However, as technology shrinks, fault mechanisms in memories become more complex, as well as their detection conditions. To anticipate any limitation, memory structural testing is investigated. Structural testing proposes to study the defect before the fault, as one or several manufactured defects or imperfections may be responsible for a fault. A structural test methodology for memory has been recently published and proposes to adapt the Cell-Aware test methodology from the digital domain to analog memories. As the resulting Structural Fault Models (SFM) for analog memory are compatible with digital test environment, this work proposes a digital SRAM modeling methodology, compatible with digital simulation and test environments, leveraging Fault Simulator for test algorithm coverage analysis, and Automatic Test Pattern Generator for dedicated and optimized defect-specific test generation.

内存测试是至关重要的，因为内存在现代计算系统中扮演着越来越重要的角色，内存故障可能导致系统故障。内存测试通常通过功能测试方法来解决，该方法包括验证制造的内存功能。功能测试的重点是识别记忆功能故障机制，该机制由功能故障模型（FFM）建模，并开发了专用的测试算法来确保其检测。然而，随着技术的萎缩，记忆中的故障机制变得更加复杂，它们的检测条件也变得更加复杂。为了预测任何限制，研究了记忆结构测试。结构测试建议在故障发生之前对缺陷进行研究，因为一个或几个制造缺陷或缺陷可能导致故障。最近发表了一种存储器的结构测试方法，并建议将细胞感知测试方法从数字域调整到模拟存储器。由于模拟存储器的结构故障模型（SFM）与数字测试环境兼容，本工作提出了一种与数字仿真和测试环境兼容的数字SRAM建模方法，利用故障模拟器进行测试算法覆盖分析，并利用自动测试模式生成器进行专用和优化的缺陷特定测试生成。

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引用次数: 0

A cost-effective fault-tolerant EDAC solution for SRAM-based FPGAs and memory in space applications 为空间应用中基于sram的fpga和存储器提供经济高效的容错EDAC解决方案

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-11-01 Epub Date: 2025-10-05 DOI: 10.1016/j.micpro.2025.105208

Youcef Bentoutou, El Habib Bensikaddour, Chahira Serief, Chafika Belamri, Malika Bendouda

The reliability of memory and Field Programmable Gate Array (FPGA) devices in space is significantly challenged by Single Event Upsets (SEUs) caused by radiation exposure. To mitigate this, traditional methods such as Hamming (12, 8) codes and Triple Modular Redundancy (TMR) are commonly used. TMR involves triplicating memory or FPGA devices and using a voting logic to detect and correct erroneous bits, offering defense against radiation-induced upsets. However, this approach comes at a high cost in terms of resource utilization and power consumption. This paper presents a novel Error Detection and Correction (EDAC) system that combines partial TMR and Quasi-cyclic (QC) codes to enhance the protection of memory and SRAM-based FPGAs. The system selectively applies partial TMR to critical design components, reducing overhead while ensuring robust SEU protection. QC codes further improve memory error correction capabilities while minimizing the overhead associated with TMR. Experimental results demonstrate that the proposed EDAC system outperforms traditional methods, offering notable reductions in delay, area, and power consumption. This approach provides a more efficient and cost-effective solution for space applications, ensuring better reliability of FPGA and memory devices in low-Earth polar orbits.

空间存储器和现场可编程门阵列（FPGA）器件的可靠性受到辐射暴露引起的单事件干扰（seu）的显著挑战。为了减轻这种情况，通常使用汉明（12,8）码和三模冗余（TMR）等传统方法。TMR包括三倍存储器或FPGA设备，并使用投票逻辑来检测和纠正错误位，提供防御辐射引起的干扰。然而，这种方法在资源利用和功耗方面的成本很高。本文提出了一种结合部分TMR和准循环（QC）码的错误检测与校正（EDAC）系统，以增强对存储器和基于sram的fpga的保护。该系统选择性地将部分TMR应用于关键设计组件，减少开销，同时确保强大的SEU保护。QC代码进一步提高了内存纠错能力，同时最小化了与TMR相关的开销。实验结果表明，所提出的EDAC系统优于传统方法，在延迟、面积和功耗方面都有显著的降低。这种方法为空间应用提供了一种更高效、更经济的解决方案，确保了低地球极轨道上FPGA和存储设备的更好可靠性。

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引用次数: 0

Evaluating the performance of TinyML singular and ensemble techniques for intrusion detection in IoT networks 评估TinyML奇异和集成技术在物联网网络中入侵检测的性能

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-09-01 Epub Date: 2025-06-03 DOI: 10.1016/j.micpro.2025.105172

Abderahmane Hamdouchi , Ali Idri

As the Internet of Things (IoT) expands, safeguarding IoT networks from vulnerabilities becomes critical. Intrusion detection systems (IDS) leveraging machine learning (ML) techniques are essential for enhancing security and preventing unauthorized access. However, transmitting data to the cloud can introduce latency, impeding real-time attack detection. This research evaluates three TinyML ensemble techniques (random forest, XGBoost, and extra trees) and three singular techniques (decision tree, Gaussian naive Bayes, and multilayer perceptron) using two feature selection methods (maximum relevance minimum redundancy and analysis of variance) on the NF-ToN-IoT-v2 and NF-BoT-IoT-v2 datasets for cyberattack detection. Evaluations on the Arduino UNO used the prediction performance criteria (Cohen’s kappa and Matthew’s correlation coefficient), device metrics (latency, static RAM, and flash memory), and the Scott-Knott test and Borda count voting system to assess the statistical significance and to rank the models. Results show that singular TinyML models outperformed ensemble models for multiclass classification in the IDS-IoT context. The best models are: (1) MLP with 20 features and a hidden layer size of 56 for NF-ToN-IoT-v2; and (2) ET with 13 features, 2 estimators, and a tree depth of 16 for NF-BoT-IoT-v2.

随着物联网（IoT）的扩展，保护物联网网络免受漏洞的侵害变得至关重要。利用机器学习（ML）技术的入侵检测系统（IDS）对于增强安全性和防止未经授权的访问至关重要。然而，将数据传输到云可能会引入延迟，从而阻碍实时攻击检测。本研究评估了三种TinyML集成技术（随机森林、XGBoost和额外树）和三种奇异技术（决策树、高斯朴素贝叶斯和多层感知器），使用两种特征选择方法（最大相关最小冗余和方差分析）在NF-ToN-IoT-v2和NF-BoT-IoT-v2数据集上进行网络攻击检测。对Arduino UNO的评估使用了预测性能标准（Cohen’s kappa和Matthew’s相关系数）、设备指标（延迟、静态RAM和闪存）、Scott-Knott测试和Borda计数投票系统来评估统计显著性并对模型进行排名。结果表明，在IDS-IoT环境下，单一TinyML模型在多类分类方面优于集成模型。最佳模型是：(1)NF-ToN-IoT-v2的MLP具有20个特征，隐藏层大小为56；(2) NF-BoT-IoT-v2的ET具有13个特征，2个估计器，树深度为16。

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引用次数: 0

CRAX: Code reuse attacks on Xtensa’s register window ABI CRAX：对Xtensa的注册窗口ABI的代码重用攻击

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-09-01 Epub Date: 2025-08-12 DOI: 10.1016/j.micpro.2025.105188

Adebayo Omotosho , Christian Hammer

Code reuse attacks exploit existing codes in applications to hijack control flow and cause security breaches. However, reusing code on architectures with a register window or windowed register application binary interface (Winreg ABI), as known on Xtensa, poses significant challenges due to their unique architectural behavior. Winreg ABI aims to enhance register performance by reducing stack operations during procedure calls in reduced instruction set computer architectures. Rudimentary investigations have explored Winreg ABI exception handlers as potential sources of vulnerability in register window operations. Despite these efforts, the approach has been limited, even in synthetic examples, as it cannot technically reuse codes beyond changing register values.

In this paper, we present a novel approach to producing gadget-based code reuse attacks on Xtensa cores utilizing Winreg ABI, as found in embedded systems like ESP32 and ESP8266. At the same time, we showcase that established methods to detect such attacks such as leveraging hardware performance counter can also detect such attack schemes. Finally, we identify an additional potential loophole in the Winreg ABI. Our evaluation results using a number of benchmark applications demonstrate that successful attacks exhibit a consistent pattern that can be accurately detected.

代码重用攻击利用应用程序中的现有代码劫持控制流并导致安全漏洞。然而，在具有寄存器窗口或窗口寄存器应用程序二进制接口（Winreg ABI）的体系结构上重用代码，就像Xtensa所知道的那样，由于它们独特的体系结构行为，会带来重大挑战。Winreg ABI旨在通过在精简指令集计算机体系结构中减少过程调用期间的堆栈操作来提高寄存器性能。初步的调查已经将Winreg ABI异常处理程序作为注册窗口操作中的潜在漏洞来源进行了探索。尽管做出了这些努力，但这种方法仍然受到限制，即使在合成示例中也是如此，因为它在技术上不能重用代码，只能更改寄存器值。在本文中，我们提出了一种利用Winreg ABI在Xtensa内核上产生基于小工具的代码重用攻击的新方法，这种方法可以在ESP32和ESP8266等嵌入式系统中找到。同时，我们展示了现有的检测此类攻击的方法（如利用硬件性能计数器）也可以检测此类攻击方案。最后，我们确定了Winreg ABI中的另一个潜在漏洞。我们使用许多基准测试应用程序的评估结果表明，成功的攻击呈现出一种可以准确检测到的一致模式。

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引用次数: 0

Implementation and characterization of a fault-tolerant CCSDS 123 hardware accelerator under neutron radiation 中子辐射容错CCSDS 123硬件加速器的实现与特性研究

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-09-01 Epub Date: 2025-07-30 DOI: 10.1016/j.micpro.2025.105184

Wesley Grignani , Douglas A. Santos , Maria Kastriotou , Carlo Cazzaniga , Luigi Dilillo , Douglas R. Melo

In space applications, remote sensing relies on HSIs (Hyperspectral Images) to capture extensive Earth observation data. However, the substantial data volumes generated by HSIs present significant challenges for onboard storage and processing in space systems, underscoring the importance of efficient compression strategies. Additionally, the harsh conditions of the space environment expose these systems to potential faults, making the integration of fault-tolerant mechanisms crucial for maintaining reliable operation. In this context, this article presents the implementation of a low-cost and fault-tolerant CCSDS 123 HSI compressor. The compressor is present in different configurations employing hardening techniques such as TMR (Triple Modular Redundancy) and Hamming ECC (Error Correcting Code) to mitigate SEUs (Single-Event Upsets). We implemented techniques to enhance observability and evaluated the compressor reliability through fault injection simulations and physical tests at the ChipIr neutron irradiation facility. We present the resource utilization and performance results of each version with a comparative analysis with related work. The results highlight the lowest resource utilization achieved in the unhardened version, capable of processing 20.57 MSa/s and accelerating the application in 24

\times

compared to a software solution. The reliability results demonstrate a high error rate of 97.9% in the unhardened version, significantly reduced in partially hardened versions, with no error propagation in the fully hardened design. Furthermore, we present an analysis of the main components of the accelerator affected by the radiation-induced events observed in the particle accelerator test.

在空间应用中，遥感依靠高光谱图像（hsi）来获取广泛的地球观测数据。然而，hsi产生的大量数据量对空间系统的机载存储和处理提出了重大挑战，强调了有效压缩策略的重要性。此外，空间环境的恶劣条件使这些系统暴露于潜在故障，使得容错机制的集成对于保持可靠运行至关重要。在这种情况下，本文介绍了一种低成本、容错的CCSDS 123 HSI压缩机的实现。压缩机采用不同的配置，采用强化技术，如TMR（三模冗余）和Hamming ECC（纠错码），以减轻SEUs（单事件故障）。通过故障注入模拟和ChipIr中子辐照设施的物理测试，我们实施了增强可观测性的技术，并评估了压缩机的可靠性。我们给出了每个版本的资源利用率和性能结果，并与相关工作进行了比较分析。结果显示，未加固版本的资源利用率最低，处理速度为20.57 MSa/s，与软件解决方案相比，应用程序的速度提高了24倍。可靠性结果表明，在未硬化版本中错误率高达97.9%，在部分硬化版本中显著降低，在完全硬化设计中没有错误传播。此外，我们还分析了粒子加速器试验中观测到的辐射诱导事件对加速器主要部件的影响。

{"title":"Implementation and characterization of a fault-tolerant CCSDS 123 hardware accelerator under neutron radiation","authors":"Wesley Grignani , Douglas A. Santos , Maria Kastriotou , Carlo Cazzaniga , Luigi Dilillo , Douglas R. Melo","doi":"10.1016/j.micpro.2025.105184","DOIUrl":"10.1016/j.micpro.2025.105184","url":null,"abstract":"<div><div>In space applications, remote sensing relies on HSIs (Hyperspectral Images) to capture extensive Earth observation data. However, the substantial data volumes generated by HSIs present significant challenges for onboard storage and processing in space systems, underscoring the importance of efficient compression strategies. Additionally, the harsh conditions of the space environment expose these systems to potential faults, making the integration of fault-tolerant mechanisms crucial for maintaining reliable operation. In this context, this article presents the implementation of a low-cost and fault-tolerant CCSDS 123 HSI compressor. The compressor is present in different configurations employing hardening techniques such as TMR (Triple Modular Redundancy) and Hamming ECC (Error Correcting Code) to mitigate SEUs (Single-Event Upsets). We implemented techniques to enhance observability and evaluated the compressor reliability through fault injection simulations and physical tests at the ChipIr neutron irradiation facility. We present the resource utilization and performance results of each version with a comparative analysis with related work. The results highlight the lowest resource utilization achieved in the unhardened version, capable of processing 20.57 MSa/s and accelerating the application in 24<span><math><mo>×</mo></math></span> compared to a software solution. The reliability results demonstrate a high error rate of 97.9% in the unhardened version, significantly reduced in partially hardened versions, with no error propagation in the fully hardened design. Furthermore, we present an analysis of the main components of the accelerator affected by the radiation-induced events observed in the particle accelerator test.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105184"},"PeriodicalIF":2.6,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Detecting time drifts for securing Proof of Hardware Time in blockchain 在区块链中检测时间漂移以确保硬件时间证明

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-09-01 Epub Date: 2025-08-06 DOI: 10.1016/j.micpro.2025.105185

Quentin Jayet , Christine Hennebert , Yann Kieffer , Vincent Beroulle

Blockchain technology enables the creation of a timestamped, shared, and replicated history of events among participants who do not trust each other. To agree on the shared history, the blockchain uses a consensus protocol, such as Nakamoto’s protocol in Bitcoin. This protocol relies on a proof that statistically ensures the elapsed time between two blocks by design through the Proof of Work (PoW) mechanism. However, PoW relies heavily on computation and is not suitable for embedded systems. Proof of Hardware Time (PoHT) aims to provide a secure by design elapsed time proof mechanism with low power consumption. PoHT is embedded in a System on Module (SoM) that features an ARM Cortex-A7 microprocessor with a TrustZone and a Trusted Platform Module. This paper focuses on the security of the elapsed time measurement during PoHT, conducting experimental attacks targeting clock oscillators under temperature variations. It presents a consolidation of the various available time sources, as well as a solution for detecting time drifts. Furthermore, an embedded architecture for the time drift detection system is outlined and experimental testing of the system is performed.

区块链技术允许在互不信任的参与者之间创建带有时间戳的、共享的和复制的事件历史。为了在共享历史上达成一致，区块链使用共识协议，例如比特币中的中本聪协议。该协议依赖于通过工作量证明（PoW）机制在统计上确保两个块之间经过的时间的证明。然而，PoW严重依赖于计算，不适合嵌入式系统。硬件时间证明（PoHT）旨在通过设计提供一种安全的低功耗运行时间证明机制。PoHT嵌入在模块系统（SoM）中，该模块具有ARM Cortex-A7微处理器，具有TrustZone和可信平台模块。本文重点研究了在温度变化条件下对时钟振荡器进行攻击的经过时间测量的安全性。它提出了各种可用时间源的整合，以及时间漂移检测的解决方案。在此基础上，提出了时间漂移检测系统的嵌入式架构，并对系统进行了实验测试。

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引用次数: 0

High throughput DLP and mixed radix based architectures of Viterbi decoder 高吞吐量DLP和基于混合基数的维特比解码器架构

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-09-01 Epub Date: 2025-06-23 DOI: 10.1016/j.micpro.2025.105181

Mohamed Asan Basiri M.

Viterbi decoders play an important role in digital communication. This manuscript proposes two high throughput VLSI architectures of Viterbi decoder. In the first proposed architecture, the data level parallelism (DLP) based Viterbi decoder of rate

\frac{1}{N}

can be used to perform 1, 2, 4, 8, …parallel decodings of rates

\frac{1}{N}

,

\frac{1}{(N / 2)}

,

\frac{1}{(N / 4)}

,

\frac{1}{(N / 8)}

, …respectively. The second proposed mixed radix Viterbi decoder architecture is to perform four numbers of radix-

2^{k - 1}

decodings in parallel using one radix-

2^{k}

Viterbi decoder, where

k \geq 1

. All the conventional and proposed Viterbi decoders are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the proposed designs achieve high throughput as compared with the conventional designs. According to the synthesis results, the proposed mixed radix-2&4 decoder achieves 73.9% of improvement in maximum throughput as compared with the conventional radix-4 design.

维特比解码器在数字通信中起着重要的作用。本文提出了两种高吞吐量Viterbi译码器的VLSI架构。在第一种结构中，基于数据级并行（DLP）的1N速率的Viterbi解码器可以分别进行速率为1N、1（N/2）、1（N/4）、1（N/8）、…的1、2、4、8、…的并行解码。第二种提出的混合基数Viterbi解码器架构是使用一个基数2k的Viterbi解码器并行执行四个数的基数2k−1解码，其中k≥1。所有传统的和提出的维特比解码器都是使用Cadence在45纳米CMOS技术上实现的。综合结果表明，与传统设计相比，所提出的设计具有较高的通量。综合结果表明，所提出的混合radix-2&；4解码器与传统的radix-4设计相比，最大吞吐量提高了73.9%。

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引用次数: 0

High throughput event filtering: The interpolation-based DIF algorithm hardware architecture 高吞吐量事件过滤：基于插值的DIF算法硬件架构

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-09-01 Epub Date: 2025-06-11 DOI: 10.1016/j.micpro.2025.105171

Marcin Kowalczyk, Tomasz Kryjak

In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels.

近年来，事件视觉领域得到了迅速发展。它既体现在技术方面，随着越来越好的事件传感器的出现，也体现在算法方面，随着越来越多的技术应用的提出和科学论文的发表。然而，来自这些传感器的数据流通常包含大量的噪声，这取决于诸如观察场景中的照明程度或传感器的温度等因素。我们提出了一种基于距离的频率权重插值（DIF）滤波器的硬件架构，并在FPGA上实现。为了评估算法并将其与其他解决方案进行比较，我们准备了一个新的高分辨率事件数据集，我们也向社区发布了该数据集。我们的架构在传感器分辨率为1280 × 720时实现了每秒40339万事件（MEPS）的吞吐量，在分辨率为640 × 480时实现了428.45 MEPS。接收器工作特性下面积（AUROC）指数的平均值从0.844到0.999不等，具体取决于数据集，这与最先进的滤波解决方案相当，但在大范围的噪声水平下具有更高的吞吐量和更好的操作。

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引用次数: 0