2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Pub Date : 2017-06-29 DOI: 10.1109/ULIS.2017.7962596 Yusuke Yoshida, K. Usami

Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962584 A. Farokhnejad, M. Graef, F. Horst, C. Liu, Q. Zhao, B. Iñíguez, F. Lime, A. Kloes

S-shaped gate-all-around MOSFETs for high density design

Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962566 Ya-Chi Huang, Shui-Jinn Wang, M. Chiang