Oxidation induced stress effects on hole mobility as a function of transistor geometry in a 0.15 /spl mu/m dual gate oxide CMOS SOI process

Abstract

Additional process complexity required for multiple gate oxide thicknesses has been demonstrated to cause significant impact on p-channel mobility through oxidation induced stress effects. This can occur even after the STI oxide planarization step. Therefore, process flow options to minimize all oxidations after island definition should be considered. The data presented here also underscores the need to understand and model the oxidation induced stress associated with the specific device of interest. Since these stresses have a major impact on device mobility and current drive, care must be taken to make sure variation in layout options such as stacking transistors in a single device island rather than individual islands do not lead to circuit design modeling errors sufficient to compromise circuit performance margins. SUPREM4 appears to be able to model this behavior but most circuit level transistor models are not capable of handling this level of detail or complexity.