A modified instruction fetch control mechanism for SMT architecture

Abstract

In SMT architecture, instruction fetch unit is capable of fetching instructions from one or more threads simultaneously. Because of resource competing and run-time characteristics of threads, system resources are not sufficiently utilized. Considering necessary factors, a powerful instruction fetch mechanism can alleviate the adverse effects through appropriately fetch as many compatible instructions as possible. In this paper, the effects of instruction fetch policy on SMT performance are analyzed in detail, and a modified instruction fetch control mechanism is proposed. In this mechanism, a ready thread buffer is introduced in. With hardware list pointer structure, the buffer can be dynamically allotted. Further, the instruction fetch process is divided into two steps, and they deal with wrong branch prediction and instruction queue clog issues separately. Our instruction fetch control mechanism increase IPC for 9.39% over an unmodified SMT processor with ICOUNT2.8 policy. This speedup is enhanced by an advantage of considering main factors separately, the ability to favor for fetch those threads most efficiently using the processor each cycle, thereby, providing the "best" instructions to the processor.