{"title":"An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imaging","authors":"Changhyuk Lee, Ben Johnson, A. Molnar","doi":"10.1109/VLSIC.2014.6858427","DOIUrl":null,"url":null,"abstract":"We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, reject high-powered UV stimulus, and map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings over the SPAD to extract the incident angle of light, enabling 3-D localization at a micrometer scale. The chip integrates pixel-level counters and shared timing circuitry, and is implemented in unmodified 180nm CMOS.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Circuits Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2014.6858427","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, reject high-powered UV stimulus, and map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings over the SPAD to extract the incident angle of light, enabling 3-D localization at a micrometer scale. The chip integrates pixel-level counters and shared timing circuitry, and is implemented in unmodified 180nm CMOS.