Design of Random Forest-Based Low-Power VLSI Architecture to Detect Congestive Heart Failure for Wearable Devices

Abstract

Congestive heart failure (CHF) is an acute syndrome that results from ventricular dysfunction and progresses in four stages. Its timely detection can reverse heart damage and save lives. This work proposes a low-power, computationally efficient VLSI architecture to detect CHF using a single-lead ECG signal for the first time. This architecture employs a novel wavelet function-based electrocardiogram (ECG) feature extraction method and a random forest (RF) classifier, which can classify regular beats from CHF beats using a subject-oriented approach. Using ECG signals from publicly available datasets, BIDMC-CHF and MIT-BIH NSRDB, the proposed architecture achieves 90.5% accuracy, having a power consumption of $0.1~\mu W$ when implemented using TSMC 40-nm bulk CMOS technology as an ASIC. The low power consumption of the proposed architecture enables it to be utilized efficiently for real-time ECG analysis in wearable devices.