Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

SoC R&D trend for future digital life

Pub Date : 2005-08-01 DOI: 10.1093/ietele/e88-c.8.1705 Ki Won Lee

Interconnect delay aware RTL Verilog bus architecture generation for an SoC

Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349441 Kyeong Keol Ryu, A. Talpasanu, V. Mooney, J. Davis

A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications

Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349409 Kuo-Hsing Cheng, Shu-Ming Chang, Y. Lo, Shu-Yu Jiang