A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications

Abstract

In this paper, a DLL-based frequency multiplier is proposed. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier doesn't require external component and it is primarily intended for ASIC design. The HSPICE simulation results are based upon TSMC 0.18 /spl mu/m 1P6M N-well CMOS process at 1.8 V power supply. The simulation results show that the DLL can operate from 350 to 550MHz and the frequency multiplier synthesize frequency from 350MHz to 2.2GHz. The proposed frequency multiplier possess the programmable function, and the output clock frequency is 1/spl times/, 2/spl times/ and 4/spl times/ of an input reference clock. Each different clock frequency, the power dissipation all less than 7mW and the cycle-to-cycle jitter is less than 33ps.