Leveraging the Error Margins of Approximate Adders for Fault Tolerance with Minimum Redundancy

Abstract

Approximate Computing (AC) can be useful to applications with error resiliency, such as neural networks, to trade off between accuracy, performance, area, and power. Fault tolerance remains an open issue in AC since HW faults that are caused, for example, by radiation-induced effects, can lead to an arithmetic error out of application specification boundaries. Our approach guards approximate adders against HW faults by selectively inserting Hardware Error Detection (HED) redundancy, i.e., Double Modular Redundancy (DMR), only to the primitive adder cells of approximate adders that can cause an arithmetic error out of their resiliency boundaries (when corrupted by HW faults). Therefore, our approach introduces less area and delay overhead than hardening the whole circuit. We employ our methodology in various state-of-the-art approximate adders, such as low-latency and multi-bit approximate adders. We synthesize both the unhardened and hardened versions of the examined ASIC- and FPGA-based approximate adder architectures with Openlane and Vivado design flows, respectively. Our experimental results show that the proposed HED scheme can detect all out-of-boundaries errors: 1) without negating the original approximation gains of the unhardened design in terms of area and performance, and 2) by imposing significantly reduced overhead compared to the baseline (full DMR) hardened version.