FPGA Implementation of a 20 Mb/s OOK/8b10b VLC Receiver With Edge-Triggered Oversampled CDR and Measurement-Driven Calibration Characterization

Abstract

This paper reports an FPGA-based visible light communication (VLC) receiver prototype employing on–off keying (OOK) with 8b/10b line coding at a 20 Mb/s line rate (effective payload $\approx$ 16 Mb/s). The transmitter and receiver use 100 MHz DAC/ADC devices, yielding an oversampling ratio $M=5$. The receiver performs real-time clock and data recovery (CDR) on FPGA using a counter-based, edge-triggered timing rule: symbol transitions are detected by a first-difference (slope) operator, which re-anchors a counter and schedules symbol-center decisions. We also describe a measurement-driven offline calibration of timing-relevant parameters $\theta =[T_{\Delta },n_c,L_{\min }]$. The formulation is solver-agnostic; in our scripts we employ genetic algorithm (GA) and ant colony optimization (ACO) and use their agreement as a robustness check. From captured training streams we report the optimized slope threshold versus distance and outline a practical deployment path via a compact power-indexed look-up table (LUT) driven by a preamble-based received-power indicator. On a Xilinx Zynq-7000 FPGA, the complete design occupies 9.31% LUTs and 7.17% flip-flops, demonstrating feasibility for low-cost VLC front-ends. Beyond the hardware prototype, we develop a measurement-anchored link-level simulation that reproduces the measured slope-threshold-versus-distance characteristic ($R^2=0.987$) and use it to quantify bit-error-rate (BER) versus SNR against a fixed-phase baseline and to characterize robustness to sampling-frequency and sampling-phase offsets; these results are reported transparently as simulation, while a full hardware BER campaign and dynamic perturbation tests are left for future work.