Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045588
Dae-Hee Kim, R. Nagi, Deming Chen
As graphs become larger and more complex, it is becoming nearly impossible to process them without graph partitioning. Graph partitioning creates many subgraphs which can be processed in parallel thus delivering high-speed computation results. However, graph partitioning is a difficult task. In this work, we introduce Thanos, a fast graph partitioning tool which uses the cross-decomposition algorithm that iteratively partitions a graph. It also produces balanced loads of partitions. The algorithm is well suited for parallel GPU programming which leads to fast and high-quality graph partitioning solutions. Experimental results show that we have achieved 30x speedup and 35% better edge cut reduction compared to the CPU version of the popular graph partitioner, METIS, on average.
{"title":"Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition","authors":"Dae-Hee Kim, R. Nagi, Deming Chen","doi":"10.1109/ASP-DAC47756.2020.9045588","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045588","url":null,"abstract":"As graphs become larger and more complex, it is becoming nearly impossible to process them without graph partitioning. Graph partitioning creates many subgraphs which can be processed in parallel thus delivering high-speed computation results. However, graph partitioning is a difficult task. In this work, we introduce Thanos, a fast graph partitioning tool which uses the cross-decomposition algorithm that iteratively partitions a graph. It also produces balanced loads of partitions. The algorithm is well suited for parallel GPU programming which leads to fast and high-quality graph partitioning solutions. Experimental results show that we have achieved 30x speedup and 35% better edge cut reduction compared to the CPU version of the popular graph partitioner, METIS, on average.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114978125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045169
Ching-Hwa Cheng
Due to the high integration required for system application, the three-dimensional chip may resolve this requirement. The three-dimensional vertically stacking (3D-stacking) systems have been proposed to satisfy these requirements. However, the 3D-stacking system contains several design risks from its long layer interconnections. For a 3D-stacking system, it is difficult to identify where the numerous power and signal-interconnection are open-, shorted-fault, or resistive-short has accrued. Therefore, solving these interconnection problems is necessary. A feasible interconnection quality-evaluation, fault-diagnosis, and connection-reconfigurable mechanism are proposed. The proposed interconnection-measurement-recovery (IMR) mechanism will make it easy to find interconnection faults and make recovery in 3D-Stacking systems. The proposed IMR can detect interconnection open, short, bridge and resistive defects with the path-reroute mechanism. Future more, the signal transmission quality can be measured. This measurement provides to monitor signal propagation in pico-second accuracy. IMR has less extra area and power consumption overhead. The feasibilities of the proposed mechanism have been justified by 2D-chip and 3D-stacking MorPack both systems.
{"title":"A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System","authors":"Ching-Hwa Cheng","doi":"10.1109/ASP-DAC47756.2020.9045169","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045169","url":null,"abstract":"Due to the high integration required for system application, the three-dimensional chip may resolve this requirement. The three-dimensional vertically stacking (3D-stacking) systems have been proposed to satisfy these requirements. However, the 3D-stacking system contains several design risks from its long layer interconnections. For a 3D-stacking system, it is difficult to identify where the numerous power and signal-interconnection are open-, shorted-fault, or resistive-short has accrued. Therefore, solving these interconnection problems is necessary. A feasible interconnection quality-evaluation, fault-diagnosis, and connection-reconfigurable mechanism are proposed. The proposed interconnection-measurement-recovery (IMR) mechanism will make it easy to find interconnection faults and make recovery in 3D-Stacking systems. The proposed IMR can detect interconnection open, short, bridge and resistive defects with the path-reroute mechanism. Future more, the signal transmission quality can be measured. This measurement provides to monitor signal propagation in pico-second accuracy. IMR has less extra area and power consumption overhead. The feasibilities of the proposed mechanism have been justified by 2D-chip and 3D-stacking MorPack both systems.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121234328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045570
Sidhartha Sankar Rout, M. Badri, Sujay Deb
The contemporary network-on-chips (NoCs) are so complex that capturing all network functional faults at presilicon verification stage is nearly impossible. So, on-chip design-for-debug (DfD) structures such as trace buffers are provided to assist capturing escaped faults during post-silicon debug. Most of the DfD modules are left idle after the debug process. Reuse of such structures can compensate for the area overhead introduced by them. In this work, the trace buffers are reutilized as extended virtual channels for the router nodes of an NoC during in-field execution. Optimal distribution of trace buffers among the routers is performed based upon their load profiling. Experiments with several benchmarks on the proposed architecture show an average of 11.36% increase in network throughput and 13.97% decrease in average delay.
{"title":"Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs","authors":"Sidhartha Sankar Rout, M. Badri, Sujay Deb","doi":"10.1109/ASP-DAC47756.2020.9045570","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045570","url":null,"abstract":"The contemporary network-on-chips (NoCs) are so complex that capturing all network functional faults at presilicon verification stage is nearly impossible. So, on-chip design-for-debug (DfD) structures such as trace buffers are provided to assist capturing escaped faults during post-silicon debug. Most of the DfD modules are left idle after the debug process. Reuse of such structures can compensate for the area overhead introduced by them. In this work, the trace buffers are reutilized as extended virtual channels for the router nodes of an NoC during in-field execution. Optimal distribution of trace buffers among the routers is performed based upon their load profiling. Experiments with several benchmarks on the proposed architecture show an average of 11.36% increase in network throughput and 13.97% decrease in average delay.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125160030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network quantization is an effective solution to compress Deep Neural Networks (DNN) that can be accelerated with custom circuit. However, existing quantization methods suffer from significant loss in accuracy. In this paper, we propose an efficient shortcut architecture to enhance the representational capability of DNN between different convolution layers. We further implement the shortcut hardware architecture to effectively improve the accuracy of fully quantized neural networks accelerator. The experimental results show that our shortcut architecture can obviously improve network accuracy while increasing very few hardware resources $( 0.11 times$ and $0.17 times$ for LUT and FF respectively) compared with the whole accelerator.
{"title":"Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks Accelerator","authors":"Baoting Li, Longjun Liu, Yan-ming Jin, Peng Gao, Hongbin Sun, Nanning Zheng","doi":"10.1109/ASP-DAC47756.2020.9045739","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045739","url":null,"abstract":"Network quantization is an effective solution to compress Deep Neural Networks (DNN) that can be accelerated with custom circuit. However, existing quantization methods suffer from significant loss in accuracy. In this paper, we propose an efficient shortcut architecture to enhance the representational capability of DNN between different convolution layers. We further implement the shortcut hardware architecture to effectively improve the accuracy of fully quantized neural networks accelerator. The experimental results show that our shortcut architecture can obviously improve network accuracy while increasing very few hardware resources $( 0.11 times$ and $0.17 times$ for LUT and FF respectively) compared with the whole accelerator.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115195677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045449
Yangdi Lyu, P. Mishra
Hardware Trojans are serious threat to security and reliability of computing systems. It is hard to detect these malicious implants using traditional validation methods since an adversary is likely to hide them under rare trigger conditions. While existing statistical test generation methods are promising for Trojan detection, they are not suitable for activating extremely rare trigger conditions in stealthy Trojans. To address the fundamental challenge of activating rare triggers, we propose a new test generation paradigm by mapping trigger activation problem to clique cover problem. The basic idea is to utilize a satisfiability solver to construct a test corresponding to each maximal clique. This paper makes two fundamental contributions: 1) it proves that the trigger activation problem can be mapped to clique cover problem, 2) it proposes an efficient test generation algorithm to activate trigger conditions by repeated maximal clique sampling. Experimental results demonstrate that our approach is scalable and it outperforms state-of-the-art approaches by several orders-of-magnitude in detecting stealthy Trojans.
{"title":"Automated Trigger Activation by Repeated Maximal Clique Sampling","authors":"Yangdi Lyu, P. Mishra","doi":"10.1109/ASP-DAC47756.2020.9045449","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045449","url":null,"abstract":"Hardware Trojans are serious threat to security and reliability of computing systems. It is hard to detect these malicious implants using traditional validation methods since an adversary is likely to hide them under rare trigger conditions. While existing statistical test generation methods are promising for Trojan detection, they are not suitable for activating extremely rare trigger conditions in stealthy Trojans. To address the fundamental challenge of activating rare triggers, we propose a new test generation paradigm by mapping trigger activation problem to clique cover problem. The basic idea is to utilize a satisfiability solver to construct a test corresponding to each maximal clique. This paper makes two fundamental contributions: 1) it proves that the trigger activation problem can be mapped to clique cover problem, 2) it proposes an efficient test generation algorithm to activate trigger conditions by repeated maximal clique sampling. Experimental results demonstrate that our approach is scalable and it outperforms state-of-the-art approaches by several orders-of-magnitude in detecting stealthy Trojans.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116454031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the fast evolvement of deep-learning specific embedded computing systems, applications powered by deep learning are moving from the cloud to the edge. When deploying NNs onto the edge devices under complex environments, there are various types of possible faults: soft errors caused by atmospheric neutrons and radioactive impurities, voltage instability, aging, temperature variations, and malicious attackers. Thus the safety risk of deploying neural networks at edge computing devices in safety-critic applications is now drawing much attention. In this paper, we implement the random bit-flip, Gaussian, and Salt-and-Pepper fault models and establish a multi-objective fault-tolerant neural architecture search framework. On top of the NAS framework, we propose Fault-Tolerant Neural Architecture Search (FT-NAS) to automatically discover convolutional neural network (CNN) architectures that are reliable to various faults in nowadays edge devices. Then we incorporate fault-tolerant training (FTT) in the search process to achieve better results, which we called FTT-NAS. Experiments show that the discovered architecture FT-NAS-Net and FTT-NAS-Net outperform other hand-designed baseline architectures (58.1%/86.6% VS. 10.0%/52.2%), with comparable FLOPs and less parameters. What is more, the architectures trained under a single fault model can also defend against other faults. By inspecting the discovered architecture, we find that there are redundant connections learned to protect the sensitive paths. This insight can guide future fault-tolerant neural architecture design, and we verify it by a modification on ResNet-20–ResNet-M.
随着深度学习专用嵌入式计算系统的快速发展，由深度学习驱动的应用程序正在从云端向边缘移动。在复杂环境下将神经网络部署到边缘设备上时，可能存在各种类型的故障:大气中子和放射性杂质引起的软错误、电压不稳定、老化、温度变化、恶意攻击等。因此，在安全关键应用的边缘计算设备上部署神经网络的安全风险现在引起了人们的广泛关注。在本文中，我们实现了随机位翻转、高斯和盐胡椒故障模型，并建立了一个多目标容错神经结构搜索框架。在NAS框架的基础上，我们提出了容错神经架构搜索(FT-NAS)来自动发现当前边缘设备中可靠的卷积神经网络(CNN)架构。然后我们在搜索过程中加入容错训练(FTT)来获得更好的结果，我们称之为FTT- nas。实验表明，所发现的体系结构FT-NAS-Net和FTT-NAS-Net优于其他手工设计的基准体系结构(58.1%/86.6% VS. 10.0%/52.2%)，具有相当的FLOPs和较少的参数。更重要的是，在单一故障模型下训练的体系结构也可以防御其他故障。通过检查发现的结构，我们发现存在冗余连接来保护敏感路径。本文通过对ResNet-20-ResNet-M的修改，验证了这一观点对未来容错神经网络架构设计的指导作用。
{"title":"FTT-NAS: Discovering Fault-Tolerant Neural Architecture","authors":"Xuefei Ning, Guangjun Ge, Wenshuo Li, Zhenhua Zhu, Yin Zheng, Xiaoming Chen, Zhen Gao, Yu Wang, Huazhong Yang","doi":"10.1109/ASP-DAC47756.2020.9045324","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045324","url":null,"abstract":"With the fast evolvement of deep-learning specific embedded computing systems, applications powered by deep learning are moving from the cloud to the edge. When deploying NNs onto the edge devices under complex environments, there are various types of possible faults: soft errors caused by atmospheric neutrons and radioactive impurities, voltage instability, aging, temperature variations, and malicious attackers. Thus the safety risk of deploying neural networks at edge computing devices in safety-critic applications is now drawing much attention. In this paper, we implement the random bit-flip, Gaussian, and Salt-and-Pepper fault models and establish a multi-objective fault-tolerant neural architecture search framework. On top of the NAS framework, we propose Fault-Tolerant Neural Architecture Search (FT-NAS) to automatically discover convolutional neural network (CNN) architectures that are reliable to various faults in nowadays edge devices. Then we incorporate fault-tolerant training (FTT) in the search process to achieve better results, which we called FTT-NAS. Experiments show that the discovered architecture FT-NAS-Net and FTT-NAS-Net outperform other hand-designed baseline architectures (58.1%/86.6% VS. 10.0%/52.2%), with comparable FLOPs and less parameters. What is more, the architectures trained under a single fault model can also defend against other faults. By inspecting the discovered architecture, we find that there are redundant connections learned to protect the sensitive paths. This insight can guide future fault-tolerant neural architecture design, and we verify it by a modification on ResNet-20–ResNet-M.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045426
Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin
Electromagnetic (EM) side-channel attacks aim at extracting secret information from cryptographic hardware implementations. Countermeasures have been proposed at device level, register-transfer level (RTL) and layout level, though efficient, there are still requirements for quantitative assessment of the hardware implementations’ resistance against EM side-channel attacks. In this paper, we propose a design for EM side-channel security evaluation and optimization framework based on the t-test evaluation results derived from RTL hardware implementations. Different implementations of the same cryptographic algorithm are evaluated under different hypothesis leakage models considering the driven capabilities of logic components, and the evaluation results are validated with side-channel attacks on FPGA platform. Experimental results prove the feasibility of the proposed side-channel leakage evaluation method at pre-silicon stage. The remedies and suggested security design rules are also discussed.
{"title":"Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations","authors":"Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin","doi":"10.1109/ASP-DAC47756.2020.9045426","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045426","url":null,"abstract":"Electromagnetic (EM) side-channel attacks aim at extracting secret information from cryptographic hardware implementations. Countermeasures have been proposed at device level, register-transfer level (RTL) and layout level, though efficient, there are still requirements for quantitative assessment of the hardware implementations’ resistance against EM side-channel attacks. In this paper, we propose a design for EM side-channel security evaluation and optimization framework based on the t-test evaluation results derived from RTL hardware implementations. Different implementations of the same cryptographic algorithm are evaluated under different hypothesis leakage models considering the driven capabilities of logic components, and the evaluation results are validated with side-channel attacks on FPGA platform. Experimental results prove the feasibility of the proposed side-channel leakage evaluation method at pre-silicon stage. The remedies and suggested security design rules are also discussed.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045153
Lukas Burgholzer, R. Wille
Quantum computing is gaining considerable momentum through the recent progress in physical realizations of quantum computers. This led to rather sophisticated design flows in which the originally specified quantum functionality is compiled through different abstractions. This increasingly raises the question whether the respectively resulting quantum circuits indeed realize the originally intended function. Accordingly, efficient methods for equivalence checking are gaining importance. However, existing solutions still suffer from significant shortcomings such as their exponential worst case performance and an increased effort to obtain counterexamples in case of non-equivalence. In this work, we propose an improved DD-based equivalence checking approach which addresses these shortcomings. To this end, we utilize decision diagrams and exploit the fact that quantum operations are inherently reversible - allowing for dedicated strategies that keep the overhead moderate in many cases. Experimental results confirm that the proposed strategies lead to substantial speed-ups – allowing to perform equivalence checking of quantum circuits factors or even magnitudes faster than the state of the art.
{"title":"Improved DD-based Equivalence Checking of Quantum Circuits","authors":"Lukas Burgholzer, R. Wille","doi":"10.1109/ASP-DAC47756.2020.9045153","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045153","url":null,"abstract":"Quantum computing is gaining considerable momentum through the recent progress in physical realizations of quantum computers. This led to rather sophisticated design flows in which the originally specified quantum functionality is compiled through different abstractions. This increasingly raises the question whether the respectively resulting quantum circuits indeed realize the originally intended function. Accordingly, efficient methods for equivalence checking are gaining importance. However, existing solutions still suffer from significant shortcomings such as their exponential worst case performance and an increased effort to obtain counterexamples in case of non-equivalence. In this work, we propose an improved DD-based equivalence checking approach which addresses these shortcomings. To this end, we utilize decision diagrams and exploit the fact that quantum operations are inherently reversible - allowing for dedicated strategies that keep the overhead moderate in many cases. Experimental results confirm that the proposed strategies lead to substantial speed-ups – allowing to perform equivalence checking of quantum circuits factors or even magnitudes faster than the state of the art.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114553339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045462
Wenjian Yu, Ming Yang, Yao Feng, Ganqu Cui, B. Gu
Capacitance extraction and power grid (PG) analysis for IC design involve large-scale numerical simulation problems. As the process technology becomes more complicated and design margin is shrinking, the capacitance field solver and power-grid matrix solver with high accuracy and capability for handing large and complex structure are highly demanded. In this invited paper, we present recent application of statistical and AI methods in these two fields. The Markov-chain model and relevant analysis are presented for developing an efficient technique for handling conformal dielectrics in the floating random walk based capacitance extraction. Then, two approaches reducing the computational cost of a domain decomposition based power-grid solver are presented. One employs supervised machine learning while the other is inspired by the A*-search algorithm.
{"title":"Capacitance Extraction and Power Grid Analysis Using Statistical and AI Methods","authors":"Wenjian Yu, Ming Yang, Yao Feng, Ganqu Cui, B. Gu","doi":"10.1109/ASP-DAC47756.2020.9045462","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045462","url":null,"abstract":"Capacitance extraction and power grid (PG) analysis for IC design involve large-scale numerical simulation problems. As the process technology becomes more complicated and design margin is shrinking, the capacitance field solver and power-grid matrix solver with high accuracy and capability for handing large and complex structure are highly demanded. In this invited paper, we present recent application of statistical and AI methods in these two fields. The Markov-chain model and relevant analysis are presented for developing an efficient technique for handling conformal dielectrics in the floating random walk based capacitance extraction. Then, two approaches reducing the computational cost of a domain decomposition based power-grid solver are presented. One employs supervised machine learning while the other is inspired by the A*-search algorithm.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"15 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126231293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/ASP-DAC47756.2020.9045161
M. Hashimoto, Wang Liao
This paper discusses soft errors in digital chips consisting of SRAM, flip-flops, and combinational logic in the terrestrial environment. We review the effectiveness of error-correction coding (ECC) in processor systems and point out the importance of radiation-hardened flip-flops for further error mitigation. The discussion includes the difference between planar and FD-SOI transistors, and the type of secondary cosmic rays including neutron and muon, using irradiation test results. Also, the difficulty in characterizing SER of a commercial GPU chip is exemplified.
{"title":"Soft Error and Its Countermeasures in Terrestrial Environment","authors":"M. Hashimoto, Wang Liao","doi":"10.1109/ASP-DAC47756.2020.9045161","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045161","url":null,"abstract":"This paper discusses soft errors in digital chips consisting of SRAM, flip-flops, and combinational logic in the terrestrial environment. We review the effectiveness of error-correction coding (ECC) in processor systems and point out the importance of radiation-hardened flip-flops for further error mitigation. The discussion includes the difference between planar and FD-SOI transistors, and the type of secondary cosmic rays including neutron and muon, using irradiation test results. Also, the difficulty in characterizing SER of a commercial GPU chip is exemplified.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128050878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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