Pub Date : 2019-07-12DOI: 10.1109/EDSSC.2019.8754263
H. Deng, M. Chan, Shaolin Zhou
The metasurface is an ultra-thin two-dimensional array of planar device composed of periodic meta-units to enable multi-functional and extraordinary electromagnetic control, and thus shows great potentials in many scientific and technical applications due to its excellent filtering characteristics when used as filters. For most applications, the filter bandwidth is one of the most important performance metrics. In this paper, we demonstrate a broadband terahertz band-stop filter based on the design principle of metasurface. By superposition of multi-layer metasurfaces and the interactive couplings in-between, the designed filter demonstrates a significantly broadened bandwidth and the stop-band rejection with excellent cut-off in the range of 373-502GHz. The result reveals the mechanism of bandwidth broadening through field distribution in the full-wave analysis by finite element simulation. Further study also reveals absolute polarization independence of the designed metasurface filter, i.e. exactly the same transmission spectra for TE or TM incidence.
{"title":"Terahertz broadband band-stop filter based on metasurface","authors":"H. Deng, M. Chan, Shaolin Zhou","doi":"10.1109/EDSSC.2019.8754263","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754263","url":null,"abstract":"The metasurface is an ultra-thin two-dimensional array of planar device composed of periodic meta-units to enable multi-functional and extraordinary electromagnetic control, and thus shows great potentials in many scientific and technical applications due to its excellent filtering characteristics when used as filters. For most applications, the filter bandwidth is one of the most important performance metrics. In this paper, we demonstrate a broadband terahertz band-stop filter based on the design principle of metasurface. By superposition of multi-layer metasurfaces and the interactive couplings in-between, the designed filter demonstrates a significantly broadened bandwidth and the stop-band rejection with excellent cut-off in the range of 373-502GHz. The result reveals the mechanism of bandwidth broadening through field distribution in the full-wave analysis by finite element simulation. Further study also reveals absolute polarization independence of the designed metasurface filter, i.e. exactly the same transmission spectra for TE or TM incidence.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123536240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754439
Shijie Qiao, Q. Li, Yuzhuo Wang
An improved color attenuation priori dehazing algorithm is proposed in this paper. The performance of the improved algorithm is tested with MATALAB program. The hardware architecture for the improved algorithm is designed, the RTL codes of the architecture are programed, simulated, and synthesized to Altera’s FPGA. Experiment results show that the improved algorithm is efficient for image dehazing and the hardware architecture designed in this paper is correct.
{"title":"An Improved Color Attenuation Priori Dehazing Algorithm and Its Hardware Implementation","authors":"Shijie Qiao, Q. Li, Yuzhuo Wang","doi":"10.1109/EDSSC.2019.8754439","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754439","url":null,"abstract":"An improved color attenuation priori dehazing algorithm is proposed in this paper. The performance of the improved algorithm is tested with MATALAB program. The hardware architecture for the improved algorithm is designed, the RTL codes of the architecture are programed, simulated, and synthesized to Altera’s FPGA. Experiment results show that the improved algorithm is efficient for image dehazing and the hardware architecture designed in this paper is correct.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124279842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754486
Bai Chunfeng, Zhao Heming, Qiao Donghai
Two main topologies of feedback amplifiers are analyzed in detail in this paper. One is based on operational transconductance amplifier, but is limited in bandwidth. The other one is based on operational current amplifier, and can achieve wide bandwidth. In order to implement a wide-band feedback amplifier in a 130 nm CMOS with 1.2 V supply, a novel operational current amplifier with reasonable CMRR and wide output swing is proposed. This feedback amplifier draws 2.1 mA from 1.2 V supply while obtain 160 MHz bandwidth and 20.4 dBm IIP3 at 14-dB gain setting. The CMRR is 79 dB within 100 kHz, and is 20 dB within 2.5 GHz.
{"title":"A Wide-Band Feedback Amplifier based on A New Operational Current Amplifier in 130nm CMOS","authors":"Bai Chunfeng, Zhao Heming, Qiao Donghai","doi":"10.1109/EDSSC.2019.8754486","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754486","url":null,"abstract":"Two main topologies of feedback amplifiers are analyzed in detail in this paper. One is based on operational transconductance amplifier, but is limited in bandwidth. The other one is based on operational current amplifier, and can achieve wide bandwidth. In order to implement a wide-band feedback amplifier in a 130 nm CMOS with 1.2 V supply, a novel operational current amplifier with reasonable CMRR and wide output swing is proposed. This feedback amplifier draws 2.1 mA from 1.2 V supply while obtain 160 MHz bandwidth and 20.4 dBm IIP3 at 14-dB gain setting. The CMRR is 79 dB within 100 kHz, and is 20 dB within 2.5 GHz.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754354
W. Lai, Wei-Te Liu, Yan-Cu Lin, S. Jang
This article presents a low consumption phase locked loop (PLL) with electrostatic discharge (ESD) and use gain-boosted charge pump organization and a divided by 48 pulse swallow dividers. By gain-boosted technique can efficient to reduce the PLL reference spurs. The PLL consume of power is 6mW from 1.8V souring. The phase noise of the PLL is - 86.71 dBc/Hz at 1MHz offset and spurs are -32.64 dB. The PLL fully integrated and processing in UMC 0.18μm and it occupies 698μm×848μm active chipset area.
{"title":"Low Power Device Phase Locked Loop with Gm-Boosted Charge Pump and ESD Protection","authors":"W. Lai, Wei-Te Liu, Yan-Cu Lin, S. Jang","doi":"10.1109/EDSSC.2019.8754354","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754354","url":null,"abstract":"This article presents a low consumption phase locked loop (PLL) with electrostatic discharge (ESD) and use gain-boosted charge pump organization and a divided by 48 pulse swallow dividers. By gain-boosted technique can efficient to reduce the PLL reference spurs. The PLL consume of power is 6mW from 1.8V souring. The phase noise of the PLL is - 86.71 dBc/Hz at 1MHz offset and spurs are -32.64 dB. The PLL fully integrated and processing in UMC 0.18μm and it occupies 698μm×848μm active chipset area.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124049406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754474
Xitao He, Libo Qian, Da Li, Yinshui Xia
A high power supply rejection (PSR) low dropout (LDO) regulator is presented in the paper for system on chip applications. The small signal models of LDOs are analyzed and a power noise cancellation technique is developed. The PSR performance is improved by introducing a negative capacitor at the gate of power devices. The proposed technique is verified with an LDO that is simulated in a $0.18mu mathrm {m}$ CMOS technology with a power supply of 1. 2V. The entire LDO dissipate $76mu A$ quiescent current. The PSR is better than -30dB for the 0.1MHz-l0MHz frequency range when delivering a current of l0mA.
{"title":"Capacitor-Less Low Dropout Regulator with High PSR in 0.1–10MHz Range","authors":"Xitao He, Libo Qian, Da Li, Yinshui Xia","doi":"10.1109/EDSSC.2019.8754474","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754474","url":null,"abstract":"A high power supply rejection (PSR) low dropout (LDO) regulator is presented in the paper for system on chip applications. The small signal models of LDOs are analyzed and a power noise cancellation technique is developed. The PSR performance is improved by introducing a negative capacitor at the gate of power devices. The proposed technique is verified with an LDO that is simulated in a $0.18mu mathrm {m}$ CMOS technology with a power supply of 1. 2V. The entire LDO dissipate $76mu A$ quiescent current. The PSR is better than -30dB for the 0.1MHz-l0MHz frequency range when delivering a current of l0mA.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754222
Xufeng Liao, Wenbin Huang, Lianxi Liu
This paper proposes an 8 MHz boost converter with optimized line transient response and adaptive dead time for energy harvest system. The feed-forward compensation technique is proposed to achieve rapid line transient response. A dead-time control circuit is presented to achieve the adaptive dead time, which minimizes the body-diode conduction loss and thus improves the efficiency. The proposed converter is implemented in $0.18,mu mathrm {m}$ standard CMOS process with an active area of $0.80times 0.75 mathrm {m}mathrm {m}^{2}$. According to the simulation results, the line transient response is improved by 86.6%. Less than 1 ns body-diode conduction time has been achieved without bringing in shoot-through current across 10–150 mA load current range. The 1.8 V output voltage is achieved from 0.35–1.5V input voltage, and the peak efficiency is 88.9%.
{"title":"An 8 MHz Boost Converter with Feed-Forward Compensation and Adaptive Dead-Time Control","authors":"Xufeng Liao, Wenbin Huang, Lianxi Liu","doi":"10.1109/EDSSC.2019.8754222","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754222","url":null,"abstract":"This paper proposes an 8 MHz boost converter with optimized line transient response and adaptive dead time for energy harvest system. The feed-forward compensation technique is proposed to achieve rapid line transient response. A dead-time control circuit is presented to achieve the adaptive dead time, which minimizes the body-diode conduction loss and thus improves the efficiency. The proposed converter is implemented in $0.18,mu mathrm {m}$ standard CMOS process with an active area of $0.80times 0.75 mathrm {m}mathrm {m}^{2}$. According to the simulation results, the line transient response is improved by 86.6%. Less than 1 ns body-diode conduction time has been achieved without bringing in shoot-through current across 10–150 mA load current range. The 1.8 V output voltage is achieved from 0.35–1.5V input voltage, and the peak efficiency is 88.9%.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130839267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8753978
Yongjun Shi, Dan Li, Shengwei Gao, Yihua Zhang, Li Geng
A 112Gb/s PAM-4 linear optical receiver with low noise, high linearity in 28nm CMOS is presented. The receiver signal chain consists of a transimpedance amplifier (TIA), a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. PMOS CML logic is used based on the device characteristics. The low-noise topology and novel gain control techniques together enable state-of-the-art performance. The receiver achieves 2.72$mu$ Arms input-referred noise current, 71dB $Omega$ transimpedance gain and 37 GHz bandwidth. It is able to provide 18.5dB dynamic range to support maximum input overload current of 1.8mApp. The total harmonica distortion (THD) is below 5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.
提出了一种低噪声、高线性度的28nm CMOS 112Gb/s PAM-4线性光接收机。接收机信号链由一个跨阻放大器(TIA)、一个连续时间线性均衡器(CTLE)、一个可变增益放大器(VGA)和一个输出缓冲器组成。PMOS CML逻辑是基于器件特性使用的。低噪声拓扑结构和新颖的增益控制技术共同实现了最先进的性能。接收机的输入参考噪声电流为2.72 $mu$ Arms，跨阻增益为71dB $Omega$，带宽为37 GHz。它能够提供18.5dB动态范围，以支持1.8mApp的最大输入过载电流。口琴总失真(THD)低于5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.
{"title":"A 112Gb/s Low-Noise PAM-4 Linear Optical Receiver in 28nm CMOS","authors":"Yongjun Shi, Dan Li, Shengwei Gao, Yihua Zhang, Li Geng","doi":"10.1109/EDSSC.2019.8753978","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753978","url":null,"abstract":"A 112Gb/s PAM-4 linear optical receiver with low noise, high linearity in 28nm CMOS is presented. The receiver signal chain consists of a transimpedance amplifier (TIA), a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. PMOS CML logic is used based on the device characteristics. The low-noise topology and novel gain control techniques together enable state-of-the-art performance. The receiver achieves 2.72$mu$ Arms input-referred noise current, 71dB $Omega$ transimpedance gain and 37 GHz bandwidth. It is able to provide 18.5dB dynamic range to support maximum input overload current of 1.8mApp. The total harmonica distortion (THD) is below 5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128415731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754023
Lu Wang, Shuang Zhang
This paper proposes a new dual vector attitude coarse alignment method based on polarization information. In this paper, the linear polarization position angle (PPA) is analyzed by using the stability factor, and the optimal linear PPA is selected. On this basis, the initial attitude is estimated by the double vector method. Simulation experiments show that the proposed method is not sensitive to errors. This method can effectively determine the coarse attitude of the spacecraft and provide a better initial attitude angle for other subsequent attitude determination algorithm.
{"title":"Double Vector Attitude Coarse Estimation Method based on Polarization Information of X-ray Pulsar","authors":"Lu Wang, Shuang Zhang","doi":"10.1109/EDSSC.2019.8754023","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754023","url":null,"abstract":"This paper proposes a new dual vector attitude coarse alignment method based on polarization information. In this paper, the linear polarization position angle (PPA) is analyzed by using the stability factor, and the optimal linear PPA is selected. On this basis, the initial attitude is estimated by the double vector method. Simulation experiments show that the proposed method is not sensitive to errors. This method can effectively determine the coarse attitude of the spacecraft and provide a better initial attitude angle for other subsequent attitude determination algorithm.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754111
Mengdi Cao, Luqiang Duan, Guopei Chen, Ruichang Ma, Zhiyuan Chen, B. Chi
An optimized Ka-band low noise amplifier (LNA) for phased array radar system is presented in this paper. Two gain-boosting techniques are quantitatively analyzed and employed on the proposed LNA to achieve high gain and low noise performances. Meanwhile, three switched-capacitor arrays are inserted to prevent the center frequency (35GHz) from shifting with the PVT variations. Implemented in 65nm CMOS, the presented LNA features 26.2dB gain over 7GHz-3dB bandwidth (BW-3dB) while drawing 24.5mA current from one 1V power supply. The noise figure (NF) is lower than 3.4dB at 35GHz. S11 and S22 are below -10dB within the entire operating frequency band (33GHz-37GHz). The input third-order intercept point (IIP3) is higher than -22dBm.
{"title":"A Ka-Band Low Noise Amplifier for Phased Array Radar System in 65nm CMOS","authors":"Mengdi Cao, Luqiang Duan, Guopei Chen, Ruichang Ma, Zhiyuan Chen, B. Chi","doi":"10.1109/EDSSC.2019.8754111","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754111","url":null,"abstract":"An optimized Ka-band low noise amplifier (LNA) for phased array radar system is presented in this paper. Two gain-boosting techniques are quantitatively analyzed and employed on the proposed LNA to achieve high gain and low noise performances. Meanwhile, three switched-capacitor arrays are inserted to prevent the center frequency (35GHz) from shifting with the PVT variations. Implemented in 65nm CMOS, the presented LNA features 26.2dB gain over 7GHz-3dB bandwidth (BW-3dB) while drawing 24.5mA current from one 1V power supply. The noise figure (NF) is lower than 3.4dB at 35GHz. S11 and S22 are below -10dB within the entire operating frequency band (33GHz-37GHz). The input third-order intercept point (IIP3) is higher than -22dBm.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"7 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114031547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.1109/EDSSC.2019.8754374
Zekai Wu, Fule Li, Meng Ni, Yang Ding, Zhihua Wang
This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub- ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14- bit 500MS/s TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1% oTs initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.
提出了一种用于时间交错模数转换器(adc)的背景时序偏差校准技术。通过基于斜率和基于统计的技术，在数字域检测两个相邻子adc之间的时序偏差。基于检测误差，将数字控制延迟线(DCDL)驱动到最小的时序偏差。在14位500MS/s TI ADC模型中使用所提出的校准算法，MATLAB仿真结果表明，在Nyquist频率输入、1% oTs初始时序失配的情况下，所提出的校准算法收敛时间为346ms，可以有效降低电路实现中的硬件消耗。
{"title":"A Background Timing Skew Calibration Technique in Time-Interleaved ADCs","authors":"Zekai Wu, Fule Li, Meng Ni, Yang Ding, Zhihua Wang","doi":"10.1109/EDSSC.2019.8754374","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754374","url":null,"abstract":"This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub- ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14- bit 500MS/s TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1% oTs initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133184578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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