Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599228
Z. Yang, H. X. Liu, S. L. Wang
The gate leakage current issue in nanometer CMOS process is serious. An ESD detection circuit with reverse-used RC network is proposed in a 90-nm CMOS process. It reduces the leakage current in RC network by reducing the area of MOS capacitor and avoiding high voltage drop across MOS capacitor. The leakage current is 5.7 nA at 25°C. The total capacitor area used is only 4 μm2. Under ESD event, it can generate 39 mA trigger current to turn on the SCR.
{"title":"ESD detection circuit with reverse-used RC network in a 90-nm CMOS process","authors":"Z. Yang, H. X. Liu, S. L. Wang","doi":"10.1109/IPFA.2013.6599228","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599228","url":null,"abstract":"The gate leakage current issue in nanometer CMOS process is serious. An ESD detection circuit with reverse-used RC network is proposed in a 90-nm CMOS process. It reduces the leakage current in RC network by reducing the area of MOS capacitor and avoiding high voltage drop across MOS capacitor. The leakage current is 5.7 nA at 25°C. The total capacitor area used is only 4 μm2. Under ESD event, it can generate 39 mA trigger current to turn on the SCR.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134481304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599181
M. Zhou, Jigang Wu, Guiyuan Jiang, Xu Wang, Ji-zhou Sun
Although many reconfiguration strategies for fault tolerance on VLSI arrays have been proposed in the last two decades, few works on parallel reconfiguration have been reported. This paper presents an algorithm based on divide and conquer strategy for parallel reconfiguration VLSI arrays in the presence of faulty processing elements (PEs). The proposed algorithm splits the original host array into many sub-arrays in a recursive way, then target arrays are formed on each sub-arrays in parallel using a previous algorithm named GCR. The final target array is achieved by merging all these target arrays constructed on each sub-arrays. Experimental results show that the reconfiguration is significantly accelerated in comparison with previous algorithm GCR.
{"title":"Divide and conquer algorithm for parallel reconfiguration of VLSI array with faults","authors":"M. Zhou, Jigang Wu, Guiyuan Jiang, Xu Wang, Ji-zhou Sun","doi":"10.1109/IPFA.2013.6599181","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599181","url":null,"abstract":"Although many reconfiguration strategies for fault tolerance on VLSI arrays have been proposed in the last two decades, few works on parallel reconfiguration have been reported. This paper presents an algorithm based on divide and conquer strategy for parallel reconfiguration VLSI arrays in the presence of faulty processing elements (PEs). The proposed algorithm splits the original host array into many sub-arrays in a recursive way, then target arrays are formed on each sub-arrays in parallel using a previous algorithm named GCR. The final target array is achieved by merging all these target arrays constructed on each sub-arrays. Experimental results show that the reconfiguration is significantly accelerated in comparison with previous algorithm GCR.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134575706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599208
Seigo Ito, T. Matsumoto
The laser NEPS (Nano Electrostatic field Probe Sensor) method is one of the techniques to estimate a failing region by imaging the change of the carrier signal that occurs by irradiating the laser beam light to LSI under the non-contact and non-bias source analysis environment. In this announcement, the principle of the NEPS method is explained using a capacitive coupling model, and the laser irradiation position and the most suitable analysis condition of NEPS detecting position is clarified. In addition, the I/O terminal leak defect of the chip LSI products is analyzed by means of the NEPS method, and the result of detected abnormalities by the via contact and the meltdown of the silicon basal plate interface will be shown.
{"title":"A failure analysis technique using the Nano Electrostatic field Probe Sensor (NEPS)","authors":"Seigo Ito, T. Matsumoto","doi":"10.1109/IPFA.2013.6599208","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599208","url":null,"abstract":"The laser NEPS (Nano Electrostatic field Probe Sensor) method is one of the techniques to estimate a failing region by imaging the change of the carrier signal that occurs by irradiating the laser beam light to LSI under the non-contact and non-bias source analysis environment. In this announcement, the principle of the NEPS method is explained using a capacitive coupling model, and the laser irradiation position and the most suitable analysis condition of NEPS detecting position is clarified. In addition, the I/O terminal leak defect of the chip LSI products is analyzed by means of the NEPS method, and the result of detected abnormalities by the via contact and the meltdown of the silicon basal plate interface will be shown.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599117
Shao-feng Xie, En Yun-fei, Xiao-ling Lin, Yu-dong Lu, Yi-qiang Chen
Prognostics and health management (PHM) refers to functions that equipment in use can automatically complete the fault detection, prediction, isolation and monitoring, and timely fault impact assessment, fault report and condition monitoring management. This paper analyzes the requirement of engineering application and development of PHM technology. It focuses on three aspects technical problems of the application of PHM technology, including fault diagnosis and prediction model based on physics-of-failure (PoF), data mining technology and special sensors for critical failure mechanism of MOS devices. Correspondingly, present research work on these three aspects is introduced.
PHM (Prognostics and health management)是指在使用中的设备能够自动完成故障检测、预测、隔离和监测，并及时进行故障影响评估、故障报告和状态监测管理的功能。分析了PHM技术的工程应用需求和发展趋势。重点研究了基于失效物理(PoF)的故障诊断与预测模型、基于数据挖掘技术的MOS器件关键失效机理专用传感器等三个方面的技术问题。相应地，介绍了这三个方面的研究现状。
{"title":"Development and application of prognostics and health management technology","authors":"Shao-feng Xie, En Yun-fei, Xiao-ling Lin, Yu-dong Lu, Yi-qiang Chen","doi":"10.1109/IPFA.2013.6599117","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599117","url":null,"abstract":"Prognostics and health management (PHM) refers to functions that equipment in use can automatically complete the fault detection, prediction, isolation and monitoring, and timely fault impact assessment, fault report and condition monitoring management. This paper analyzes the requirement of engineering application and development of PHM technology. It focuses on three aspects technical problems of the application of PHM technology, including fault diagnosis and prediction model based on physics-of-failure (PoF), data mining technology and special sensors for critical failure mechanism of MOS devices. Correspondingly, present research work on these three aspects is introduced.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132527402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599195
M. Monjur, M. S. Wei, H. B. Chong, L. Nasar-Abdat, V. Narang
Back-side die polishing for thinning silicon uniformly to less than 100 μm is challenging due to sample warpage issues. A novel method involving back-side die polishing at elevated temperature has been used to minimize warpage of the sample during the actual milling process. The optimized process achieves highly uniform silicon thickness across the whole die. High-resolution laser images can be obtained across the samples at the same focal length, thus greatly improving the capability and accuracy of electrical fault isolation necessary for advanced devices.
{"title":"Thermal effect on die warpage during back-side die polishing of flip-chip BGA device","authors":"M. Monjur, M. S. Wei, H. B. Chong, L. Nasar-Abdat, V. Narang","doi":"10.1109/IPFA.2013.6599195","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599195","url":null,"abstract":"Back-side die polishing for thinning silicon uniformly to less than 100 μm is challenging due to sample warpage issues. A novel method involving back-side die polishing at elevated temperature has been used to minimize warpage of the sample during the actual milling process. The optimized process achieves highly uniform silicon thickness across the whole die. High-resolution laser images can be obtained across the samples at the same focal length, thus greatly improving the capability and accuracy of electrical fault isolation necessary for advanced devices.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133706727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599212
Y. Shen, E.S.C. Lee, S. Y. Chow, B. S. Khoo, C. Kon, D. Gui, Z. X. Xing
Transmission EBSD is used to analyze aluminum metal layer and GaAs/AlAs epitaxial layers, both are very common in semiconductor industries. Transmission EBSD shows a lateral spatial resolution about 20 nm and successfully reveals to features less than 100 nm in these samples.
{"title":"Application of transmission EBSD in aluminium metal layer and GaAs/AlAs epitaxial layers","authors":"Y. Shen, E.S.C. Lee, S. Y. Chow, B. S. Khoo, C. Kon, D. Gui, Z. X. Xing","doi":"10.1109/IPFA.2013.6599212","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599212","url":null,"abstract":"Transmission EBSD is used to analyze aluminum metal layer and GaAs/AlAs epitaxial layers, both are very common in semiconductor industries. Transmission EBSD shows a lateral spatial resolution about 20 nm and successfully reveals to features less than 100 nm in these samples.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132586892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599262
Y. Wang, Guangyi Lu, Jian Cao, S. Jia, Ganggang Zhang, Xing Zhang
A novel dual-directional silicon controlled rectifier (dSCR) device with dummy gate for electrostatic discharge (ESD) protection is presented. Compared with the traditional dSCR, the novel device has the desirable characteristics of dual-directional conduction, a low ESD trigger voltage, an adjustable ESD holding voltage and non-consumption of the extra area.
{"title":"Analysis of dummy-gate dual-directional SCR (dSCR) device for ESD protection","authors":"Y. Wang, Guangyi Lu, Jian Cao, S. Jia, Ganggang Zhang, Xing Zhang","doi":"10.1109/IPFA.2013.6599262","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599262","url":null,"abstract":"A novel dual-directional silicon controlled rectifier (dSCR) device with dummy gate for electrostatic discharge (ESD) protection is presented. Compared with the traditional dSCR, the novel device has the desirable characteristics of dual-directional conduction, a low ESD trigger voltage, an adjustable ESD holding voltage and non-consumption of the extra area.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132617355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599155
A. Singulani, H. Ceric, E. Langer
We have studied the stress evolution in the tungsten film of a particular open TSV technology during the thermal processing cycle. The film is attached to the via's wall and some plasticity is expected in the metal due to the temperature variation. Our work introduces a stress model for thin-films utilizing the traditional mechanical FEM approach. The results reveal potential reliability issues and a specific evolution of the stress in the tungsten layer.
{"title":"Stress evolution on tungsten thin-film of an open through silicon via technology","authors":"A. Singulani, H. Ceric, E. Langer","doi":"10.1109/IPFA.2013.6599155","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599155","url":null,"abstract":"We have studied the stress evolution in the tungsten film of a particular open TSV technology during the thermal processing cycle. The film is attached to the via's wall and some plasticity is expected in the metal due to the temperature variation. Our work introduces a stress model for thin-films utilizing the traditional mechanical FEM approach. The results reveal potential reliability issues and a specific evolution of the stress in the tungsten layer.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132697294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599214
Liyuan Liu, Guangning Xu, Fuyao Mo
Different abnormal appearances would usually be observed on dies of failed devices after decapsulation. In this paper, cases of failure analysis on typical abnormal appearances were introduced, such as discoloration region observed by metallographic microscope, fused/arching lines, common burnout of metallization on surface and uncovered by Photon Emission Microscope (EMMI) result, etc. It showed a simple and distinct way to study on the causation of abnormal appearances based on Focused Ion Beam (FIB) milling technology. Meanwhile the advantage of strong applicability was presented also.
{"title":"Study of abnormal appearances on the failed die by FIB milling technology","authors":"Liyuan Liu, Guangning Xu, Fuyao Mo","doi":"10.1109/IPFA.2013.6599214","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599214","url":null,"abstract":"Different abnormal appearances would usually be observed on dies of failed devices after decapsulation. In this paper, cases of failure analysis on typical abnormal appearances were introduced, such as discoloration region observed by metallographic microscope, fused/arching lines, common burnout of metallization on surface and uncovered by Photon Emission Microscope (EMMI) result, etc. It showed a simple and distinct way to study on the causation of abnormal appearances based on Focused Ion Beam (FIB) milling technology. Meanwhile the advantage of strong applicability was presented also.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116003133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-07-15DOI: 10.1109/IPFA.2013.6599234
Y. Tseng, Chun-Liang Wang, Yu-Chia Chang
In this paper, we develop a pulsing electrical over stress testing method to simulate different electrical over stress (EOS) in CMOS integrated circuits and the tolerance values distinguished from ESD failure. The electrical and deprocessing analysis shows that pulsing EOS testing can acquire a tolerance index of integrated circuits for production quality control.
{"title":"Pulsing electrical over-stress (EOS) testing and its failure analysis for advanced process integrated circuits","authors":"Y. Tseng, Chun-Liang Wang, Yu-Chia Chang","doi":"10.1109/IPFA.2013.6599234","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599234","url":null,"abstract":"In this paper, we develop a pulsing electrical over stress testing method to simulate different electrical over stress (EOS) in CMOS integrated circuits and the tolerance values distinguished from ESD failure. The electrical and deprocessing analysis shows that pulsing EOS testing can acquire a tolerance index of integrated circuits for production quality control.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116583308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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