Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521773
A. Grunewald, K. Hahn, R. Bruck
In recent years 3D IC design and manufacturing is continuously emerging. Along with the variety of possibilities on how to vertically integrate two or more dies, many aspects including cost, design and choice of technology must be considered. Therefore a design methodology and software implementation is presented in this paper which makes use of the mutual dependency of design and process technology in order to provide a manufacturable integration flow.
{"title":"Software-based development of 3D integration flows","authors":"A. Grunewald, K. Hahn, R. Bruck","doi":"10.1109/IEMT.2012.6521773","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521773","url":null,"abstract":"In recent years 3D IC design and manufacturing is continuously emerging. Along with the variety of possibilities on how to vertically integrate two or more dies, many aspects including cost, design and choice of technology must be considered. Therefore a design methodology and software implementation is presented in this paper which makes use of the mutual dependency of design and process technology in order to provide a manufacturable integration flow.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116932209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521793
J. Lim
Delamination is very critical for Power Mosfet devices especially Die Attach (DA) delamination. This is due to drain is always connected to Die Attach Paddle (DAP) area using interconnect (soft solder or epoxy type). When there is DA delamination occuring, resistance between Drain and Source will increase causing slow switching time on Power Mosfet devices. Since delamination is very crucial for Power Mosfet, a lot of design of engineerings (DOEs) are performed using on Moisture Sensitivity Level 1 (MSL 1) to screen the delamination. However MSL 1 always takes considerable long duration (168hrs) to complete the study. Time to market release of the products will be further delayed when repeat DOE is needed. This paper will discuss correlation study between Autoclave test (ACLV) and MSL 1 in term of delamination and weight gain (moisture absorption) of mold compound been done. Three mold compounds have been selected to perform weight gain study and delamination check to correlate MSL 1 versus ACLV test. Results on correlation between MSL 1 (85/85% soaking 168 hours) versus ACLV found DOE study can be used in evaluation stage to reduce DOE duration as it is comparable.
{"title":"Correlation study on moisture soak equivalent between MSL1 (85/85% soaking 168 hours) and Autoclave test in term of weight gain and delamination","authors":"J. Lim","doi":"10.1109/IEMT.2012.6521793","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521793","url":null,"abstract":"Delamination is very critical for Power Mosfet devices especially Die Attach (DA) delamination. This is due to drain is always connected to Die Attach Paddle (DAP) area using interconnect (soft solder or epoxy type). When there is DA delamination occuring, resistance between Drain and Source will increase causing slow switching time on Power Mosfet devices. Since delamination is very crucial for Power Mosfet, a lot of design of engineerings (DOEs) are performed using on Moisture Sensitivity Level 1 (MSL 1) to screen the delamination. However MSL 1 always takes considerable long duration (168hrs) to complete the study. Time to market release of the products will be further delayed when repeat DOE is needed. This paper will discuss correlation study between Autoclave test (ACLV) and MSL 1 in term of delamination and weight gain (moisture absorption) of mold compound been done. Three mold compounds have been selected to perform weight gain study and delamination check to correlate MSL 1 versus ACLV test. Results on correlation between MSL 1 (85/85% soaking 168 hours) versus ACLV found DOE study can be used in evaluation stage to reduce DOE duration as it is comparable.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116936301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521792
Seen Fang Lee, Yingxin Goh, A. Haseeb
Eutectic Sn-Bi alloy is gaining considerable attention in the electronic packaging applications. This alloy exhibits favorable properties such as low melting temperature, good wettability, high yield strength and fracture strength at room temperature. Miniaturization of electronic devices limited the choices of deposition technique where electrodeposition is identified as one of the most suitable ones. This work focuses on the formation of eutectic Sn-Bi solder alloys by reflowing a metal stack containing sequentially electrodeposited Sn and Bi layers. Three layer sequential deposition of Sn-Bi alloys is a new attempt in the electroplating field. The effects of layer sequence on the composition and microstructure of the resulting alloy is investigated. Irrespective of the layering sequence, a homogeneous microstructure is achieved after reflow. Near-eutectic alloy of composition Sn- 54.6 wt.% Bi is obtained from this sequential plating method.
{"title":"Effects of stacking sequence of electrodeposited Sn and Bi layers on reflowed Sn-Bi solder alloys","authors":"Seen Fang Lee, Yingxin Goh, A. Haseeb","doi":"10.1109/IEMT.2012.6521792","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521792","url":null,"abstract":"Eutectic Sn-Bi alloy is gaining considerable attention in the electronic packaging applications. This alloy exhibits favorable properties such as low melting temperature, good wettability, high yield strength and fracture strength at room temperature. Miniaturization of electronic devices limited the choices of deposition technique where electrodeposition is identified as one of the most suitable ones. This work focuses on the formation of eutectic Sn-Bi solder alloys by reflowing a metal stack containing sequentially electrodeposited Sn and Bi layers. Three layer sequential deposition of Sn-Bi alloys is a new attempt in the electroplating field. The effects of layer sequence on the composition and microstructure of the resulting alloy is investigated. Irrespective of the layering sequence, a homogeneous microstructure is achieved after reflow. Near-eutectic alloy of composition Sn- 54.6 wt.% Bi is obtained from this sequential plating method.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130450565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521815
Chee Yin Khuen, Thong Kai Choh
Power device application is one of the highest growth sectors in today's semiconductor technology. The main applications for power devices are switches or rectifiers used in servers, desktops, notebook, cell phone etc. From a packaging perspective, power devices are characterised by its ability and efficiency in conducting high current. To conduct high current, a power package must have low electrical resistance and good thermal dissipation system. As such, applying solder as interconnect between the die and the leadframe or cu clips to mosfets is by far the best solution for thermal dissipation and electrical conductivity. This is because solder poses superior thermal conductivity performance (approximate 3 times better than high thermal conductive epoxy & approximate 10 times lower in terms of volume resistivity). In the industry today, typical power package that applies conductive epoxy handles about 2~16A current while package applies solder capable to handles 25~60A current. As such, solder will continue to be the preferred material over epoxy for power packages that requires high current. This paper will discuss on the challenges faced when using solder as the die attach material on leadframe based packages.
{"title":"Challenges in solder on leadframe packages","authors":"Chee Yin Khuen, Thong Kai Choh","doi":"10.1109/IEMT.2012.6521815","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521815","url":null,"abstract":"Power device application is one of the highest growth sectors in today's semiconductor technology. The main applications for power devices are switches or rectifiers used in servers, desktops, notebook, cell phone etc. From a packaging perspective, power devices are characterised by its ability and efficiency in conducting high current. To conduct high current, a power package must have low electrical resistance and good thermal dissipation system. As such, applying solder as interconnect between the die and the leadframe or cu clips to mosfets is by far the best solution for thermal dissipation and electrical conductivity. This is because solder poses superior thermal conductivity performance (approximate 3 times better than high thermal conductive epoxy & approximate 10 times lower in terms of volume resistivity). In the industry today, typical power package that applies conductive epoxy handles about 2~16A current while package applies solder capable to handles 25~60A current. As such, solder will continue to be the preferred material over epoxy for power packages that requires high current. This paper will discuss on the challenges faced when using solder as the die attach material on leadframe based packages.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128827456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521768
S. H. Liew, W. Law
Smart mobile devices such as smart phones & tablets are gaining tremendous growth in the consumer market due to their ability to offer greater functionality and ease of use such as voice and SMS coupled with mobile internet applications, multimedia functionality, high speed data processing capabilities, and inbuilt GPS capabilities, not forgetting the cm mm-sized thickness platform that makes them easily transportable, readily accompanied or even wearable. These requirements for higher integration & miniaturization drive integrated circuits (ICs) to be packaged towards thinner, smaller or more complex configurations. Multidie within a package will most likely to be the configuration used to attain higher integration. With wirebonding as still the preferred interconnection method of choice, be it between die to leadframe or die to die, these in turn drive the interconnections towards various advanced looping trajectories such as multi-height loops, long wires or ultra-low-loop. When the wire loop height gets low as in the ultra-low loop, there would be potential of the neck damage as well as wire shorting/collapsing to the surface beneath it. Looping gets even more challenging when the wire length gets longer with ultra-low loop bonding at the same time. This paper will discuss on the forming of reliable ultra-low-loop for various configurations in the QFN thin packages, eg. X2 (max0.4mm package thickness) or X3 (max 0.3mm package thickness), through the selection of wires, shapes of the loop profile, supporting tools, while maintaining high quality and reliability at post-bond and post-mold conditions. Finally, full reliability testing and qualification will be performed on the ultra-low-loop for various configurations to ensure robustness of the looping.
{"title":"Reliable ultra-low-loop bonding approach on X2/X3 thin QFN","authors":"S. H. Liew, W. Law","doi":"10.1109/IEMT.2012.6521768","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521768","url":null,"abstract":"Smart mobile devices such as smart phones & tablets are gaining tremendous growth in the consumer market due to their ability to offer greater functionality and ease of use such as voice and SMS coupled with mobile internet applications, multimedia functionality, high speed data processing capabilities, and inbuilt GPS capabilities, not forgetting the cm mm-sized thickness platform that makes them easily transportable, readily accompanied or even wearable. These requirements for higher integration & miniaturization drive integrated circuits (ICs) to be packaged towards thinner, smaller or more complex configurations. Multidie within a package will most likely to be the configuration used to attain higher integration. With wirebonding as still the preferred interconnection method of choice, be it between die to leadframe or die to die, these in turn drive the interconnections towards various advanced looping trajectories such as multi-height loops, long wires or ultra-low-loop. When the wire loop height gets low as in the ultra-low loop, there would be potential of the neck damage as well as wire shorting/collapsing to the surface beneath it. Looping gets even more challenging when the wire length gets longer with ultra-low loop bonding at the same time. This paper will discuss on the forming of reliable ultra-low-loop for various configurations in the QFN thin packages, eg. X2 (max0.4mm package thickness) or X3 (max 0.3mm package thickness), through the selection of wires, shapes of the loop profile, supporting tools, while maintaining high quality and reliability at post-bond and post-mold conditions. Finally, full reliability testing and qualification will be performed on the ultra-low-loop for various configurations to ensure robustness of the looping.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126227210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521819
M. Sabri, D. A. Shnawah, I. Badruddin, S. Said
Effects of 0.1 wt.% Al addition on the microstructural stability and mechanical properties of the low-Ag-content Sn-1Ag-0.5Cu (SAC105) solder alloy under high-temperature aging were investigated. Addition of Al suppresses the formation of Cu6Sn5 intermetallic compound (IMC) particles and leads to the formation of large AlCu IMCs. Moreover, the Ag3Sn IMC particles become larger and less-packed in the interdendritic regions after the additions of Al. The addition of Al also leads to enlarge the primary β-Sn dendrites and diminish the interdendritic regions. The tensile test results indicate that the addition of Al significantly decreases the elastic modulus, yield strength, and total elongation. After 720 h and 24 h of aging at 100°C and 180°C, respectively, the Al-bearing SAC105 solder alloy exhibits more resistance to microstructural coarsening than the SAC105 solder alloy which in turn significantly reduces the mechanical properties degradation with aging.
{"title":"Microstructural stability and mechanical properties of Sn-1Ag-0.5Cu solder alloy with 0.1 wt.% Al addition under high-temperature annealing","authors":"M. Sabri, D. A. Shnawah, I. Badruddin, S. Said","doi":"10.1109/IEMT.2012.6521819","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521819","url":null,"abstract":"Effects of 0.1 wt.% Al addition on the microstructural stability and mechanical properties of the low-Ag-content Sn-1Ag-0.5Cu (SAC105) solder alloy under high-temperature aging were investigated. Addition of Al suppresses the formation of Cu6Sn5 intermetallic compound (IMC) particles and leads to the formation of large AlCu IMCs. Moreover, the Ag3Sn IMC particles become larger and less-packed in the interdendritic regions after the additions of Al. The addition of Al also leads to enlarge the primary β-Sn dendrites and diminish the interdendritic regions. The tensile test results indicate that the addition of Al significantly decreases the elastic modulus, yield strength, and total elongation. After 720 h and 24 h of aging at 100°C and 180°C, respectively, the Al-bearing SAC105 solder alloy exhibits more resistance to microstructural coarsening than the SAC105 solder alloy which in turn significantly reduces the mechanical properties degradation with aging.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127554967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521796
N. Yap, C. Hermosura, F. Pascual
Diebond process is one of the key assembly process step in terms of defining reliability and performance of an integrated circuit, IC product. The process requires epoxy dispense accuracy and consistency to ensure that IC is secured and within the required position in the lead frame pad ready for wire bonding. These requirements though in the realm of assembly manufacturing is easier said than done. In the actual manufacturing Diebond process environment, there are several machine technologies that process different devices of IC. This complex condition coupled with increasing volume for processing was observed to be potentially related to the increase of Epoxy bridging defect. Normally a unit of IC with Epoxy bridging defect fails electrical testing as the conductive epoxy tails or spreads connecting the lead frame flag and the internal leads causing electrical short. However there are cases of very thin Epoxy bridging that can pass electrical test which has a risk of failing during application. ON Semiconductor Philippines Inc, OSPI formed a DMAIC team to immediately address opportunities in the trend of Epoxy bridging. Using the disciplined Six Sigma approach, the team identified Z level offset and Z level position as key input variable, KPIV using a resolution 4 fractional factorial design of experiment. These KPIV was found necessary as standard for all Diebond machine technologies. And even with the complexity of number of devices, with this KPIV's controlled and locked, Epoxy bridging was eliminated.
{"title":"Elimination of epoxy bridging in diebond process","authors":"N. Yap, C. Hermosura, F. Pascual","doi":"10.1109/IEMT.2012.6521796","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521796","url":null,"abstract":"Diebond process is one of the key assembly process step in terms of defining reliability and performance of an integrated circuit, IC product. The process requires epoxy dispense accuracy and consistency to ensure that IC is secured and within the required position in the lead frame pad ready for wire bonding. These requirements though in the realm of assembly manufacturing is easier said than done. In the actual manufacturing Diebond process environment, there are several machine technologies that process different devices of IC. This complex condition coupled with increasing volume for processing was observed to be potentially related to the increase of Epoxy bridging defect. Normally a unit of IC with Epoxy bridging defect fails electrical testing as the conductive epoxy tails or spreads connecting the lead frame flag and the internal leads causing electrical short. However there are cases of very thin Epoxy bridging that can pass electrical test which has a risk of failing during application. ON Semiconductor Philippines Inc, OSPI formed a DMAIC team to immediately address opportunities in the trend of Epoxy bridging. Using the disciplined Six Sigma approach, the team identified Z level offset and Z level position as key input variable, KPIV using a resolution 4 fractional factorial design of experiment. These KPIV was found necessary as standard for all Diebond machine technologies. And even with the complexity of number of devices, with this KPIV's controlled and locked, Epoxy bridging was eliminated.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131196998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521755
Chek Yean Feng
Today the device that required intensive RF testing in mass production is commonly performed using the expensive high end automated test equipment (ATE) installed with RF/microwave resources for measuring and analyzing the RF signals. We can reduce test cost if one could develop the RF test on the basic ATE without RF resources. The paper proposes a test method using the on board RF power detector to measure the RF output signal beyond 1.0GHz for a device under test (DUT) with expected power level from -5dBm to +3dBm. The proposed method has been applied to test clocking and timing devices with internal voltage control oscillator (VCO) in the production and achieved significant test time improvement.
{"title":"A cost effective method to test RF power on the ATE in manufacturing","authors":"Chek Yean Feng","doi":"10.1109/IEMT.2012.6521755","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521755","url":null,"abstract":"Today the device that required intensive RF testing in mass production is commonly performed using the expensive high end automated test equipment (ATE) installed with RF/microwave resources for measuring and analyzing the RF signals. We can reduce test cost if one could develop the RF test on the basic ATE without RF resources. The paper proposes a test method using the on board RF power detector to measure the RF output signal beyond 1.0GHz for a device under test (DUT) with expected power level from -5dBm to +3dBm. The proposed method has been applied to test clocking and timing devices with internal voltage control oscillator (VCO) in the production and achieved significant test time improvement.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"49 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521776
Lim Chuan Yik, Y. B. Kar, N. Shafika
Silver plated copper is a new developed die attachment material to replace pure silver. As year past, price of silver getting higher and become a problem for those semiconductors packaging company. Therefore, silver plated copper was developed as new die attachment material to solve the costing problem. But the characteristic and reliability of silver plated copper filler has be a doubt to replace the pure silver in the market. This paper will review few test method to test on the reliability of silver plated copper filler and proved that it is as good as silver to be the filler.
{"title":"Study on reliability test of die attach material","authors":"Lim Chuan Yik, Y. B. Kar, N. Shafika","doi":"10.1109/IEMT.2012.6521776","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521776","url":null,"abstract":"Silver plated copper is a new developed die attachment material to replace pure silver. As year past, price of silver getting higher and become a problem for those semiconductors packaging company. Therefore, silver plated copper was developed as new die attachment material to solve the costing problem. But the characteristic and reliability of silver plated copper filler has be a doubt to replace the pure silver in the market. This paper will review few test method to test on the reliability of silver plated copper filler and proved that it is as good as silver to be the filler.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"6 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131839059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521834
A. Chang, A. B. Lim, C. Lee, B. Milton, H. Clauberg, O. Yauw, B. Chylak
In this study, we experimented with palladium-coated copper (PdCu) wires of different diameters (0.6 mil, 0.7 mil and 0.8 mil) and from different manufactures. It was seen that wire diameters that varied within the manufacturing tolerances show an effect on bonding responses. The effect was especially prominent in the production environment, for example, when electric-flame-off (EFO) time remained fixed and free air ball (FAB) and subsequent bonded ball size varied according to the variation in wire diameter. The effect of Pd thickness control in PdCu wire was also studied and its implication to bonding responses is presented. Aside from the variations from the wires, bonding parameters such as EFO conditions, cover gas types, and gas flow rates were also found to affect wire bonding responses by varying degrees for wires from different suppliers. All of these observations suggest the added complications and considerations necessary when dealing with PdCu wire. Therefore, ensuring an understanding of the wire characteristics, especially pertaining to the Pd coating and their relations to wire bonding responses, is critical in overcoming these additional challenges.
{"title":"Characterization of a wire bonding process with the added challenges from palladium-coated copper wires","authors":"A. Chang, A. B. Lim, C. Lee, B. Milton, H. Clauberg, O. Yauw, B. Chylak","doi":"10.1109/IEMT.2012.6521834","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521834","url":null,"abstract":"In this study, we experimented with palladium-coated copper (PdCu) wires of different diameters (0.6 mil, 0.7 mil and 0.8 mil) and from different manufactures. It was seen that wire diameters that varied within the manufacturing tolerances show an effect on bonding responses. The effect was especially prominent in the production environment, for example, when electric-flame-off (EFO) time remained fixed and free air ball (FAB) and subsequent bonded ball size varied according to the variation in wire diameter. The effect of Pd thickness control in PdCu wire was also studied and its implication to bonding responses is presented. Aside from the variations from the wires, bonding parameters such as EFO conditions, cover gas types, and gas flow rates were also found to affect wire bonding responses by varying degrees for wires from different suppliers. All of these observations suggest the added complications and considerations necessary when dealing with PdCu wire. Therefore, ensuring an understanding of the wire characteristics, especially pertaining to the Pd coating and their relations to wire bonding responses, is critical in overcoming these additional challenges.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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