A fabless company perspective is presented on the roles of the foundries, design entities and EDA providers in the DFM arena, and the requirements for measurement of the economic benefits of DFM.
{"title":"Are there economic benefits in DFM?","authors":"M. Nowak, R. Radojcic","doi":"10.1145/1065579.1065783","DOIUrl":"https://doi.org/10.1145/1065579.1065783","url":null,"abstract":"A fabless company perspective is presented on the roles of the foundries, design entities and EDA providers in the DFM arena, and the requirements for measurement of the economic benefits of DFM.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123716877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, C. Raibaut, U. Ko
Methodology, EDA flow, scripts, and documentation play a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on leakage reduction techniques but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are implemented to build an efficient, re-usable, robust, low cost and portable platform. Techniques have been silicon proven on the 90-nm TI CMOS technology and is commonly used to design SoC with complexities over 100 million transistors.
{"title":"A design platform for 90-nm leakage reduction techniques","authors":"P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, C. Raibaut, U. Ko","doi":"10.1145/1065579.1065722","DOIUrl":"https://doi.org/10.1145/1065579.1065722","url":null,"abstract":"Methodology, EDA flow, scripts, and documentation play a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on leakage reduction techniques but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are implemented to build an efficient, re-usable, robust, low cost and portable platform. Techniques have been silicon proven on the 90-nm TI CMOS technology and is commonly used to design SoC with complexities over 100 million transistors.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem extremely difficult thereby introducing severe challenges in design and optimization. The inherent analysis complexity calls for innovations in simulation techniques that must provide appropriate accuracy, efficiency as well as the tradeoff thereof to aid design verification and optimization. In this paper, we first present a sampling-based sensitivity analysis by employing the notation of importance sampling in a Monte Carlo based circuit simulation framework. This technique allows the extraction of multi-parameter sensitivities for the node voltages of interest in the same Monte Carlo runs that are used for computing the nominal voltage values. For more efficient nonstructured whole-grid solution approaches, we further introduce a new direct solution method by embedding symbolic relaxation steps in a hierarchical fashion. As a direct method, the proposed hierarchical symbolic relaxation is suitable to both DC and transient analyses. Circuit examples are included to demonstrate the efficacy of the proposed techniques.
{"title":"Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation","authors":"Peng Li","doi":"10.1145/1065579.1065753","DOIUrl":"https://doi.org/10.1145/1065579.1065753","url":null,"abstract":"On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem extremely difficult thereby introducing severe challenges in design and optimization. The inherent analysis complexity calls for innovations in simulation techniques that must provide appropriate accuracy, efficiency as well as the tradeoff thereof to aid design verification and optimization. In this paper, we first present a sampling-based sensitivity analysis by employing the notation of importance sampling in a Monte Carlo based circuit simulation framework. This technique allows the extraction of multi-parameter sensitivities for the node voltages of interest in the same Monte Carlo runs that are used for computing the nominal voltage values. For more efficient nonstructured whole-grid solution approaches, we further introduce a new direct solution method by embedding symbolic relaxation steps in a hierarchical fashion. As a direct method, the proposed hierarchical symbolic relaxation is suitable to both DC and transient analyses. Circuit examples are included to demonstrate the efficacy of the proposed techniques.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"30 30","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114059444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Parthasarathy, Madhu K. Iyer, K. Cheng, F. Brewer
The authors presented an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). The authors used the RTL circuit structure by extending concepts from classic automatic test-pattern generation (ATPG) algorithms and interval-arithmetic to guide the search process. The idea of Boolean recursive learning was extended on predicate logic in the RTL using Boolean and interval constraint propagation in the control and data-path of the circuit. This is used as a pre-processing step to derive relations between predicate logic signals that are used to augment the search. It is demonstrated experimentally that these methods provide significant improvement over current techniques on sample benchmarks.
{"title":"Structural search for RTL with predicate learning","authors":"G. Parthasarathy, Madhu K. Iyer, K. Cheng, F. Brewer","doi":"10.1145/1065579.1065698","DOIUrl":"https://doi.org/10.1145/1065579.1065698","url":null,"abstract":"The authors presented an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). The authors used the RTL circuit structure by extending concepts from classic automatic test-pattern generation (ATPG) algorithms and interval-arithmetic to guide the search process. The idea of Boolean recursive learning was extended on predicate logic in the RTL using Boolean and interval constraint propagation in the control and data-path of the circuit. This is used as a pre-processing step to derive relations between predicate logic signals that are used to augment the search. It is demonstrated experimentally that these methods provide significant improvement over current techniques on sample benchmarks.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129566543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placement-unaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable - task graphs with hundreds of nodes are processed in a couple of minutes.
{"title":"Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration","authors":"Sudarshan Banerjee, E. Bozorgzadeh, N. Dutt","doi":"10.1145/1065579.1065667","DOIUrl":"https://doi.org/10.1145/1065579.1065667","url":null,"abstract":"Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placement-unaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable - task graphs with hundreds of nodes are processed in a couple of minutes.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128465541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
During the last decade, wireless communication has seen a trend towards application diversification leading to a significant growth in users. With the availability of - however energy-limited - nomadic devices and real-time multimedia applications, user demand is shifting from simply asking for higher data rates to more complex requirements in terms of quality of service (QoS) and energy-efficiency. In this new context energy management is becoming a key success factor. Optimized energy-efficiency requires an energy management that continuously trades off QoS and energy adapting to varying user expectations and environment dynamics. But, QoS can only be evaluated on top of the whole protocol stack while energy consumption largely appears at the lower layers. To minimize overhead during the transitions between layers, we need to address the problem from a cross-layer perspective. We present a methodology that, based on systematic exploration, effective problem partitioning and minimal cross-layer interface, allows energy management in a cross-layer way, while maintaining efficient layered semantics. Different case studies in the context of wireless LAN (WLAN) for multimedia and data traffic transport are discussed, to show how cross-layer energy management can easily be included in systems running state-of-the-art protocols.
{"title":"From myth to methodology: cross-layer design for energy-efficient wireless communication","authors":"W. Eberle, B. Bougard, S. Pollin, F. Catthoor","doi":"10.1145/1065579.1065659","DOIUrl":"https://doi.org/10.1145/1065579.1065659","url":null,"abstract":"During the last decade, wireless communication has seen a trend towards application diversification leading to a significant growth in users. With the availability of - however energy-limited - nomadic devices and real-time multimedia applications, user demand is shifting from simply asking for higher data rates to more complex requirements in terms of quality of service (QoS) and energy-efficiency. In this new context energy management is becoming a key success factor. Optimized energy-efficiency requires an energy management that continuously trades off QoS and energy adapting to varying user expectations and environment dynamics. But, QoS can only be evaluated on top of the whole protocol stack while energy consumption largely appears at the lower layers. To minimize overhead during the transitions between layers, we need to address the problem from a cross-layer perspective. We present a methodology that, based on systematic exploration, effective problem partitioning and minimal cross-layer interface, allows energy management in a cross-layer way, while maintaining efficient layered semantics. Different case studies in the context of wireless LAN (WLAN) for multimedia and data traffic transport are discussed, to show how cross-layer energy management can easily be included in systems running state-of-the-art protocols.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128584981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are -1.3% and -4.1%.
{"title":"Full-chip analysis of leakage power under process variations, including spatial correlations","authors":"Hongliang Chang, S. Sapatnekar","doi":"10.1145/1065579.1065716","DOIUrl":"https://doi.org/10.1145/1065579.1065716","url":null,"abstract":"In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are -1.3% and -4.1%.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128995967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. The authors presented an integer linear programming (ILP) model that could be used to minimize the testing time for small problem instances. An efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances was also presented. Compared to recent work on wrapper design using a single shift frequency, lower testing times were obtained and the reduction in testing time is especially significant under power constraints.
{"title":"Multi-frequency wrapper design and optimization for embedded cores under average power constraints","authors":"Q. Xu, N. Nicolici, K. Chakrabarty","doi":"10.1145/1065579.1065615","DOIUrl":"https://doi.org/10.1145/1065579.1065615","url":null,"abstract":"This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. The authors presented an integer linear programming (ILP) model that could be used to minimize the testing time for small problem instances. An efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances was also presented. Compared to recent work on wrapper design using a single shift frequency, lower testing times were obtained and the reduction in testing time is especially significant under power constraints.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130622209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a number of independent design parameters and each parameter can vary in a large numeric range. On the other hand, these requirements can cause a large percentage of functionally incorrect designs in the design space and thus results in a sparse feasible design space. They also complicate the mathematical relationship between the performance parameters and the design parameters. In order to tackle these challenges, this paper presents a combined feasibility and performance macromodel based on support vector machines (SVMs). The feasibility model identifies the feasible designs that satisfy the design constraints. The performance macromodel is valid for feasible designs. Feasibility macromodeling is formulated as a classification problem while performance macromelting as a regression problem. An active learning scheme (Ding, et al., 2005) has been applied to improve the accuracy of the feasibility model much faster than only using uniformly distributed designs in the entire design space. The experiment of the authors showed that the performance macromodels in the feasible design space are more accurate and faster to construct and evaluate than performance macromodels in the entire design space without functional or performance constraints considered.
重用模拟电路拓扑的性能宏模型的需求对现有的基于回归的建模技术提出了挑战。具有良好可重用性的模型应该具有许多独立的设计参数，并且每个参数可以在很大的数值范围内变化。另一方面，这些需求可能导致设计空间中很大比例的功能不正确的设计，从而导致稀疏的可行设计空间。它们还使性能参数与设计参数之间的数学关系复杂化。为了解决这些问题，本文提出了一种基于支持向量机(svm)的可行性与性能相结合的宏模型。可行性模型识别满足设计约束的可行设计。性能宏模型对于可行的设计是有效的。可行性宏建模是一个分类问题，而性能宏建模是一个回归问题。一种主动学习方案(Ding, et al.， 2005)被应用于提高可行性模型的准确性，比在整个设计空间中只使用均匀分布的设计要快得多。实验表明，在可行设计空间中的性能宏模型比在不考虑功能或性能约束的整个设计空间中的性能宏模型更准确、更快地构建和评估。
{"title":"A combined feasibility and performance macromodel for analog circuits","authors":"Mengmeng Ding, R. Vemuri","doi":"10.1145/1065579.1065600","DOIUrl":"https://doi.org/10.1145/1065579.1065600","url":null,"abstract":"The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a number of independent design parameters and each parameter can vary in a large numeric range. On the other hand, these requirements can cause a large percentage of functionally incorrect designs in the design space and thus results in a sparse feasible design space. They also complicate the mathematical relationship between the performance parameters and the design parameters. In order to tackle these challenges, this paper presents a combined feasibility and performance macromodel based on support vector machines (SVMs). The feasibility model identifies the feasible designs that satisfy the design constraints. The performance macromodel is valid for feasible designs. Feasibility macromodeling is formulated as a classification problem while performance macromelting as a regression problem. An active learning scheme (Ding, et al., 2005) has been applied to improve the accuracy of the feasibility model much faster than only using uniformly distributed designs in the entire design space. The experiment of the authors showed that the performance macromodels in the feasible design space are more accurate and faster to construct and evaluate than performance macromodels in the entire design space without functional or performance constraints considered.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121133962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
From the IC industry's standpoint, the incubation of formal methods for deployment in EDA verification flows has been very long and is still occurring. Formal methods applied at functional verification have interpreted different roles and finally have federated with simulation for the purpose of achieving coverage closure. Commercially available IP's and custom IP's have very often been exposed to sneaky bugs. Having correct IP's is not enough for verifying the correctness of the whole system. Formal methods have to extend their effectiveness by including the so called transactional level models (TLM) in their analysis, that abstract the mechanisms that SoC blocks use to communicate and synchronize among themselves. Two major problems have to be faced: the first is that TLM includes a range of abstraction levels and the second is that a mapping between TLM assertions and RTL assertions should be provided and formally proven.
{"title":"Can we really do without the support of formal methods in the verification of large designs?","authors":"U. Rossi","doi":"10.1145/1065579.1065756","DOIUrl":"https://doi.org/10.1145/1065579.1065756","url":null,"abstract":"From the IC industry's standpoint, the incubation of formal methods for deployment in EDA verification flows has been very long and is still occurring. Formal methods applied at functional verification have interpreted different roles and finally have federated with simulation for the purpose of achieving coverage closure. Commercially available IP's and custom IP's have very often been exposed to sneaky bugs. Having correct IP's is not enough for verifying the correctness of the whole system. Formal methods have to extend their effectiveness by including the so called transactional level models (TLM) in their analysis, that abstract the mechanisms that SoC blocks use to communicate and synchronize among themselves. Two major problems have to be faced: the first is that TLM includes a range of abstraction levels and the second is that a mapping between TLM assertions and RTL assertions should be provided and formally proven.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128053641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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