Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194508
G. Stopponi, L. Roselli, S. Buonincontri, P. Ciampolini
A high-frequency circuit simulation technique is presented, based on the selfconsistent, coordinated solution of Maxwell’s equation and semiconductor device equations. This makes it possible to evaluate signal propagation along arbitrary network, including non-linear devices. Distributed device simulation is exploited, allowing actual fabrication-technology parameters to be taken into account. Charge-transport properties of GaAs are considered, and the simulation of a Gunn-diode based oscillator, working in the 20 GHz range, is illustrated. Introduction GaAs Gunn devices are customarily used for the implementation of microwave and millimeter-wave oscillators. An accurate analysis of such kind of circuits poses a number of challenging problems: the operating mode of Gunn-diode based harmonic oscillators, in fact, inherently involves quite complex charge transfer mechanisms, occurring within the solidstate device, and, at the same time, strongly depends on the electromagnetic propagation effects in the surrounding circuit. In this summary, a comprehensive circuit-simulation technique is presented, which selfconsistently takes into account the charge-transport properties of GaAs (by means of numerical device-simulation algorithms) and the details of fi eldpropagation along the passive network. The approach described in [1] has been extended here to GaAs devices, and applied to the analysis of an active antenna exploiting a Gunn diode. Analysis method The simulation scheme can be regarded as an extension of the Lumped-Element FiniteDifference Time-Domain algorithm [2]. In most devices of practical interest, the activedevice size is small, compared with signal wavelength, so that EM-fi eldpropagation can be neglected within the device itself; under such an assumption, two sets of equations are then to be almost independently solved: namely, a full-wave solution of Maxwell’s equations is obtained on the passive network domain, whereas quasi-stationary device equations describe the lumped-element behavior. Interaction between the device(s) and the passive network is accounted for by means of proper formulation of boundary conditions for both systems. Compact device models can be incorporated along the lines described in [3], while in [1] distributed modeling of silicon solid-state device has been introduced. To this purpose, transport equations (in the drift-diffusion approximation) are discretized and numerically solved over a distributed domain[4]. Here, the method is extended to GaAs by accounting for the empirical relationship among electric fi eldand electron mobility [5]: The expression above has been discretized and incorporated into the mixed-mode simulation code. Simulation results The structure sketched in Fig. 1 has been simulated; it consists of a single element of an array antenna, fabricated by etching the metalization plane of a single-side, copper-plated substrate. An aperture of 27.5 0.8 mm is obtained, across which a GaAs Gunn diode is
{"title":"Circuit simulation through coordinated EM and solid-state device numerical analyses","authors":"G. Stopponi, L. Roselli, S. Buonincontri, P. Ciampolini","doi":"10.1109/ESSDERC.1997.194508","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194508","url":null,"abstract":"A high-frequency circuit simulation technique is presented, based on the selfconsistent, coordinated solution of Maxwell’s equation and semiconductor device equations. This makes it possible to evaluate signal propagation along arbitrary network, including non-linear devices. Distributed device simulation is exploited, allowing actual fabrication-technology parameters to be taken into account. Charge-transport properties of GaAs are considered, and the simulation of a Gunn-diode based oscillator, working in the 20 GHz range, is illustrated. Introduction GaAs Gunn devices are customarily used for the implementation of microwave and millimeter-wave oscillators. An accurate analysis of such kind of circuits poses a number of challenging problems: the operating mode of Gunn-diode based harmonic oscillators, in fact, inherently involves quite complex charge transfer mechanisms, occurring within the solidstate device, and, at the same time, strongly depends on the electromagnetic propagation effects in the surrounding circuit. In this summary, a comprehensive circuit-simulation technique is presented, which selfconsistently takes into account the charge-transport properties of GaAs (by means of numerical device-simulation algorithms) and the details of fi eldpropagation along the passive network. The approach described in [1] has been extended here to GaAs devices, and applied to the analysis of an active antenna exploiting a Gunn diode. Analysis method The simulation scheme can be regarded as an extension of the Lumped-Element FiniteDifference Time-Domain algorithm [2]. In most devices of practical interest, the activedevice size is small, compared with signal wavelength, so that EM-fi eldpropagation can be neglected within the device itself; under such an assumption, two sets of equations are then to be almost independently solved: namely, a full-wave solution of Maxwell’s equations is obtained on the passive network domain, whereas quasi-stationary device equations describe the lumped-element behavior. Interaction between the device(s) and the passive network is accounted for by means of proper formulation of boundary conditions for both systems. Compact device models can be incorporated along the lines described in [3], while in [1] distributed modeling of silicon solid-state device has been introduced. To this purpose, transport equations (in the drift-diffusion approximation) are discretized and numerically solved over a distributed domain[4]. Here, the method is extended to GaAs by accounting for the empirical relationship among electric fi eldand electron mobility [5]: The expression above has been discretized and incorporated into the mixed-mode simulation code. Simulation results The structure sketched in Fig. 1 has been simulated; it consists of a single element of an array antenna, fabricated by etching the metalization plane of a single-side, copper-plated substrate. An aperture of 27.5 0.8 mm is obtained, across which a GaAs Gunn diode is","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115389431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194442
N. Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, C. Claeys
In this paper,for the first time, a systematic study of the Random Telegraph Signal (RTS)jlitctuations in submicron W-array n-MOSFEI's is reported. It is shown that besides the classical channel-related RTS another type ocCurs, which is associated with the source or drain contact. Secondly, a new way of measuring the RTS is introduced for such signals, whereby the transistor is biased in the forward drain-substrate diode configuration. The available experimental evidence strongly suggests that the underlying oxide defects are lying in the transition region between the gate oxide and the field oxide, i.e. at the bird's beak of the structure.
{"title":"RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs","authors":"N. Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, C. Claeys","doi":"10.1109/ESSDERC.1997.194442","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194442","url":null,"abstract":"In this paper,for the first time, a systematic study of the Random Telegraph Signal (RTS)jlitctuations in submicron W-array n-MOSFEI's is reported. It is shown that besides the classical channel-related RTS another type ocCurs, which is associated with the source or drain contact. Secondly, a new way of measuring the RTS is introduced for such signals, whereby the transistor is biased in the forward drain-substrate diode configuration. The available experimental evidence strongly suggests that the underlying oxide defects are lying in the transition region between the gate oxide and the field oxide, i.e. at the bird's beak of the structure.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117346233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194395
L. D. de Vreede, W. V. Noort, H. de Graaff, J. Tauritz, J. Slotboom
{"title":"MAIDS: A Microwave Active Integral Device Simulator","authors":"L. D. de Vreede, W. V. Noort, H. de Graaff, J. Tauritz, J. Slotboom","doi":"10.1109/ESSDERC.1997.194395","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194395","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194450
M. Kerber, U. Schwalke, R. Heinrich
A low cost CMOS process flow is proposed which unifies all implantations to form NMOS and PMOS devices in a single mask step for each transistor type. This reduces the total mask count by three and hence cost and processing time accordingly. Experimental results demonstrate electrical performance comparable to conventional CMOS technologies.
{"title":"Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme","authors":"M. Kerber, U. Schwalke, R. Heinrich","doi":"10.1109/ESSDERC.1997.194450","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194450","url":null,"abstract":"A low cost CMOS process flow is proposed which unifies all implantations to form NMOS and PMOS devices in a single mask step for each transistor type. This reduces the total mask count by three and hence cost and processing time accordingly. Experimental results demonstrate electrical performance comparable to conventional CMOS technologies.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126057405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194408
J. Son, S. Lee, K. Huh, W. Yang, Y. Lee, J. Hwang
Suppression of short channel effect (SCE) is one of the key technology for deep submicron CMOS. Surface channel (SC) pMOSFET with p polysilicon has been known as a good candidate to improve SCE while BC pMOSFET has poor SCE. However, SC pMOSFET has several disadvantages, for example, process complexity, boron penetration, and low hole mobility. Especially, gate depletion, which degrades drive current, due to insufficient polysilicon doping becomes more severe for thin gate oxide. Therefore the use of BC pMOSFET is profitable if SCE of BC pMOSFET can be sufficiently reduced. In recent, many of technologies have been proposed to suppress SCE in BC pMOSFET. A 0.15 BC pMOSFET with conventional arsenic punchthrough stopper [1], tilt implanted punchthrough stopper [2], and co-implanted punchthrough stopper with arsenic and phosphorous [3] have been reported. In this report, double arsenic punchthrough stopper (DAPS) is proposed to improve SCE in BC pMOSFET and compared with the conventional structure and the tilt implanted punchthrough stopper structure by using arsenic.
{"title":"New anti-punchthrough design for buried channel PMOSFET","authors":"J. Son, S. Lee, K. Huh, W. Yang, Y. Lee, J. Hwang","doi":"10.1109/ESSDERC.1997.194408","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194408","url":null,"abstract":"Suppression of short channel effect (SCE) is one of the key technology for deep submicron CMOS. Surface channel (SC) pMOSFET with p polysilicon has been known as a good candidate to improve SCE while BC pMOSFET has poor SCE. However, SC pMOSFET has several disadvantages, for example, process complexity, boron penetration, and low hole mobility. Especially, gate depletion, which degrades drive current, due to insufficient polysilicon doping becomes more severe for thin gate oxide. Therefore the use of BC pMOSFET is profitable if SCE of BC pMOSFET can be sufficiently reduced. In recent, many of technologies have been proposed to suppress SCE in BC pMOSFET. A 0.15 BC pMOSFET with conventional arsenic punchthrough stopper [1], tilt implanted punchthrough stopper [2], and co-implanted punchthrough stopper with arsenic and phosphorous [3] have been reported. In this report, double arsenic punchthrough stopper (DAPS) is proposed to improve SCE in BC pMOSFET and compared with the conventional structure and the tilt implanted punchthrough stopper structure by using arsenic.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125474373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194441
D. Schumann, R. Krieg, H. Schaefer, U. Schwalke
nMOSFETs with elevated S/D structures were fabricated by selective epitaxial growth of in-situ doped S/D regions. Variation of the total thermal budget allowed the optimization of outdiffusion from the epi-Si with respect to the realization of shallow junctions. For all process conditions investigated the Reverse Short Channel Effect (RSCE) was completely suppressed indicating that the RSCE observed for conventional processed nMOSFETs has to be attributed to S/D implantation. The process presented allows a realization of typical advantages for elevated S/D structures with an optimized Vth roll-off.
{"title":"Suppression of the Reverse Short Channel Effect in (Sub-)0.25um nMOSFETs using elevated S/D structures","authors":"D. Schumann, R. Krieg, H. Schaefer, U. Schwalke","doi":"10.1109/ESSDERC.1997.194441","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194441","url":null,"abstract":"nMOSFETs with elevated S/D structures were fabricated by selective epitaxial growth of in-situ doped S/D regions. Variation of the total thermal budget allowed the optimization of outdiffusion from the epi-Si with respect to the realization of shallow junctions. For all process conditions investigated the Reverse Short Channel Effect (RSCE) was completely suppressed indicating that the RSCE observed for conventional processed nMOSFETs has to be attributed to S/D implantation. The process presented allows a realization of typical advantages for elevated S/D structures with an optimized Vth roll-off.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122783627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194389
W. Beckenbaugh
{"title":"Semiconductor Packaging and New Packaging Concepts","authors":"W. Beckenbaugh","doi":"10.1109/ESSDERC.1997.194389","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194389","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129831699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194491
S. Biesemans, S. Simoen, S. Kubicek, K. De Meyer, C. Claeys
{"title":"The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K","authors":"S. Biesemans, S. Simoen, S. Kubicek, K. De Meyer, C. Claeys","doi":"10.1109/ESSDERC.1997.194491","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194491","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124602426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194382
K. Nieuwesteeg, A. van Ommen
Today the cathode-ray tube (CRT), stemming from a well-known branch of vacuum electron devices, dominates the display market. However, through the maturing of active-matrix addressed liquid crystal displays, semiconductor technology has made its way into display applications that have until recently been reserved to CRTs. Amorphous silicon based thin film transistors (TFTs) are predominantly used as devices for driving the picture elements (pixels). Future developments regarding material and device structures are described. Based on these developments and strong investments in processing equipment and productivity, it is believed that LCD technology will penetrate display applications ranging from personal digital assistants and digital cameras to . on-vehicle use and desk-top monitors,. Display diagonals will range between 1 and 40 inches are possible, commercially reaching 21-inch before the year 2000.
{"title":"AM-LCDs bring solid-state devices to the display","authors":"K. Nieuwesteeg, A. van Ommen","doi":"10.1109/ESSDERC.1997.194382","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194382","url":null,"abstract":"Today the cathode-ray tube (CRT), stemming from a well-known branch of vacuum electron devices, dominates the display market. However, through the maturing of active-matrix addressed liquid crystal displays, semiconductor technology has made its way into display applications that have until recently been reserved to CRTs. Amorphous silicon based thin film transistors (TFTs) are predominantly used as devices for driving the picture elements (pixels). Future developments regarding material and device structures are described. Based on these developments and strong investments in processing equipment and productivity, it is believed that LCD technology will penetrate display applications ranging from personal digital assistants and digital cameras to . on-vehicle use and desk-top monitors,. Display diagonals will range between 1 and 40 inches are possible, commercially reaching 21-inch before the year 2000.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126759452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/ESSDERC.1997.194524
S. Renn, J. Pelloie, F. Balestra
Hot-carrier effects are thoroughly investigated in deep submicron Nand P-channel SOI MOSFET. A saturation phenomenon relative to the initial power time-dependent law can be observed for long stress time. In this paper, various lifetime prediction methods in the saturation regime are proposed and compared. The gate length dependence of the maximal drain biases in order to obtain a 10 years lifetime is also addressed with these various extrapolation techniques.
{"title":"On the determination of the time-dependent degradation laws in deep submicron SOI MOSFETs","authors":"S. Renn, J. Pelloie, F. Balestra","doi":"10.1109/ESSDERC.1997.194524","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194524","url":null,"abstract":"Hot-carrier effects are thoroughly investigated in deep submicron Nand P-channel SOI MOSFET. A saturation phenomenon relative to the initial power time-dependent law can be observed for long stress time. In this paper, various lifetime prediction methods in the saturation regime are proposed and compared. The gate length dependence of the maximal drain biases in order to obtain a 10 years lifetime is also addressed with these various extrapolation techniques.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123934699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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