Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229667
V. Rossi, Cristina Somma, Giovanni Graziosi, Aurora Sanna
In the most advanced automotive applications, where high frequency signals, design density, high pin-count, miniaturization and integration dominate the scene, the use of Ball Grid Array (BGA) package is necessary to guarantee an excellent performance of devices. This is possible thanks to the higher design flexibility and the compatibility with advanced interconnection technologies like Flip Chip (FC), that allow shorter overall connections inside IC–Package systems. In this context, the trade-off between performance and production costs must be deeply analyzed, in order to drive the choice of materials and technologies to be used for substrates, which represent a significant cost factor in laminate-based packages. This work describes the comparative analysis between a 4-layer and a 6-layer stack-up on a BGA package designed for the same Double Data Rate 3 (DDR3) high speed interface for automotive application. The applied technology combines Flip Chip Solder Bump (FCSB) and High Density Interconnect (HDI) substrate, that uses blind and buried vias. The comparison involves multiple aspects, starting from pre-layout analysis, to the different strategies used during the design implementation, to the Signal Integrity (SI) and Power Integrity (PI) electrical performance. In this field of applications, packages with at least 4-layer substrates are recommended in order to use an optimized microstrip signal-routing with a solid ground reference and dedicate one metal layer to the different power domains. This design strategy helps both SI and PI efficiency. However, 6-layer substrates, despite the additional cost, give a further improvement: for high density signal-routing, the higher flexibility in terms of layers assignment allows an efficient stripline configuration. This leads to enhanced SI parameters (Insertion and Reflection Losses, Crosstalk), while keeping similar advantages in terms of PI. In this analysis, it will also be shown, for both substrates, how Power Integrity can be improved by using Surface Mounting Technology (SMT) decoupling capacitors. The results of SI and PI that will be discussed are obtained by electrical simulations: this permits to quantify the differences between the design strategies considering the operating frequencies of the DDR3 interface.
{"title":"BGA Package for DDR3 Interface – 4 vs 6 Layers Design Strategy and Electrical Performance Comparison","authors":"V. Rossi, Cristina Somma, Giovanni Graziosi, Aurora Sanna","doi":"10.1109/ESTC48849.2020.9229667","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229667","url":null,"abstract":"In the most advanced automotive applications, where high frequency signals, design density, high pin-count, miniaturization and integration dominate the scene, the use of Ball Grid Array (BGA) package is necessary to guarantee an excellent performance of devices. This is possible thanks to the higher design flexibility and the compatibility with advanced interconnection technologies like Flip Chip (FC), that allow shorter overall connections inside IC–Package systems. In this context, the trade-off between performance and production costs must be deeply analyzed, in order to drive the choice of materials and technologies to be used for substrates, which represent a significant cost factor in laminate-based packages. This work describes the comparative analysis between a 4-layer and a 6-layer stack-up on a BGA package designed for the same Double Data Rate 3 (DDR3) high speed interface for automotive application. The applied technology combines Flip Chip Solder Bump (FCSB) and High Density Interconnect (HDI) substrate, that uses blind and buried vias. The comparison involves multiple aspects, starting from pre-layout analysis, to the different strategies used during the design implementation, to the Signal Integrity (SI) and Power Integrity (PI) electrical performance. In this field of applications, packages with at least 4-layer substrates are recommended in order to use an optimized microstrip signal-routing with a solid ground reference and dedicate one metal layer to the different power domains. This design strategy helps both SI and PI efficiency. However, 6-layer substrates, despite the additional cost, give a further improvement: for high density signal-routing, the higher flexibility in terms of layers assignment allows an efficient stripline configuration. This leads to enhanced SI parameters (Insertion and Reflection Losses, Crosstalk), while keeping similar advantages in terms of PI. In this analysis, it will also be shown, for both substrates, how Power Integrity can be improved by using Surface Mounting Technology (SMT) decoupling capacitors. The results of SI and PI that will be discussed are obtained by electrical simulations: this permits to quantify the differences between the design strategies considering the operating frequencies of the DDR3 interface.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"3 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75431513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229654
Oliver Albrecht, K. Meier, H. Wohlrabe
The coplanarity of printed circuit boards (PCBs) and surface mount technology packages (e.g. BGAs, LGAs, FCCSPs) is a notable characteristic. It depends on the warpage of the PCBs and the packages which itself is caused by their heterogeneous buildup. BGAs are known to be susceptible to component warpage. In order to this, various BGA solder joint configurations were designed und investigated. This paper will describe a design approach for a reliability test board with respect to different warpage levels – during soldering as well as under temperature shock testing conditions – and the implementation of an electric test environment for a real IC BGA package. First results show that the coplanarity after soldering is mainly influenced by the PCB. Further, different coplanarities cause different and partially unknown damage pictures due to a combination of tensile, compressive and shear stress in BGA solder joints under alternating temperature loads.
{"title":"Study on the Effect of the Warpage of Electronic Assemblies on Their Reliability","authors":"Oliver Albrecht, K. Meier, H. Wohlrabe","doi":"10.1109/ESTC48849.2020.9229654","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229654","url":null,"abstract":"The coplanarity of printed circuit boards (PCBs) and surface mount technology packages (e.g. BGAs, LGAs, FCCSPs) is a notable characteristic. It depends on the warpage of the PCBs and the packages which itself is caused by their heterogeneous buildup. BGAs are known to be susceptible to component warpage. In order to this, various BGA solder joint configurations were designed und investigated. This paper will describe a design approach for a reliability test board with respect to different warpage levels – during soldering as well as under temperature shock testing conditions – and the implementation of an electric test environment for a real IC BGA package. First results show that the coplanarity after soldering is mainly influenced by the PCB. Further, different coplanarities cause different and partially unknown damage pictures due to a combination of tensile, compressive and shear stress in BGA solder joints under alternating temperature loads.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"242 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74727992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229711
P. Knoch, K. Meier, M. Luniak, Maria Esche, K. Bock
This work focuses on the development of a silkscreen printing process to be applied for the manufacturing of sensors based on ultra-thin glass substrates. The main target of this project consists in the development of technologies for mechanical flexible electronics and sensors to be used for high temperature fuel cells application. The challenges in this application case exist in harsh environmental conditions and a very low thickness of the sensor. Sensors are required to operate at harsh environmental conditions including chemically reactive ambient and use temperatures above 400 °C. To meet the spatial requirements in fuel cells, a sensor must be thinner than 250 µm. To transfer the deposition technology and the manufacturing on Roll-2-Roll processes is another request of this project. In a first step, a temperature-sensor was designed and tested under atmospheric conditions at 450 °C. The sensor was proven to sustain functional at temperatures of up to 450 °C for test durations of 60 h. Sensors which meet the described requirements and can be manufactured cost-effectively in Roll-2-Roll processes are certainly of interest for many other areas of application.
{"title":"Ultra-Thin Glass Based Temperature Sensor Package for High Temperature Applications","authors":"P. Knoch, K. Meier, M. Luniak, Maria Esche, K. Bock","doi":"10.1109/ESTC48849.2020.9229711","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229711","url":null,"abstract":"This work focuses on the development of a silkscreen printing process to be applied for the manufacturing of sensors based on ultra-thin glass substrates. The main target of this project consists in the development of technologies for mechanical flexible electronics and sensors to be used for high temperature fuel cells application. The challenges in this application case exist in harsh environmental conditions and a very low thickness of the sensor. Sensors are required to operate at harsh environmental conditions including chemically reactive ambient and use temperatures above 400 °C. To meet the spatial requirements in fuel cells, a sensor must be thinner than 250 µm. To transfer the deposition technology and the manufacturing on Roll-2-Roll processes is another request of this project. In a first step, a temperature-sensor was designed and tested under atmospheric conditions at 450 °C. The sensor was proven to sustain functional at temperatures of up to 450 °C for test durations of 60 h. Sensors which meet the described requirements and can be manufactured cost-effectively in Roll-2-Roll processes are certainly of interest for many other areas of application.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78439874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229716
Han He, Xiaochen Chen, Zahangir Khan, L. Sydänheimo, L. Ukkonen, Jiahui Li, H. Nishikawa, J. Virkki
In this paper, the manufacturing parameters of a passive ultra-high frequency (UHF) radio frequency identification (RFID)-based air humidity sensor were studied and optimized to reach the highest sensing ability. The sensor is fabricated by 3D printing combined with embroidering technology. In a high humidity environment, the sensor tag permanently changes its shape from flat to curved, which has a significant effect on the sensor tag read range and received signal strength indicator (RSSI) value. By modifying the infill percentage of the 3D-printed pattern and the stretching percentage of the elastic textile, the curving of the sensor tag can be modified. Based on the study, the stretching percentage of the elastic textile has the most significant influence on the sensor performance. As a result, the wireless performance of the sensor tag with optimized manufacturing parameters has a significant change in curvature after exposure to 60 % relative humidity for one hour. This passive sensor can provide cost-effective and flexible monitoring of air humidity for versatile application fields.
{"title":"Textile-based Passive Sensor for Air Humidity","authors":"Han He, Xiaochen Chen, Zahangir Khan, L. Sydänheimo, L. Ukkonen, Jiahui Li, H. Nishikawa, J. Virkki","doi":"10.1109/ESTC48849.2020.9229716","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229716","url":null,"abstract":"In this paper, the manufacturing parameters of a passive ultra-high frequency (UHF) radio frequency identification (RFID)-based air humidity sensor were studied and optimized to reach the highest sensing ability. The sensor is fabricated by 3D printing combined with embroidering technology. In a high humidity environment, the sensor tag permanently changes its shape from flat to curved, which has a significant effect on the sensor tag read range and received signal strength indicator (RSSI) value. By modifying the infill percentage of the 3D-printed pattern and the stretching percentage of the elastic textile, the curving of the sensor tag can be modified. Based on the study, the stretching percentage of the elastic textile has the most significant influence on the sensor performance. As a result, the wireless performance of the sensor tag with optimized manufacturing parameters has a significant change in curvature after exposure to 60 % relative humidity for one hour. This passive sensor can provide cost-effective and flexible monitoring of air humidity for versatile application fields.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87907491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229840
L. Lorenz, Florian Hanesch, K. Nieweglowski, Y. Eiche, J. Franke, G. Hoffmann, L. Overmeyer, K. Bock
The development of easy-to-use optical bus-systems without the need for waveguide interruption is one important step to establish optical interconnects in short- to midrange networks. The challenge from the packaging side of view is the three-dimensional integration of optical parts and waveguides to a novel kind of package, called 3D-Opto-MID. In this article, we present an approach for stereolithographic printed, three-dimensional polymer structures on ceramic thick-film substrates. Thus, we are able to combine the design freedom of 3D printing with the excellent RF- and heat-management properties of the thick-film technology, especially important for electro-optical (e/o) converters. On the three-dimensional structures, the waveguides for the bus-coupler are applied, while the ceramic holds the electro optical converters. Furthermore, the 3D printing allows for easily manufactured alignment- and fixing structures for the coupler with a high accuracy. The results section shows the analysis of the adhesion behavior of the printed polymer on the ceramic, as well as the obtainable tolerances with the printed alignment structures. The average accuracy of the alignment was measured with 31.1µm, which is sufficient for the used 200 µm multimode waveguides. Furthermore, we demonstrate the functionality of the optical path of the module assembly, as well as the coupling to a bus waveguide, which proves the success of the 3D-Opto-MID integration.
{"title":"3D-Opto-MID for Asymmetric Optical Bus Couplers","authors":"L. Lorenz, Florian Hanesch, K. Nieweglowski, Y. Eiche, J. Franke, G. Hoffmann, L. Overmeyer, K. Bock","doi":"10.1109/ESTC48849.2020.9229840","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229840","url":null,"abstract":"The development of easy-to-use optical bus-systems without the need for waveguide interruption is one important step to establish optical interconnects in short- to midrange networks. The challenge from the packaging side of view is the three-dimensional integration of optical parts and waveguides to a novel kind of package, called 3D-Opto-MID. In this article, we present an approach for stereolithographic printed, three-dimensional polymer structures on ceramic thick-film substrates. Thus, we are able to combine the design freedom of 3D printing with the excellent RF- and heat-management properties of the thick-film technology, especially important for electro-optical (e/o) converters. On the three-dimensional structures, the waveguides for the bus-coupler are applied, while the ceramic holds the electro optical converters. Furthermore, the 3D printing allows for easily manufactured alignment- and fixing structures for the coupler with a high accuracy. The results section shows the analysis of the adhesion behavior of the printed polymer on the ceramic, as well as the obtainable tolerances with the printed alignment structures. The average accuracy of the alignment was measured with 31.1µm, which is sufficient for the used 200 µm multimode waveguides. Furthermore, we demonstrate the functionality of the optical path of the module assembly, as well as the coupling to a bus waveguide, which proves the success of the 3D-Opto-MID integration.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"143 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86192455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229754
R. Juric, K. McClenaghan, K. Enger
An ad-hoc creation of situations where interconnected and movable devices, often empowered with computational capabilities, create instances of Internet-of-Everything, (IoE) has become common. The examples range from autonomous vehicles on our roads and unmanned movable objects, designed for a variety of tasks, to internet of biomedical devices, wearable robotics and digital therapeutics. In all these examples, we create computational models and solutions, which enable inter-operation between devices, and secure the accomplishment of various tasks. However, computational models in such environments are highly influenced by physical devices, which either generate data and feed our computations, or perform "action(s)" according to results of computing. Computations and devices do not exist in isolation; they are interwoven and influence each other, even if we see them as belonging to two different worlds. Design decision and manufacturing of a device may have implications on types of computing we could perform with them, and thus affect the performance of an instance of IoE, as a cyber-physical space. The same is true for software abstractions and models. We expect that data should be available or delivered by devices, and computations should be accommodated by at least partially, if not completely by these devices. In this study, we illustrate the interference or an impact of engineering practices and design of wearable devices, including wearable robotics, with/on computational power these devices may or should have. We debate the way of enhancing the both: device manufacturing and creation of software where these wearable devices perform a crucial role. The purpose of this study is to open discussions towards intelligent engineering, where the purpose and usefulness of devices are jointly decided, during their design, by both engineers and computer scientists. By understanding the impact of engineering design decisions to potential computational power of cyber physical spaces, such as IoE, we should be able to create more efficient operational IoE, which will be more manageable and might meet our expectations.
{"title":"Building Computationally Intensive Internet-of-Everything through Synergy of Engineering and Computer Science","authors":"R. Juric, K. McClenaghan, K. Enger","doi":"10.1109/ESTC48849.2020.9229754","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229754","url":null,"abstract":"An ad-hoc creation of situations where interconnected and movable devices, often empowered with computational capabilities, create instances of Internet-of-Everything, (IoE) has become common. The examples range from autonomous vehicles on our roads and unmanned movable objects, designed for a variety of tasks, to internet of biomedical devices, wearable robotics and digital therapeutics. In all these examples, we create computational models and solutions, which enable inter-operation between devices, and secure the accomplishment of various tasks. However, computational models in such environments are highly influenced by physical devices, which either generate data and feed our computations, or perform \"action(s)\" according to results of computing. Computations and devices do not exist in isolation; they are interwoven and influence each other, even if we see them as belonging to two different worlds. Design decision and manufacturing of a device may have implications on types of computing we could perform with them, and thus affect the performance of an instance of IoE, as a cyber-physical space. The same is true for software abstractions and models. We expect that data should be available or delivered by devices, and computations should be accommodated by at least partially, if not completely by these devices. In this study, we illustrate the interference or an impact of engineering practices and design of wearable devices, including wearable robotics, with/on computational power these devices may or should have. We debate the way of enhancing the both: device manufacturing and creation of software where these wearable devices perform a crucial role. The purpose of this study is to open discussions towards intelligent engineering, where the purpose and usefulness of devices are jointly decided, during their design, by both engineers and computer scientists. By understanding the impact of engineering design decisions to potential computational power of cyber physical spaces, such as IoE, we should be able to create more efficient operational IoE, which will be more manageable and might meet our expectations.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"85 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89166014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-15DOI: 10.1109/ESTC48849.2020.9229798
Nu Bich Duyen Do, E. Andreassen, K. Imenes
This paper presents a study on the encapsulation of an interventional medical device, for use temporarily inside the human esophagus for cardiac imaging. A metallized polymer encapsulation, a potential encapsulation approach for simplifying the device assembly, was evaluated experimentally with regard to thermal performance. The encapsulation was fabricated by 3D printing followed by electroplating. The surface temperature of a simplified model of the device, with this double layer encapsulation, was measured in a tissue mimicking thermal phantom, stabilized at around 37 °C. Encapsulations based on a 0.9 mm thick polymer part with a 10, 80 or 150 µm thick Cu layer were tested. The effect of the power supplied to the model was also considered. The present model satisfied the maximum temperature limit for thermal safety (43 °C) when the Cu layer thickness of the encapsulation was at least 80 µm, for a heat source power not higher than 0.5 W.
{"title":"Thermal management with a new encapsulation approach for a medical device","authors":"Nu Bich Duyen Do, E. Andreassen, K. Imenes","doi":"10.1109/ESTC48849.2020.9229798","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229798","url":null,"abstract":"This paper presents a study on the encapsulation of an interventional medical device, for use temporarily inside the human esophagus for cardiac imaging. A metallized polymer encapsulation, a potential encapsulation approach for simplifying the device assembly, was evaluated experimentally with regard to thermal performance. The encapsulation was fabricated by 3D printing followed by electroplating. The surface temperature of a simplified model of the device, with this double layer encapsulation, was measured in a tissue mimicking thermal phantom, stabilized at around 37 °C. Encapsulations based on a 0.9 mm thick polymer part with a 10, 80 or 150 µm thick Cu layer were tested. The effect of the power supplied to the model was also considered. The present model satisfied the maximum temperature limit for thermal safety (43 °C) when the Cu layer thickness of the encapsulation was at least 80 µm, for a heat source power not higher than 0.5 W.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"33 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83104664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the 2 by 2 mmWave AiP array is design in organic substrate using fcCSP structure. The RF die is placed on bottom side of organic substrate and the AiP array is designed in the front side of organic substrate. Furthermore, the losses of transition from chip to antennas are related to thickness of redistribution layer (RDL), passivation thickness, and passivation material characteristic in AiP(Antenna-in-Package) technology. However, it is not clear in which manner a parameter really affects the losses of transition. This study tends to offer the lowest losses of transition from chip to antenna for AiP technology. This work also demonstrates the reduction of losses of transition from chip to AiP approximated 35% and 44% at 28 and 77 GHz. The designed AiP has better than 10 dB return loss in 26.4-29.7 GHz range, with ~3.4 GHz bandwidth and provides a high-gain (above ~5 dBi) radiation pattern for 5G mmWave application. In addition, many researchers have published lots of related papers about mmWave AiP design, but it is not clear a measurement solution or flow in mass production for mmWave AiP. In design stage, the spherical chamber is utilized to validate single antenna performance. It can direct measurement by RF prober on C4 bump pad or micro bump pad to get 2D or 3D radiation pattern of single antenna. From the simulation and measurement results, there is a good correlation. In engineering stage, the RF die is mounted on the bottom of organic substrate. The AiP device can utilize the compact antenna test range (CATR) chamber to get all relative radiation patterns, such as 2D/3D pattern and EIRP. Of course, the CART is a good validation solution for beamforming measurement. Finally, for mass production, a testing set is announced for mmWave AiP or SiP production test. Through the three different measurement solutions and mmWave measurement flow, a completed mmWave AiP and SiP flow from design to validation is delivered.
{"title":"Performance Analysis and Test Solution with Integrated Antenna-in-Package for Millimeter-Wave System","authors":"Sheng-Chi Hsieh, Cheng-Yu Ho, Chen-Chao Wang, Fu-Cheng Chu","doi":"10.1109/ESTC48849.2020.9229721","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229721","url":null,"abstract":"In this paper, the 2 by 2 mmWave AiP array is design in organic substrate using fcCSP structure. The RF die is placed on bottom side of organic substrate and the AiP array is designed in the front side of organic substrate. Furthermore, the losses of transition from chip to antennas are related to thickness of redistribution layer (RDL), passivation thickness, and passivation material characteristic in AiP(Antenna-in-Package) technology. However, it is not clear in which manner a parameter really affects the losses of transition. This study tends to offer the lowest losses of transition from chip to antenna for AiP technology. This work also demonstrates the reduction of losses of transition from chip to AiP approximated 35% and 44% at 28 and 77 GHz. The designed AiP has better than 10 dB return loss in 26.4-29.7 GHz range, with ~3.4 GHz bandwidth and provides a high-gain (above ~5 dBi) radiation pattern for 5G mmWave application. In addition, many researchers have published lots of related papers about mmWave AiP design, but it is not clear a measurement solution or flow in mass production for mmWave AiP. In design stage, the spherical chamber is utilized to validate single antenna performance. It can direct measurement by RF prober on C4 bump pad or micro bump pad to get 2D or 3D radiation pattern of single antenna. From the simulation and measurement results, there is a good correlation. In engineering stage, the RF die is mounted on the bottom of organic substrate. The AiP device can utilize the compact antenna test range (CATR) chamber to get all relative radiation patterns, such as 2D/3D pattern and EIRP. Of course, the CART is a good validation solution for beamforming measurement. Finally, for mass production, a testing set is announced for mmWave AiP or SiP production test. Through the three different measurement solutions and mmWave measurement flow, a completed mmWave AiP and SiP flow from design to validation is delivered.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"74 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90747604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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