Energy efficiency is one of the most important metrics in AI system designs on both servers and mobile devices. Especially, mobile and edge devices require 10-100X better energy-efficient computing for immersive AR/VR applications as well as AI-based apps on smartphones, smart cameras, etc. Due to battery and cost reasons, such emerging applications demand extreme energy efficiency and high performance to run dozens of heavy neural network models in real time and under stringent power budgets. In order to realize 100X improvements in energy efficiency, we require innovative ideas in both software and hardware. In this special issue, which originated from the Highly Efficient Neural Processing (HENP) workshop held in ESWEEK 2020, we aimed at covering state-of-the-art industrial and academic efforts to achieve orders of magnitude better energy efficiency in software and hardware designs for AI chips. Recent neural networks adopt special layers for better compute efficiency. “MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units” by Lee et al. proposes an approach to improve area-efficiency of systolic array accelerator for depth-wise separable convolution and squeeze-and-excitation layers which are widely adopted on networks for mobile and embedded systems due to efficiency reasons. Reusing computation results is one of the representative methods in reducing computation cost thereby improving energy efficiency. “Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse” by Cicek et al. proposes a novel reuse-centric hardware accelerator for CNN inference based on the proposed improved detection of neuron vector similarity. Embedded devices are often characterized by continuous sensory inputs and limited computing/programming capabilities. “A Low-Power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices” by Kee et al. proposes a hardware accelerator, called intelligent boosting engine, to accelerate sensor fusion and the SVM-based motion recognition algorithm with limited programmability. Processing sequential inputs under timing and power budgets is a representative design problem in edge applications. In “Energy Efficient LSTM Inference Accelerator for Real-Time Causal Prediction” by Chen et al. the authors take advantage of fine-grained parallelism, pipelined feedforward and recurrent updates in LSTM and present a bit-sparse quantization to reduce the circuit cost by replacing the original multiplication with the bit-shift operation. Adopting reinforcement learning on edge devices for sequential decision-making and control based on image inputs is desirable, but challenging due to the low efficiency of training and the high cost of inference. In “E2HRL: An Energy-Efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning”, Shiri et al. proposes a scalable hardware architecture called E2HRL which boosts training speed by learning hierarchical policies and
在服务器和移动设备上的人工智能系统设计中，能效是最重要的指标之一。特别是，移动和边缘设备需要10-100倍的高效节能计算来实现沉浸式AR/VR应用，以及智能手机、智能相机等上基于ai的应用。由于电池和成本的原因，这些新兴应用需要极高的能源效率和高性能，以便在严格的功率预算下实时运行数十个重型神经网络模型。为了实现100倍的能源效率提高，我们需要在软件和硬件上都有创新的想法。本期特刊源于ESWEEK 2020举办的高效神经处理(HENP)研讨会，我们旨在涵盖最先进的工业和学术努力，以实现AI芯片软件和硬件设计的数量级能效提高。最近的神经网络采用特殊的层来提高计算效率。Lee等人的“MVP:一个具有矩阵、向量和处理近内存单元的高效CNN加速器”提出了一种提高深度可分离卷积层和挤压激励层收缩阵列加速器的面积效率的方法，由于效率原因，这些层被广泛应用于移动和嵌入式系统的网络。计算结果的再利用是降低计算成本从而提高能源效率的代表性方法之一。Cicek等人的“Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse”一文中基于改进的神经元向量相似性检测，提出了一种新的以重用为中心的CNN推理硬件加速器。嵌入式设备通常以连续的感官输入和有限的计算/编程能力为特征。Kee等人的“智能边缘设备的低功耗可编程机器学习硬件加速器设计”提出了一种称为智能提升引擎的硬件加速器，以加速传感器融合和基于svm的运动识别算法，但可编程性有限。在时序和功率预算下处理顺序输入是边缘应用中的代表性设计问题。在Chen等人的“Energy Efficient LSTM Inference Accelerator for Real-Time Causal Prediction”一文中，作者利用LSTM的细粒度并行性、流水线前馈和循环更新，提出了位稀疏量化，用位移位操作取代原来的乘法运算，从而降低了电路成本。在边缘设备上采用强化学习进行基于图像输入的顺序决策和控制是可取的，但由于训练效率低和推理成本高，因此具有挑战性。在“E2HRL:用于分层深度强化学习的节能硬件加速器”一文中，Shiri等人提出了一种可扩展的硬件架构E2HRL，该架构通过学习分层策略来提高训练速度，并通过跨层设计方法实现高能效。
{"title":"Introduction to the Special Section on Energy-Efficient AI Chips","authors":"V. Chandra, Yiran Chen, Sung-kyu Yoo","doi":"10.1145/3538502","DOIUrl":"https://doi.org/10.1145/3538502","url":null,"abstract":"Energy efficiency is one of the most important metrics in AI system designs on both servers and mobile devices. Especially, mobile and edge devices require 10-100X better energy-efficient computing for immersive AR/VR applications as well as AI-based apps on smartphones, smart cameras, etc. Due to battery and cost reasons, such emerging applications demand extreme energy efficiency and high performance to run dozens of heavy neural network models in real time and under stringent power budgets. In order to realize 100X improvements in energy efficiency, we require innovative ideas in both software and hardware. In this special issue, which originated from the Highly Efficient Neural Processing (HENP) workshop held in ESWEEK 2020, we aimed at covering state-of-the-art industrial and academic efforts to achieve orders of magnitude better energy efficiency in software and hardware designs for AI chips. Recent neural networks adopt special layers for better compute efficiency. “MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units” by Lee et al. proposes an approach to improve area-efficiency of systolic array accelerator for depth-wise separable convolution and squeeze-and-excitation layers which are widely adopted on networks for mobile and embedded systems due to efficiency reasons. Reusing computation results is one of the representative methods in reducing computation cost thereby improving energy efficiency. “Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse” by Cicek et al. proposes a novel reuse-centric hardware accelerator for CNN inference based on the proposed improved detection of neuron vector similarity. Embedded devices are often characterized by continuous sensory inputs and limited computing/programming capabilities. “A Low-Power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices” by Kee et al. proposes a hardware accelerator, called intelligent boosting engine, to accelerate sensor fusion and the SVM-based motion recognition algorithm with limited programmability. Processing sequential inputs under timing and power budgets is a representative design problem in edge applications. In “Energy Efficient LSTM Inference Accelerator for Real-Time Causal Prediction” by Chen et al. the authors take advantage of fine-grained parallelism, pipelined feedforward and recurrent updates in LSTM and present a bit-sparse quantization to reduce the circuit cost by replacing the original multiplication with the bit-shift operation. Adopting reinforcement learning on edge devices for sequential decision-making and control based on image inputs is desirable, but challenging due to the low efficiency of training and the high cost of inference. In “E2HRL: An Energy-Efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning”, Shiri et al. proposes a scalable hardware architecture called E2HRL which boosts training speed by learning hierarchical policies and ","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"1 1","pages":"1 - 2"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88570604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Side-channel attack (SCA) reveals confidential information by statistically analyzing physical manifestations, which is the serious threat to cryptographic circuits. Various SCA circuit-level countermeasures have been proposed as fundamental solutions to reduce the side-channel vulnerabilities of cryptographic implementations; however, such approaches introduce non-negligible power and area overheads. Among all of the circuit components, flip-flops are the main source of information leakage. This article proposes a three-phase single-rail pulse register (TSPR) based on the three-independent-gate field effect transistor (TIGFET) to achieve all desired properties with improved metrics of area and security. TIGFET-based TSPR consumes a constant power (MCV is 0.25%), has a low delay (12 ps), and employs only 10 TIGFET devices, which is applicable for the low-overhead and high-security cryptographic circuit design compared to the existing flip-flops. In addition, a set of TIGFET-based combinational basic gates are designed to reduce the area occupation and power consumption as much as possible. As a proof of concept, a simplified advanced encryption algorithm (AES), SM4 block cipher algorithm (SM4), and light-weight cryptographic algorithm (PRESENT) are built with the TIGFET-based library. SCA is implemented on the cryptographic implementations to prove its SCA resilience, and the SCA results show that the correct key of cryptographic circuits with TIGFET-based TSPRs is not guessed within 2,000 power traces.
{"title":"A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks","authors":"Yanjiang Liu, Tongzhou Qu, Z. Dai","doi":"10.1145/3498339","DOIUrl":"https://doi.org/10.1145/3498339","url":null,"abstract":"Side-channel attack (SCA) reveals confidential information by statistically analyzing physical manifestations, which is the serious threat to cryptographic circuits. Various SCA circuit-level countermeasures have been proposed as fundamental solutions to reduce the side-channel vulnerabilities of cryptographic implementations; however, such approaches introduce non-negligible power and area overheads. Among all of the circuit components, flip-flops are the main source of information leakage. This article proposes a three-phase single-rail pulse register (TSPR) based on the three-independent-gate field effect transistor (TIGFET) to achieve all desired properties with improved metrics of area and security. TIGFET-based TSPR consumes a constant power (MCV is 0.25%), has a low delay (12 ps), and employs only 10 TIGFET devices, which is applicable for the low-overhead and high-security cryptographic circuit design compared to the existing flip-flops. In addition, a set of TIGFET-based combinational basic gates are designed to reduce the area occupation and power consumption as much as possible. As a proof of concept, a simplified advanced encryption algorithm (AES), SM4 block cipher algorithm (SM4), and light-weight cryptographic algorithm (PRESENT) are built with the TIGFET-based library. SCA is implemented on the cryptographic implementations to prove its SCA resilience, and the SCA results show that the correct key of cryptographic circuits with TIGFET-based TSPRs is not guessed within 2,000 power traces.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"43 1","pages":"1 - 13"},"PeriodicalIF":0.0,"publicationDate":"2022-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84058029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of the machine learning and IoT, many low-power edge devices, such as wearable devices with various sensors, are used for machine learning–based intelligent applications, such as healthcare or motion recognition. While these applications are becoming more complex to provide high-quality services, the performance of conventional low-power edge devices with extremely limited hardware resources is insufficient to support the emerging intelligent applications. We designed a hardware accelerator, called an Intelligence Boost Engine (IBE), for low-power smart edge devices to enable the real-time processing of emerging intelligent applications with energy efficiency and limited programmability. The measurement results confirm that the proposed IBE can reduce the power consumption of the edge node device by 75% and achieve performance improvement in processing the kernel operations of applications such as motion recognition by 69.9 times.
{"title":"A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices","authors":"Minkwan Kee, Gi-Ho Park","doi":"10.1145/3531479","DOIUrl":"https://doi.org/10.1145/3531479","url":null,"abstract":"With the advent of the machine learning and IoT, many low-power edge devices, such as wearable devices with various sensors, are used for machine learning–based intelligent applications, such as healthcare or motion recognition. While these applications are becoming more complex to provide high-quality services, the performance of conventional low-power edge devices with extremely limited hardware resources is insufficient to support the emerging intelligent applications. We designed a hardware accelerator, called an Intelligence Boost Engine (IBE), for low-power smart edge devices to enable the real-time processing of emerging intelligent applications with energy efficiency and limited programmability. The measurement results confirm that the proposed IBE can reduce the power consumption of the edge node device by 75% and achieve performance improvement in processing the kernel operations of applications such as motion recognition by 69.9 times.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"9 1","pages":"1 - 13"},"PeriodicalIF":0.0,"publicationDate":"2022-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81906020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yunkai Bai, Andrew Stern, Jungmin Park, M. Tehranipoor, Domenic Forte
The Internet of Things (IoT) and smart devices are currently being deployed in systems such as autonomous vehicles and medical monitoring devices. The introduction of IoT devices into these systems enables network connectivity for data transfer, cloud support, and more, but can also lead to malware injection. Since many IoT devices operate in remote environments, it is also difficult to protect them from physical tampering. Conventional protection approaches rely on software. However, these can be circumvented by the moving target nature of malware or through hardware attacks. Alternatively, insertion of the internal monitoring circuits into IoT chips requires a design trade-off, balancing the requirements of the monitoring circuit and the main circuit. A very promising approach to detecting anomalous behavior in the IoT and other embedded systems is side-channel analysis. To date, however, this can be performed only before deployment due to the cost and size of side-channel setups (e.g., and oscilloscopes, probes) or by internal performance counters. Here, we introduce an external monitoring printed circuit board (PCB) named RASC to provide remote access to side-channels. RASC reduces the complete side-channel analysis system into two small PCBs (2 ( times ) 2 cm), providing the ability to monitor power and electromagnetic (EM) traces of the target device. Additionally, RASC can transmit data and/or alerts of anomalous activities detected to a remote host through Bluetooth. To demonstrate RASCs capabilities, we extract keys from encryption modules such as AES implemented on Arduino and FPGA boards. To illustrate RASC’s defensive capabilities, we also use it to perform malware detection. RASC’s success in power analysis is comparable to an oscilloscope/probe setup but is lightweight and two orders of magnitude cheaper.
物联网(IoT)和智能设备目前正在自动驾驶汽车和医疗监控设备等系统中部署。将物联网设备引入这些系统，可以实现数据传输、云支持等方面的网络连接，但也可能导致恶意软件注入。由于许多物联网设备在远程环境中运行，因此也很难保护它们免受物理篡改。传统的保护方法依赖于软件。然而，这些可以通过恶意软件的移动目标特性或通过硬件攻击来绕过。或者，将内部监控电路插入物联网芯片需要进行设计权衡，平衡监控电路和主电路的要求。在物联网和其他嵌入式系统中检测异常行为的一种非常有前途的方法是侧信道分析。然而，到目前为止，由于侧通道设置(例如示波器、探头)的成本和尺寸，只能在部署之前执行此操作，或者通过内部性能计数器执行。在这里，我们介绍了一种外部监测印刷电路板(PCB)，称为RASC，提供对侧信道的远程访问。RASC将完整的侧信道分析系统缩小为两个小pcb (2 ( times ) 2 cm)，提供监控目标器件的功率和电磁(EM)走线的能力。此外，RASC可以通过蓝牙将检测到的异常活动的数据和/或警报传输到远程主机。为了演示rasc的功能，我们从Arduino和FPGA板上实现的AES等加密模块中提取密钥。为了说明RASC的防御能力，我们还使用它来执行恶意软件检测。RASC在功率分析方面的成功可与示波器/探头设置相媲美，但重量轻，价格便宜两个数量级。
{"title":"RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems","authors":"Yunkai Bai, Andrew Stern, Jungmin Park, M. Tehranipoor, Domenic Forte","doi":"10.1145/3524123","DOIUrl":"https://doi.org/10.1145/3524123","url":null,"abstract":"The Internet of Things (IoT) and smart devices are currently being deployed in systems such as autonomous vehicles and medical monitoring devices. The introduction of IoT devices into these systems enables network connectivity for data transfer, cloud support, and more, but can also lead to malware injection. Since many IoT devices operate in remote environments, it is also difficult to protect them from physical tampering. Conventional protection approaches rely on software. However, these can be circumvented by the moving target nature of malware or through hardware attacks. Alternatively, insertion of the internal monitoring circuits into IoT chips requires a design trade-off, balancing the requirements of the monitoring circuit and the main circuit. A very promising approach to detecting anomalous behavior in the IoT and other embedded systems is side-channel analysis. To date, however, this can be performed only before deployment due to the cost and size of side-channel setups (e.g., and oscilloscopes, probes) or by internal performance counters. Here, we introduce an external monitoring printed circuit board (PCB) named RASC to provide remote access to side-channels. RASC reduces the complete side-channel analysis system into two small PCBs (2 ( times ) 2 cm), providing the ability to monitor power and electromagnetic (EM) traces of the target device. Additionally, RASC can transmit data and/or alerts of anomalous activities detected to a remote host through Bluetooth. To demonstrate RASCs capabilities, we extract keys from encryption modules such as AES implemented on Arduino and FPGA boards. To illustrate RASC’s defensive capabilities, we also use it to perform malware detection. RASC’s success in power analysis is comparable to an oscilloscope/probe setup but is lightweight and two orders of magnitude cheaper.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"356 1","pages":"1 - 25"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74848826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dwaipayan Choudhury, Reet Barik, Aravind Sukumaran Rajam, A. Kalyanaraman, And Partha Pratim Pande
Manycore GPU architectures have become the mainstay for accelerating graph computations. One of the primary bottlenecks to performance of graph computations on manycore architectures is the data movement. Since most of the accesses in graph processing are due to vertex neighborhood lookups, locality in graph data structures plays a key role in dictating the degree of data movement. Vertex reordering is a widely used technique to improve data locality within graph data structures. However, these reordering schemes alone are not sufficient as they need to be complemented with efficient task allocation on manycore GPU architectures to reduce latency due to local cache misses. Consequently, in this article, we introduce a software/hardware co-design framework for accelerating graph computations. Our approach couples an architecture-aware vertex reordering with a priority-based task allocation technique. As the task allocation aims to reduce on-chip latency and associated energy, the choice of Network-on-Chip (NoC) as the communication backbone in the manycore platform is an important parameter. By leveraging emerging three-dimensional (3D) integration technology, we propose design of a small-world NoC (SWNoC)-enabled manycore GPU architecture, where the placement of the links connecting the streaming multiprocessors (SMs) and the memory controllers (MCs) follow a power-law distribution. The proposed 3D SWNoC-enabled software/hardware co-design framework achieves 11.1% to 22.9% performance improvement and 16.4% to 32.6% less energy consumption depending on the dataset and the graph application, when compared to the default order of dataset running on a conventional planar mesh architecture.
{"title":"Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations","authors":"Dwaipayan Choudhury, Reet Barik, Aravind Sukumaran Rajam, A. Kalyanaraman, And Partha Pratim Pande","doi":"10.1145/3514354","DOIUrl":"https://doi.org/10.1145/3514354","url":null,"abstract":"Manycore GPU architectures have become the mainstay for accelerating graph computations. One of the primary bottlenecks to performance of graph computations on manycore architectures is the data movement. Since most of the accesses in graph processing are due to vertex neighborhood lookups, locality in graph data structures plays a key role in dictating the degree of data movement. Vertex reordering is a widely used technique to improve data locality within graph data structures. However, these reordering schemes alone are not sufficient as they need to be complemented with efficient task allocation on manycore GPU architectures to reduce latency due to local cache misses. Consequently, in this article, we introduce a software/hardware co-design framework for accelerating graph computations. Our approach couples an architecture-aware vertex reordering with a priority-based task allocation technique. As the task allocation aims to reduce on-chip latency and associated energy, the choice of Network-on-Chip (NoC) as the communication backbone in the manycore platform is an important parameter. By leveraging emerging three-dimensional (3D) integration technology, we propose design of a small-world NoC (SWNoC)-enabled manycore GPU architecture, where the placement of the links connecting the streaming multiprocessors (SMs) and the memory controllers (MCs) follow a power-law distribution. The proposed 3D SWNoC-enabled software/hardware co-design framework achieves 11.1% to 22.9% performance improvement and 16.4% to 32.6% less energy consumption depending on the dataset and the graph application, when compared to the default order of dataset running on a conventional planar mesh architecture.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"1 1","pages":"1 - 22"},"PeriodicalIF":0.0,"publicationDate":"2022-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89460774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article introduces a fault localization method to extract the exact location of single and multiple missing gate faults in reversible ( k ) -CNOT -based circuits. The primary target of the proposed method is to obtain the complete test set for localizing faults in ( k ) -CNOT circuits. We propose a fault localization algorithm to construct a fault localization tree that can be used to find equivalent and non-equivalent faults. For the non-equivalent faults, the test sequences can be obtained from the fault localization tree that uniquely localizes the non-equivalent faults. Finally, this article presents the experimental results and comparative analysis with existing works.
本文介绍了一种故障定位方法，用于提取可逆( k ) -CNOT电路中单个和多个缺门故障的准确位置。该方法的主要目标是获得( k ) -CNOT电路故障定位的完整测试集。提出了一种故障定位算法，构建了一棵故障定位树，该树可用于发现等效和非等效故障。对于非等效故障，可以从故障定位树中获得测试序列，该树唯一地定位了非等效故障。最后，本文给出了实验结果，并与已有成果进行了对比分析。
{"title":"Fault Localization Scheme for Missing Gate Faults in Reversible Circuits","authors":"Mousum Handique, J. K. Deka, S. Biswas","doi":"10.1145/3503539","DOIUrl":"https://doi.org/10.1145/3503539","url":null,"abstract":"This article introduces a fault localization method to extract the exact location of single and multiple missing gate faults in reversible ( k ) -CNOT -based circuits. The primary target of the proposed method is to obtain the complete test set for localizing faults in ( k ) -CNOT circuits. We propose a fault localization algorithm to construct a fault localization tree that can be used to find equivalent and non-equivalent faults. For the non-equivalent faults, the test sequences can be obtained from the fault localization tree that uniquely localizes the non-equivalent faults. Finally, this article presents the experimental results and comparative analysis with existing works.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"24 1","pages":"1 - 29"},"PeriodicalIF":0.0,"publicationDate":"2022-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82433198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Pilato, Zhenman Fang, Yuko Hara-Azumi, J. Hwang
Due to the end of Dennard scaling and Moore’s law, heterogeneous System-on-Chip (SoC) architectures are replacing complex hyper-pipelined processors to achieve high performance and energy efficiency. Such architectures feature many specialized components that can be used to accelerate selected computational kernels by exploiting more intrinsic parallelism with custom logic. Among them, FPGA devices are becoming common targets for these systems, since they allow fast turnaround time, field upgradability, and easy deployment of hardware/software solutions. However, co-designing FPGA systems still requires a combination of hardware and software design skills that are uncommon in most of the designers. To overcome these issues, designers need to raise the abstraction level from low-level manual designs to high-level approaches. High-level synthesis (HLS) is becoming a key enabling technology, especially for FPGA designs, since it allows designers to describe the functionality of a component at the software level and automatically generate the corresponding hardware description, enabling fast deployment of hardware/software solutions. HLS has been making tremendous progress in many application domains, ranging from Internet of Things and edge computing to data centers and cloud computing. While HLS is becoming more popular, the other side of the coin is that it is pushing the application landscape for hardware acceleration towards unprecedented challenges. On one hand, modern applications must elaborate huge amounts of data, demanding efficient methods for managing memory accesses. On the other hand, HLS is a complex process that produces itself a huge amount of information that can be used to drive further optimizations. In both cases, machine learning is coming to the rescue to extract valuable knowledge and make accurate predictions. In this special section, we have six articles covering both challenges (the first five articles) and application aspects (the last one). These articles show that HLS is a powerful but yet difficult-touse solution. Indeed, many HLS tools offer directives, i.e., source code annotations that trigger specific optimizations, but understanding the optimal combination from a huge design space is still a manual and time-consuming effort. The articles in this special section provide interesting insights on how to automate this exploration process also with the help of machine learning. We hope you will enjoy them and find them as interesting as we did. The special section opens with an article on the compiler-level optimizations for optimizing the pointer synthesis within HLS. “A case for precise, fine-grained pointer synthesis in high-level synthesis,” by N. Ramanathan et al., aims at reducing the gap between application designers, who could make heavy use of pointers to create compact and efficient software descriptions, and hardware designers, which demand precise memory information to implement the corresponding accesses
{"title":"Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications","authors":"C. Pilato, Zhenman Fang, Yuko Hara-Azumi, J. Hwang","doi":"10.1145/3519279","DOIUrl":"https://doi.org/10.1145/3519279","url":null,"abstract":"Due to the end of Dennard scaling and Moore’s law, heterogeneous System-on-Chip (SoC) architectures are replacing complex hyper-pipelined processors to achieve high performance and energy efficiency. Such architectures feature many specialized components that can be used to accelerate selected computational kernels by exploiting more intrinsic parallelism with custom logic. Among them, FPGA devices are becoming common targets for these systems, since they allow fast turnaround time, field upgradability, and easy deployment of hardware/software solutions. However, co-designing FPGA systems still requires a combination of hardware and software design skills that are uncommon in most of the designers. To overcome these issues, designers need to raise the abstraction level from low-level manual designs to high-level approaches. High-level synthesis (HLS) is becoming a key enabling technology, especially for FPGA designs, since it allows designers to describe the functionality of a component at the software level and automatically generate the corresponding hardware description, enabling fast deployment of hardware/software solutions. HLS has been making tremendous progress in many application domains, ranging from Internet of Things and edge computing to data centers and cloud computing. While HLS is becoming more popular, the other side of the coin is that it is pushing the application landscape for hardware acceleration towards unprecedented challenges. On one hand, modern applications must elaborate huge amounts of data, demanding efficient methods for managing memory accesses. On the other hand, HLS is a complex process that produces itself a huge amount of information that can be used to drive further optimizations. In both cases, machine learning is coming to the rescue to extract valuable knowledge and make accurate predictions. In this special section, we have six articles covering both challenges (the first five articles) and application aspects (the last one). These articles show that HLS is a powerful but yet difficult-touse solution. Indeed, many HLS tools offer directives, i.e., source code annotations that trigger specific optimizations, but understanding the optimal combination from a huge design space is still a manual and time-consuming effort. The articles in this special section provide interesting insights on how to automate this exploration process also with the help of machine learning. We hope you will enjoy them and find them as interesting as we did. The special section opens with an article on the compiler-level optimizations for optimizing the pointer synthesis within HLS. “A case for precise, fine-grained pointer synthesis in high-level synthesis,” by N. Ramanathan et al., aims at reducing the gap between application designers, who could make heavy use of pointers to create compact and efficient software descriptions, and hardware designers, which demand precise memory information to implement the corresponding accesses","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"22 1","pages":"1 - 2"},"PeriodicalIF":0.0,"publicationDate":"2022-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73932609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nadesh Ramanathan, G. Constantinides, John Wickerson
This article combines two practical approaches to improve pointer synthesis within HLS tools. Both approaches focus on inefficiencies in how HLS tools treat the points-to graph—a mapping that connects each instruction to the memory locations that it might access at runtime. HLS pointer synthesis first computes the points-to graph via pointer analysis and then implements its connections in hardware, which gives rise to two inefficiencies. First, HLS tools typically favour pointer analysis that is fast, sacrificing precision. Second, they also favour centralising memory connections in hardware for instructions that can point to more than one location. In this article, we demonstrate that a more precise pointer analysis coupled with decentralised memory connections in hardware can substantially reduce the unnecessary sharing of memory resources. We implement both flow- and context-sensitive pointer analysis and fine-grained memory connections in two modern HLS tools, LegUp and Vitis HLS. An evaluation on three benchmark suites, ranging from non-trivial pointer use to standard HLS benchmarks, indicates that when we improve both precision and granularity of pointer synthesis, on average, we can reduce area and latency by around 42% and 37%, respectively.
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Modern digital circuits are often required to operate in multiple modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized, meeting different timing constraints in different operational modes. The overall power consumption and robustness to variations of a clock network are determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that timing constraints in low- and high-performance modes can be very different. In this article, we propose a clock network with a mode-reconfigurable topology (MRT) for circuits with positive-edge-triggered sequential elements. In high-performance modes, the MRT structure is reconfigured into a near-tree to provide the required robustness to variations. In low-performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Hence, the MRT structures consume no short-circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure an MRT structure into a tree topology using a single clock gate. In high-performance modes, the experimental results demonstrate that MRT structures have ( 25% ) lower power consumption than state-of-the-art near-tree structures. In low-performance modes, the power consumption of the MRT structure is similar to the power consumption of a clock tree.
{"title":"Synthesis of Clock Networks with a Mode-Reconfigurable Topology","authors":"Necati Uysal, Rickard Ewetz","doi":"10.1145/3503538","DOIUrl":"https://doi.org/10.1145/3503538","url":null,"abstract":"Modern digital circuits are often required to operate in multiple modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized, meeting different timing constraints in different operational modes. The overall power consumption and robustness to variations of a clock network are determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that timing constraints in low- and high-performance modes can be very different. In this article, we propose a clock network with a mode-reconfigurable topology (MRT) for circuits with positive-edge-triggered sequential elements. In high-performance modes, the MRT structure is reconfigured into a near-tree to provide the required robustness to variations. In low-performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Hence, the MRT structures consume no short-circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure an MRT structure into a tree topology using a single clock gate. In high-performance modes, the experimental results demonstrate that MRT structures have ( 25% ) lower power consumption than state-of-the-art near-tree structures. In low-performance modes, the power consumption of the MRT structure is similar to the power consumption of a clock tree.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"135 1","pages":"1 - 22"},"PeriodicalIF":0.0,"publicationDate":"2022-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78249676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many on-chip applications. Recently through-silicon-via– (TSV) based inductor (also known as a TSV-inductor) with a magnetic core has been proved to be a viable option for the on-chip DC-DC converter. The operating conditions of these inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, there is a critical need to study the design and optimization details of magnetic core TSV-inductors with the unique three-dimensional structure embedding magnetic core. This article aims to provide a clear understanding of the modeling details of a magnetic core TSV-inductor and a design and optimization methodology to assist efficient inductor design. Moreover, a machine learning–assisted model combining physical details and artificial neural network is also proposed to extract the equivalent circuit to further facilitate DC-DC converter design. Experimental results show that the optimized TSV-inductor with the magnetic core and air-gap can achieve inductance density improvement of up to 7.7 ( times ) and quality factor improvements of up to 1.6 ( times ) for the same footprint compared with the TSV-inductor without a magnetic core. For on-chip DC-DC converter applications, the converter efficiency can be improved by up to 15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.
传统的片上螺旋电感消耗了大量的顶部金属布线面积，从而阻碍了它在许多片上应用的普及。最近，带磁芯的通硅通孔(TSV)电感器(也称为TSV电感器)已被证明是片上DC-DC转换器的可行选择。这些电感的工作条件在最大限度地提高DC-DC变换器的性能和效率方面起着重要作用。然而，具有独特的三维结构嵌入磁芯的磁芯tsv电感器的设计和优化细节研究是非常必要的。本文旨在清楚地了解磁芯tsv电感器的建模细节，并提供设计和优化方法，以协助有效的电感器设计。此外，还提出了一种结合物理细节和人工神经网络的机器学习辅助模型来提取等效电路，进一步方便DC-DC变换器的设计。实验结果表明，与不带磁芯的tsv电感器相比，优化后的带磁芯和气隙的tsv电感器在相同占地面积下，电感密度提高了7.7 ( times )，质量因数提高了1.6 ( times )。对于片上DC-DC转换器应用，转换器效率可提高高达15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.
{"title":"Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter","authors":"Chenyi Wen, Xiao Dong, Baixin Chen, Umamaheswara Rao Tida, Yiyu Shi, Cheng Zhuo","doi":"10.1145/3507700","DOIUrl":"https://doi.org/10.1145/3507700","url":null,"abstract":"The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many on-chip applications. Recently through-silicon-via– (TSV) based inductor (also known as a TSV-inductor) with a magnetic core has been proved to be a viable option for the on-chip DC-DC converter. The operating conditions of these inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, there is a critical need to study the design and optimization details of magnetic core TSV-inductors with the unique three-dimensional structure embedding magnetic core. This article aims to provide a clear understanding of the modeling details of a magnetic core TSV-inductor and a design and optimization methodology to assist efficient inductor design. Moreover, a machine learning–assisted model combining physical details and artificial neural network is also proposed to extract the equivalent circuit to further facilitate DC-DC converter design. Experimental results show that the optimized TSV-inductor with the magnetic core and air-gap can achieve inductance density improvement of up to 7.7 ( times ) and quality factor improvements of up to 1.6 ( times ) for the same footprint compared with the TSV-inductor without a magnetic core. For on-chip DC-DC converter applications, the converter efficiency can be improved by up to 15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"156 1","pages":"1 - 23"},"PeriodicalIF":0.0,"publicationDate":"2022-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88449718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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