To enable compact quantum computing systems, cryogenically compatible CMOS-based non-volatile memories are required. In this work, we investigate 1-transistor–1-resistor (1T1R) resistive random-access memory (RRAM) devices over an extended temperature range, including previously unexplored cryogenic regimes. To enhance storage density, we explore a multilevel-cell approach via multilevel programming. As temperature decreases, the low-resistance state (LRS) effective conductance increases, improving state separation but also leading to higher LRS currents and increased reset voltages required for reliable switching to the high-resistance state (HRS), resulting in incomplete filament rupture and a broader HRS distribution. Through independent characterization of the access nMOS transistor, we identify transistor temperature dependence as the dominant factor governing LRS evolution, while extraction of the intrinsic metal–insulator–metal (MIM) behavior reveals an opposite trend, with decreasing conductivity at lower temperatures. Based on these insights, we implement an optimized programming strategy for cryogenic operation by tuning the nMOS gate bias during set, reducing LRS currents, particularly in intermediate and high conductance states, while preserving state separation, narrowing the HRS distribution, and lowering reset voltages. Overall, this work establishes a robust and scalable approach for reliable 1T1R operation at cryogenic temperatures and provides a key step toward nonvolatile memory integration in quantum computing architectures.
We developed a reconfigurable ternary logic-in-memory (LIM) device based on an organic antiambipolar transistor and incorporating a gold floating gate into a hafnium oxide (HfO2) gate insulator. First, a standard ternary inverter was obtained with extremely low input and drain voltages (2 V) owing to the high dielectric constant of the HfO2 gate insulator. Three distinct output logic states (“2,” “1,” and “0”) were clearly obtained for the corresponding input logic states (“0,” “1,” and “2”). Then, the voltage transfer curve was laterally shifted up to 1.8 V by controlling the hole- and electron-injection processes into the floating gate, obtaining a ternary nonvolatile memory. This memory function realized versatile reconfigurable ternary inverter operations. Three ternary inverters, namely, standard, negative, and positive ternary inverters, were demonstrated in a single LIM device. Remarkably, these inverter operations were performed using the same input voltages and then electrically reconfigured by adjusting the charge condition (i.e., holes or electrons) of the floating gate. Our development seems promising for performing multivalued in-memory computing toward surpassing the capabilities of existing von Neumann systems.
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