Memristive devices based on halide perovskites hold strong promise to provide energy-efficient systems for the Internet of Things (IoT); however, lead (Pb) element should be minimized or ideally replaced. Herein, we introduce a multifunctional device based on AgBiI4 Pb-free perovskite as the active layer in a normal n-i-p solar cell configuration that exhibitss multiple mode-dependent neuromorphic functions. Specifically, through electrode engineering, we show a selection between volatile or non-volatile memristive switching when the Au top electrode is replaced by Ag. The volatile device having an Au top electrode can be used for emulating threshold-dependent artificial neuron firing processes, while the non-volatile device with Ag pads can emulate numerous synaptic protocols (LTP/LTD, PPF, STDP, SRDP, LTM, STM). Both volatile (VTH = −0.86 V) and non-volatile modes possess switching low voltages <1 V, while the ON/OFF ratio of the non-volatile system is 104 with a cycling endurance of 103 cycles and state retention of 103 s. Further investigation reveals that electrode type affects the conduction mechanism, as ion charge trapping and detrapping govern threshold switching with activation energy EA ≈ 0.7 eV, while the formation/rupture of Ag filaments is responsible for non-volatile switching. The response in both modes of devices can be tuned by light, while associative learning by emulating Pavlovian learning is demonstrated. Finally, experimental non-volatile data were used for MNIST and Fashion-MNIST classification, achieving 97.11% and 87.56% accuracy, respectively. Our work provides insights into electrode-engineered mode control in lead-free perovskite systems capable for a concurrent energy harvesting (PCE ∼1%) toward self-powered systems for neuromorphic edge computing.
True random number generators (TRNGs) are essential for hardware security in edge AI systems, yet conventional designs often incur large analog overhead and limited throughput imposed by standalone macros. We present a Compute-in-Memory (CiM)-compatible TRNG that directly exploits the intrinsic stochasticity of TaOx-based 1T1R RRAM arrays, enabling entropy extraction within the memory fabric. Bit-rate is scaled by parallel column readout circuits consisting of a transimpedance amplifier (TIA) and an ADC. Our design achieves up to ∼270 Mbps throughput with TIA + 16-bit ADC per column. Furthermore, a lightweight shift-XOR post-processing stage permits reduction to 8-bit ADC resolution, lowering energy consumption to ∼51 pJ bit−1 without degrading randomness quality. Fully compatible with standard CiM read paths, the architecture introduces minimal hardware overhead and provides a scalable and energy-efficient foundation for secure random number generation in edge-AI applications.
Amorphous silicon carbide (SiC) is a promising dielectric platform for memristive artificial synapses due to its high stability and back-end-of-line compatibility for CMOS integration. Here, we demonstrate stoichiometric PECVD-grown amorphous SiC memristors with Cu active electrodes, in which synaptic functionality is engineered through control of material composition. By tuning the SiC stoichiometry from Si-rich to near-stoichiometric, the bonding configuration is modified to suppress excessive Cu ion migration, enabling gradual and stable conductance evolution. The resulting devices exhibit highly linear and programmable long-term potentiation and depression, with a low nonlinearity of 0.08, uniform conductance updates, and minimal cycle-to-cycle variation. The synaptic behavior is further shown to be controllable through pulse programming, enabling tunable multilevel conductance states. Using experimentally extracted device characteristics, we implement both artificial neural networks and convolutional neural networks to evaluate system-level performance. The memristor-based networks achieve classification accuracies exceeding 95% on MNIST and 90% on CIFAR-10, while maintaining robust performance under conductance discretisation and cycle-to-cycle variation. These results demonstrate a materials-driven approach to achieving linear and controllable synaptic behavior, establishing PECVD amorphous SiC as a strong candidate for high-precision and scalable neuromorphic computing systems.
Here we demonstrate high room-temperature Seebeck coefficient of 95 µV K−1 in combination with ultralow thermal conductivity of 0.18 W m−1 K−1 for a novel bimetallic p-type semiconducting coordination polymer. We synthesize the (Fe, Cu) bimetallic coordination polymer together with the single-metal Cu and Fe counterparts using 1,3,4,6- tetrathiapentalene-2,5-dione (TPD) as the organic ligand. The resultant poly[metal-ethylenetetrathiolate] materials are characterized by XPS (X-ray photoelectron spectroscopy) and Mössbauer spectroscopy techniques for the copper and iron metal oxidation states and with PPMS (physical property measurement system) for electronic and thermal transport properties in the temperature range of 100–350 K. The heterobimetallic effect in poly[(Fe, Cu)-ETT] is best appreciated regarding the enhanced Seebeck coefficient. We foresee that the present p-type poly[(Fe, Cu)-ETT] thermoelectrics could be a promising counterpart for the previously more widely investigated n-type conducting polymers.
In an effort to compete with the brain's efficiency at processing information, neuromorphic hardware combines artificial synapses and neurons using mixed-signal circuits and emerging memories. In ferroelectric resistive weights, the strength of the synaptic connection between two neurons is stored in the device conductance. During learning, programming pulses are applied to the synaptic weight, which reconfigures the ferroelectric domains and adjusts the conductance. One strategy to lower the energy cost during the training phase is to lower the duration of the programming pulses. However, the latter cannot be shorter than the self-loading time of the resistive weights, limited by intrinsic parasitics in the circuits. In this work, ferroelectric resistive weights are fabricated using a process compatible with CMOS Back-End-Of-Line integration, based on hafnia/zirconia nanolaminates. By laterally scaling the device area under 100