ACS Applied Electronic Materials最新文献

HfO₂-based floating body (FB) ferroelectric field-effect transistors (FeFETs) have attracted growing interest owing to their applicability across a broad range of applications, including embedded nonvolatile memory, advanced logic device, and high-density storage memory. However, efficient erase (ERS) operation in these devices is fundamentally hindered by the absence of a direct hole supply to the isolated FB, and the mechanisms governing alternative hole generation pathways and their role in polarization reset remain poorly understood. In particular, insufficient hole generation and supply to the floating string channel during block-level ERS operations of three-dimensional ferroelectric NAND (3D FeNAND) impose significant constraints on both ERS voltage and ERS speed, underscoring the need for a deeper understanding of hole dynamics.In this work, the key enabler for ERS operation in FB FeFETs is systematically identified by clarifying the correlation between hole dynamics and polarization reset. In-depth electrical characterization of silicon-on-insulator FeFETs reveals that, in conventional ERS schemes employing a negative gate bias, polarization reset is driven by gate-to-source/drain band-to-band tunneling-induced hole generation, while subsequent hole accumulation in the FB leads to anomalous threshold voltage (V_th) transitions. To improve ERS efficiency, a switching-assist pulse scheme is proposed, which enhances both reset speed and reset degree at a reduced ERS voltage. These findings offer practical design guidelines for optimized ERS schemes in high-density 3D FeNAND.

The development of self-rectifying memristors with reliable synaptic functionalities is critical for high-density neuromorphic computing systems. In this work, a memristor based on a WO₃/SiO₂ heterojunction was fabricated to achieve both intrinsic rectification behavior and biosynaptic characteristics. It is found that the device demonstrates reliable bipolar resistive switching featuring a pronounced asymmetric I−V response, enabling effective suppression of sneak current without the need for external selector devices. In particular, the incorporation of the SiO₂ interfacial layer regulates oxygen vacancy distribution and conductive filament dynamics, significantly improving switching uniformity, endurance, and retention performance. Detailed mechanism analysis reveals multiple conduction regimes, including Poole−Frenkel emission, Schottky emission, Hopping conduction, Fowler−Nordheim emission, direct tunneling, and Ohmic conduction, governed by electric field modulation. Furthermore, the memristor successfully emulates key synaptic behaviors, such as long-term potentiation or depression, paired-pulse facilitation, and spike-dependent plasticity through controllable conductance modulation under pulse stimuli. Neuromorphic simulations based on crossbar arrays demonstrate high pattern recognition accuracies on MNIST and Fashion MNIST datasets. These findings demonstrate the feasibility of the proposed memristor for energy-efficient and densely integrated neuromorphic computing hardware.

Reliable ferroelectric semiconductor devices are essential for memory and neuromorphic technologies; however, neutron-induced degradation pathways remain unclear. Here, we establish an integrated experimental framework, linking defect characterization with device-level electrical and synaptic evaluations to investigate neutron irradiation effects on α-In₂Se₃ ferroelectric semiconductor field-effect transistors (FeS-FETs). After neutron irradiation, energy-dispersive spectroscopy (EDS) reveals irradiation-induced compositional changes, while electrical analysis indicates an increased acceptor-like trap density (D_A(E)). These defect-related trap states disrupt polarization-dependent charge transport, leading to a substantial drain current reduction (∼88.95%), and degrade the memory-window-to-sweep-range ratio (MW/SR) (∼48.20%) and endurance characteristics. Synaptic functionality is also impaired, with increased nonlinearity and reduced dynamic range, which propagate to array-level synaptic weight uncertainty and degrade neural network inference accuracy. Overall, our results suggest that defect-related trap states are a key contributor to neutron-induced degradation in α-In₂Se₃ FeS-FETs. By clarifying this degradation pathway, this work provides insight into defect-related degradation mechanisms that may guide the future design of radiation-resilient ferroelectric memory and neuromorphic electronics.

Skin-interface pressure monitoring is essential for preventing pressure injuries caused by sustained mechanical loading between the human body and support surfaces. However, porous structure-based pressure sensors often exhibit high mechanical hysteresis and unstable response because of their intrinsic viscoelastic deformation and structural instability under repeated deformation, hindering reliable detection of sustained interface pressure. Herein, we report a fully flexible piezoresistive pressure sensor based on a carbon black (CB)/polydimethylsiloxane (PDMS)/ethyl cellulose (EC)-coated polyurethane (PU) sponge integrated with Ag nanowire (AgNW)-patterned textile electrodes. EC facilitated the formation of a continuous conductive coating on the PU sponge, while the pre-compression process during curing effectively reduced the mechanical hysteresis of the porous structure. The fabricated sensor exhibited a sensitivity of 0.019 kPa⁻¹ in the low-pressure range of 0−19 kPa, a broad sensing range up to 185 kPa, and stable cyclic performance over 3000 compression cycles of 100 kPa. The sensor enabled real-time monitoring of interface pressure at pressure-vulnerable body sites during postural changes. In addition, a pilot study with six participants of different body weights demonstrated the ability of the sensor to detect site-dependent interface pressure and body weight-related pressure trends. These results suggest that the developed sensor has potential for continuous interface pressure monitoring in healthcare and rehabilitation applications.

Overcoming the trade-off between strong photoresponse and fading memory remains a key challenge for efficient photonic reservoir computing based on photoactive materials. In this work, we demonstrate that Pt nanoparticle-embedded VO₂ devices can simultaneously enhance photocarrier generation and prolong photocarrier lifetime through heterogeneous nanoscale VO₂/Pt interfaces. A physical reservoir based on these devices resolves 16 distinct states under 4-bit optical input sequences and achieves an accuracy of 88.5% in sequence-encoded MNIST handwritten-digit classification, compared with 54.8% for pristine VO₂. Ultrafast transient absorption spectroscopy further confirms that Pt NPs reshape the photoexcited carrier dynamics in VO₂, leading to both improved photocarrier generation and an extended dominant carrier lifetime (3.86 ± 0.18 ns vs 2.60 ± 0.03 ns). These results suggest that nanoscale engineering of metal/oxide interfaces offers an effective materials-level strategy for improving temporal information processing in future photonic neuromorphic computing systems.

Selector-only memory (SOM) has attracted attention as a promising memory technology because it enables programmable threshold-voltage state separation using a single ovonic threshold switch (OTS) device. In SOM devices, the electrode–chalcogenide interface strongly affects the threshold-voltage difference (ΔV_th) and switching reliability, as repetitive switching induces interfacial reactions and elemental diffusion. In this study, the electrode-dependent SOM characteristics of Ge₂Se₃Te₅ (GST) devices were investigated using W, TiN, and W with an ultrathin (∼6 nm) carbon interlayer (W/C) as top electrodes. The W/C device exhibited the largest ΔV_th (∼1.0 V) and the widest read window margin (∼0.9 V), and maintained a ΔV_th exceeding 0.7 V over repeated switching cycles, exhibiting the most stable characteristics. Conduction mechanism analysis based on the Poole–Frenkel emission model, Arrhenius analysis, and the thermally assisted hopping model revealed that the enhanced ΔV_th originates from increased trap-state separation and trap-density difference between programmed states. Transmission electron microscopy coupled with energy-dispersive X-ray spectroscopy (TEM-EDS) and line-EDS analyses confirmed that the carbon interlayer effectively suppressed Te diffusion and interfacial phase formation at the W/GST interface during repetitive switching. These results demonstrate that ultrathin carbon interfacial engineering is an effective strategy for improving ΔV_th and switching reliability in GST SOM devices.

As micro-light-emitting diode (Micro-LED) pixel dimensions continue to scale down, compact driving devices that can be directly integrated with GaN light-emitting diodes are increasingly required. Here, we employ a monolithic integration scheme in which the underlying n-GaN layer serves as both the Micro-LED cathode and a buried bias electrode for the p-type carbon nanotube thin-film transistor (CNT TFT), thereby constructing a normally-on CNT TFT/Micro-LED pixel architecture. The negatively biased n-GaN layer electrostatically turns on the CNT channel through the intervening dielectric. Compared with conventional local-gate control, n-GaN control maintains comparable switching behavior, with a 10.1% increase in average subthreshold swing and an average threshold-voltage shift of 0.18 V across 60 devices. The CNT TFT is further integrated with a Micro-LED to form a one-transistor–one-diode (1T1D) CNT TFT/Micro-LED pixel, exhibiting clear gate-controlled current modulation and reproducible switching behavior. Based on this architecture, a 3 × 3 CNT TFT/Micro-LED array was fabricated as a proof-of-concept demonstration. Under data-line selection and with no scan signal applied, the corresponding columns operate in a normally-on state, while applied scan voltages modulate or suppress emission at selected data-line/scan-line intersections. This work demonstrates a normally-on, scan-suppressed addressing mode and provides a compact strategy for monolithic GaN/CNT optoelectronic integration without device transfer or bonding.

Visible-light-responsive optoelectronic synapses are attracting increasing attention for neuromorphic vision systems because they integrate optical sensing and information processing within a single device. However, conventional oxide semiconductor phototransistors are generally limited by their wide bandgap, resulting in weak visible-light absorption and insufficient synaptic performance. Here, we demonstrate a thickness-optimized TeO_x/IZO heterojunction optoelectronic synaptic phototransistor that achieves efficient visible-light sensing and neuromorphic functionality through enhanced photocarrier generation and defect-assisted carrier trapping. Systematic optimization of the TeO_x layer reveals that a thickness of 5 nm provides the optimum balance between visible-light absorption, electrical switching characteristics, and carrier transport. The optimized device exhibits a low dark current of approximately 1 × 10⁻¹² A, a high on/off current ratio of ∼10⁸, and wavelength-dependent photoresponse enhancements of up to 2377.6% under green-light illumination compared with pristine IZO devices. Furthermore, the device successfully emulates essential synaptic functions, including excitatory postsynaptic current, short- and long-term memory, paired-pulse facilitation, and long-term potentiation/depression, while achieving a handwritten digit recognition accuracy of ∼88%. X-ray photoelectron spectroscopy, spectroscopic ellipsometry, and photo-induced current transient spectroscopy reveal that the superior photosynaptic performance originates from an optimal balance among visible-light absorption, interfacial carrier transfer, and shallow-defect-assisted carrier trapping. These results establish the TeO_x/IZO heterojunction as an effective platform for oxide-based visible-light neuromorphic vision systems.

Among nanocrystals (NCs)/quantum dots (QDs), halide perovskite NCs/QDs have emerged as promising nanomaterials owing to their tunable band gaps, efficient charge transport, defect tolerance, high absorption coefficients, and low manufacturing costs. In this work, we successfully synthesized CsPbBr₃ nanocrystals (PNCs) and applied them as an interfacial layer between the dye and the electrolyte to improve the performance of dye-sensitized solar cells (DSSCs). It was revealed that PNCs not only act as co-sensitizers, thereby improving light harvesting but also as hole-transporting materials, thereby enhancing charge separation and transport within the device. These PNCs exhibit defects during synthesis that act as traps for charge transport. It was found that the N719 dye bonded to the PNCs, thereby suppressing defects and recombination losses. The synergistic effect of PNC-hole transport and N719-dye-induced defect passivation significantly enhances device performance. Photovoltaic parameters, including short-circuit current density (J_SC), open-circuit voltage (V_OC), fill factor (FF), and overall power conversion efficiency, were systematically evaluated. A high PCE of 14.21% was achieved in a DSSC using a combination of PNCs and the N719 dye. Overall, this work highlights an effective strategy to improve DSSC efficiency through defect engineering and interfacial optimization and offers valuable insights for the future development of high-performance DSSCs.

Metal-induced gap states (MIGS) and Fermi-level pinning (FLP) are major obstacles to achieving optimal spin injection efficiency at metal/magnetic semiconductor interfaces. This study demonstrates that integrating the transition metals (Ag, Co, Cu, and Ni) via van der Waals interactions with the two-dimensional bipolar magnetic semiconductor monolayer LaBr₂ effectively suppresses these detrimental interfacial effects. The weak interlayer orbital hybridization drastically restrains MIGS generation and yields nearly ideal FLP with a pinning factor S ≈ 0.99, approaching the ideal Schottky–Mott limit. This high-quality interface preserves the intrinsic spin-split band structure of LaBr₂, facilitating strongly spin-dependent Schottky barriers. Particularly, the Ni/LaBr₂ junction exhibits a near-Ohmic contact for spin-up holes (0.03 eV barrier) and a Schottky barrier for spin-down electrons (0.21 eV barrier), enabling near-unity spin-filtering efficiency. Leveraging this asymmetry, we design a dual-gate Ni/LaBr₂ field-effect transistor that generates 100% spin-polarized currents under uniform gate biases and switches to a high-resistance state under opposing biases, achieving on/off ratios up to 10⁵ at a low bias of 0.08 V. This device successfully integrates spin-filtering and spin-valve functionalities within a single architecture. Although the intrinsic Curie temperature (≈280 K) necessitates post-synthetic enhancement for room-temperature operation, this study establishes an interfacial design paradigm and material platform for developing low-power, integrated multifunctional spintronic devices.