Controlling particles in wafer dicing chip-to-wafer (C2W) hybrid bonding has been a vital issue for yield assurance. In this study, laser dicing, blade dicing and plasma dicing are first compared and plasma dicing is considered as the cleanest dicing method. Second, wafer surface protection by photoresist AZ4620 and a PDMS adhesion layer before wafer dicing is investigated. It is found that a thick protective layer mixing photoresist and PDMS together provides better protection effect, reducing particle density from 47.25 mm−2 to 19.71 mm−2. Then, surface protection of SiO2 by surface energy reduction is accomplished by spin-coating AR300-80-new and CF4 plasma treatment. The particle density shows a more significant decrease after CF4 plasma, owing to its greater effectiveness to lower dispersive component ($gamma _{mathrm {sd}}$ ) and the effect of increasing surface roughness. Finally, the particle density is further reduced by PDMS adhesion from 19.71 mm−2 to 7.60 mm−2. PDMS residue on the chip surface is detected by dynamic secondary ion mass spectroscopy (D-SIMS), and removed by O2 plasma treatment. The results provide feasible suggestions and approaches to decrease the deposition and adhesion of the particle generated from wafer dicing in C2W hybrid bonding.
{"title":"Particle Removal by Surface Protection and Adhesion in the Wafer Dicing Applied to Chip-to-Wafer Hybrid Bonding","authors":"Hao Wang;Haoyue Song;Ziyu Liu;Jingxuan Wei;Han Jiang;Yabin Sun;Hao Zhu;Qingqing Sun;David Wei Zhang","doi":"10.1109/TSM.2026.3711856","DOIUrl":"https://doi.org/10.1109/TSM.2026.3711856","url":null,"abstract":"Controlling particles in wafer dicing chip-to-wafer (C2W) hybrid bonding has been a vital issue for yield assurance. In this study, laser dicing, blade dicing and plasma dicing are first compared and plasma dicing is considered as the cleanest dicing method. Second, wafer surface protection by photoresist AZ4620 and a PDMS adhesion layer before wafer dicing is investigated. It is found that a thick protective layer mixing photoresist and PDMS together provides better protection effect, reducing particle density from 47.25 mm−2 to 19.71 mm−2. Then, surface protection of SiO2 by surface energy reduction is accomplished by spin-coating AR300-80-new and CF4 plasma treatment. The particle density shows a more significant decrease after CF4 plasma, owing to its greater effectiveness to lower dispersive component (<inline-formula> <tex-math>$gamma _{mathrm {sd}}$ </tex-math></inline-formula>) and the effect of increasing surface roughness. Finally, the particle density is further reduced by PDMS adhesion from 19.71 mm−2 to 7.60 mm−2. PDMS residue on the chip surface is detected by dynamic secondary ion mass spectroscopy (D-SIMS), and removed by O2 plasma treatment. The results provide feasible suggestions and approaches to decrease the deposition and adhesion of the particle generated from wafer dicing in C2W hybrid bonding.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"531-539"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-07-16DOI: 10.1109/TSM.2026.3714028
Dan Jiang;Songbin Li;Yisheng Sun
To address the challenges of high missed detection rates and low localization accuracy in existing wafer surface scratch detection algorithms, this paper proposes WSD-YOLO, a lightweight scratch detection method for backend packaging AOI inspection. First, the method introduces a strip convolution block to effectively suppress interference from background texture noise. Second, it integrates the content-aware attentional multi-scale aggregation module to recover high-resolution spatial details and reinforce feature semantic consistency and spatial localization capabilities. Moreover, the detection head is optimized by replacing the low-resolution P5 layer with a high-resolution P2 layer, which significantly enhances detection precision for extremely tiny targets. Finally, a task-oriented hybrid loss, termed Dynamic Angle-Inner IoU (DAI-IoU), is employed by combining SIoU, Inner-IoU, and Wise-IoU to improve bounding-box regression for slender micro-scratches. Experiments on the self-constructed dataset show that WSD-YOLO achieves 79.5% precision, 84.3% recall, 84.8% mAP50, and 46.3% mAP50-95 while maintaining 2.9 M parameters, 22.8 GFLOPs, and 127 FPS under the current experimental setup.
{"title":"Micro-Scratch Detection on Wafer Surfaces Based on Strip Convolution and High-Resolution Feature Reconstruction","authors":"Dan Jiang;Songbin Li;Yisheng Sun","doi":"10.1109/TSM.2026.3714028","DOIUrl":"https://doi.org/10.1109/TSM.2026.3714028","url":null,"abstract":"To address the challenges of high missed detection rates and low localization accuracy in existing wafer surface scratch detection algorithms, this paper proposes WSD-YOLO, a lightweight scratch detection method for backend packaging AOI inspection. First, the method introduces a strip convolution block to effectively suppress interference from background texture noise. Second, it integrates the content-aware attentional multi-scale aggregation module to recover high-resolution spatial details and reinforce feature semantic consistency and spatial localization capabilities. Moreover, the detection head is optimized by replacing the low-resolution P5 layer with a high-resolution P2 layer, which significantly enhances detection precision for extremely tiny targets. Finally, a task-oriented hybrid loss, termed Dynamic Angle-Inner IoU (DAI-IoU), is employed by combining SIoU, Inner-IoU, and Wise-IoU to improve bounding-box regression for slender micro-scratches. Experiments on the self-constructed dataset show that WSD-YOLO achieves 79.5% precision, 84.3% recall, 84.8% mAP50, and 46.3% mAP50-95 while maintaining 2.9 M parameters, 22.8 GFLOPs, and 127 FPS under the current experimental setup.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"430-440"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-06-26DOI: 10.1109/TSM.2026.3707558
Luis F. Garcia;Stefano Rini;Shun C. Chang;Ying C. Hsu
Semiconductor manufacturing data sharing is constrained by intellectual property (IP) concerns, which makes it difficult to apply collaborative learning even when multiple installations of the same equipment exist. This paper studies the applicability of adversarial variational autoencoders (VAE) as a practical sanitization mechanism for this setting. Sensitive process variables are specified by a domain expert, and the model is trained to preserve utility while making those variables harder to infer from the released representation. We evaluate the approach on native semiconductor manufacturing time-series runs, first in the original single-party setting and then in a small multi-peer extension with local and joint adversaries. The results suggest a privacy-utility trade-off: sanitized representations retain the main public operating regimes while degrading reconstruction of the protected variables. The distributed study further shows that leakage must be evaluated after aggregation, not only per peer. These results position adversarial VAE sanitization as a useful applied tool for semiconductor data sharing, while also highlighting the limitations of the current centralized simulation and small number of available runs.
{"title":"Adversarial VAE Sanitization for Privacy-Aware Data Sharing in Semiconductor Manufacturing","authors":"Luis F. Garcia;Stefano Rini;Shun C. Chang;Ying C. Hsu","doi":"10.1109/TSM.2026.3707558","DOIUrl":"https://doi.org/10.1109/TSM.2026.3707558","url":null,"abstract":"Semiconductor manufacturing data sharing is constrained by intellectual property (IP) concerns, which makes it difficult to apply collaborative learning even when multiple installations of the same equipment exist. This paper studies the applicability of adversarial variational autoencoders (VAE) as a practical sanitization mechanism for this setting. Sensitive process variables are specified by a domain expert, and the model is trained to preserve utility while making those variables harder to infer from the released representation. We evaluate the approach on native semiconductor manufacturing time-series runs, first in the original single-party setting and then in a small multi-peer extension with local and joint adversaries. The results suggest a privacy-utility trade-off: sanitized representations retain the main public operating regimes while degrading reconstruction of the protected variables. The distributed study further shows that leakage must be evaluated after aggregation, not only per peer. These results position adversarial VAE sanitization as a useful applied tool for semiconductor data sharing, while also highlighting the limitations of the current centralized simulation and small number of available runs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"381-387"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-07-09DOI: 10.1109/TSM.2026.3711401
Haomiao Cheng;Wenyan Wang;Dawei Bi;Zhiyuan Hu
As RF technologies continue to scale, the direct integration of airgap structures significantly narrows the back-end-of-line (BEOL) process window and introduces yield-sensitive integration challenges, resulting in severe wafer-level yield degradation. In this work, major airgap-related failure modes are identified, including abnormal airgap morphology and contact/via missing. The root causes of airgap-induced yield loss are systematically investigated, and a coordinated process–layout optimization strategy is developed, including reconfiguration of the IMD stack and enhancement of overlap margins. Wafer-level yield results demonstrate that the proposed optimization effectively suppresses airgap-related failures, stabilizing the overall yield above 99.4%. Stability and reliability of the process window are confirmed through FEM experiments.
{"title":"Failure Analysis and Process Optimization for Airgap-Induced Yield Degradation in RF Process","authors":"Haomiao Cheng;Wenyan Wang;Dawei Bi;Zhiyuan Hu","doi":"10.1109/TSM.2026.3711401","DOIUrl":"https://doi.org/10.1109/TSM.2026.3711401","url":null,"abstract":"As RF technologies continue to scale, the direct integration of airgap structures significantly narrows the back-end-of-line (BEOL) process window and introduces yield-sensitive integration challenges, resulting in severe wafer-level yield degradation. In this work, major airgap-related failure modes are identified, including abnormal airgap morphology and contact/via missing. The root causes of airgap-induced yield loss are systematically investigated, and a coordinated process–layout optimization strategy is developed, including reconfiguration of the IMD stack and enhancement of overlap margins. Wafer-level yield results demonstrate that the proposed optimization effectively suppresses airgap-related failures, stabilizing the overall yield above 99.4%. Stability and reliability of the process window are confirmed through FEM experiments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"472-477"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-06-17DOI: 10.1109/TSM.2026.3704346
Damien Monteil;Delphine Le Cunff;Romain Duru;Virginie Brouzet;Clément Sart;Nicolas Kubler;Caroline Bringolf-Penner;Corentin Le Maoult;Emmanuel Nolot;Van Hoan Le;Michel Mermoux
In this work, we propose using Raman spectroscopy to measure mechanical strain in silicon induced by High Aspect Ratio (HAR) trench arrays. Strain operates at different scales and can be measured by different techniques, each with specific sensitivities and probe sizes. Raman spectroscopy is interesting because it can analyze strain in ultra-thin or 3D structures down to less than $mathbf {10^{-4}}$ , with submicron lateral resolution. Comparisons with profilometry, mechanical simulation and morphological analyses illustrate the potential of Raman spectroscopy as a new in-line technique for the strain metrology.
{"title":"Contribution of Raman Spectroscopy to Strain Metrology in Trench Array Structures","authors":"Damien Monteil;Delphine Le Cunff;Romain Duru;Virginie Brouzet;Clément Sart;Nicolas Kubler;Caroline Bringolf-Penner;Corentin Le Maoult;Emmanuel Nolot;Van Hoan Le;Michel Mermoux","doi":"10.1109/TSM.2026.3704346","DOIUrl":"https://doi.org/10.1109/TSM.2026.3704346","url":null,"abstract":"In this work, we propose using Raman spectroscopy to measure mechanical strain in silicon induced by High Aspect Ratio (HAR) trench arrays. Strain operates at different scales and can be measured by different techniques, each with specific sensitivities and probe sizes. Raman spectroscopy is interesting because it can analyze strain in ultra-thin or 3D structures down to less than <inline-formula> <tex-math>$mathbf {10^{-4}}$ </tex-math></inline-formula>, with submicron lateral resolution. Comparisons with profilometry, mechanical simulation and morphological analyses illustrate the potential of Raman spectroscopy as a new in-line technique for the strain metrology.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"417-424"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-06-25DOI: 10.1109/TSM.2026.3707466
Raymond van Roijen;William Tamm;Amelia Rettmann;Janice Paduano;Steve Schneider;Noah Osinski;Lori Kermel;Qifang Qiao
Semiconductor Fabs consume substantial amounts of energy, mainly in the form of electric power, to operate manufacturing equipment and to rigorously control the environment in the Fab. Heating and cooling of the cleanroom and the equipment is a significant part of the energy demand. We have found opportunities to reduce the demand by carefully calibrated changes of two systems, the control of relative humidity (RH) in the cleanroom and the way in which we supply cooling water to the equipment. Varying these conditions can lower energy consumption and cost, but it can also affect the production process in a number of ways. To avoid adverse effects we established a list of potential issues and a plan to prevent any deviations. We then varied RH in a controlled fashion and verified that production can continue without issues. A similar approach was used to make a change to the cooling water supply. By equalizing the temperature between two separate systems used across tool platforms and then connecting these systems we gain efficiency, reduce complexity and save energy. As with the humidity change the challenge is to ensure there is no impact across all equipment affected by the change. We achieved a significant reduction of energy consumption through these changes.
{"title":"Reduction of Energy Consumption Through Fab Environment Adjustment","authors":"Raymond van Roijen;William Tamm;Amelia Rettmann;Janice Paduano;Steve Schneider;Noah Osinski;Lori Kermel;Qifang Qiao","doi":"10.1109/TSM.2026.3707466","DOIUrl":"https://doi.org/10.1109/TSM.2026.3707466","url":null,"abstract":"Semiconductor Fabs consume substantial amounts of energy, mainly in the form of electric power, to operate manufacturing equipment and to rigorously control the environment in the Fab. Heating and cooling of the cleanroom and the equipment is a significant part of the energy demand. We have found opportunities to reduce the demand by carefully calibrated changes of two systems, the control of relative humidity (RH) in the cleanroom and the way in which we supply cooling water to the equipment. Varying these conditions can lower energy consumption and cost, but it can also affect the production process in a number of ways. To avoid adverse effects we established a list of potential issues and a plan to prevent any deviations. We then varied RH in a controlled fashion and verified that production can continue without issues. A similar approach was used to make a change to the cooling water supply. By equalizing the temperature between two separate systems used across tool platforms and then connecting these systems we gain efficiency, reduce complexity and save energy. As with the humidity change the challenge is to ensure there is no impact across all equipment affected by the change. We achieved a significant reduction of energy consumption through these changes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"425-429"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-06-11DOI: 10.1109/TSM.2026.3702103
Ya Peng;Zuozuo Wu;Wei Zhou;Yangjian Li;Jianwei Cao;Shuai Yuan;Deren Yang
Chemical mechanical polishing (CMP), as the only route to obtain global planarization at present, is widely used in the manufacturing process of semiconductors. SiO2 polishing slurry finds extensive application in CMP, primarily due to the fact that SiO2 abrasives exhibit moderate hardness and exceptionally outstanding chemical and mechanical properties. Clarifying the effect of SiO2 polishing slurry on semiconductor materials and its underlying mechanism is of great significance for optimizing the polishing process. This study conducts a comprehensive literature review and in-depth analysis to systematically summarize the effects of SiO2 polishing slurry on semiconductor materials during CMP, and deeply reveals the corresponding action mechanisms. Specifically, it focuses on the influences of key components in SiO2 slurry, which including SiO2 abrasives, alkaline pH regulators, oxidants, and other additives, on the CMP performance of semiconductor materials. Through theoretical analysis, the research elaborates on the chemical reactions of each component at the molecular or atomic level and clarifies the micro-mechanisms of interaction between abrasives, chemical components, and semiconductor material surfaces during the polishing process. This review not only establishes a theoretical framework for understanding the relationship between SiO2 polishing slurry and IC semiconductor materials but also provides constructive References for optimizing the polishing process of large-sized silicon wafers.
{"title":"Effect and Mechanism of SiO2 Polishing Slurry on Chemical Mechanical Polishing Technology in Semiconductor Manufacturing","authors":"Ya Peng;Zuozuo Wu;Wei Zhou;Yangjian Li;Jianwei Cao;Shuai Yuan;Deren Yang","doi":"10.1109/TSM.2026.3702103","DOIUrl":"https://doi.org/10.1109/TSM.2026.3702103","url":null,"abstract":"Chemical mechanical polishing (CMP), as the only route to obtain global planarization at present, is widely used in the manufacturing process of semiconductors. SiO2 polishing slurry finds extensive application in CMP, primarily due to the fact that SiO2 abrasives exhibit moderate hardness and exceptionally outstanding chemical and mechanical properties. Clarifying the effect of SiO2 polishing slurry on semiconductor materials and its underlying mechanism is of great significance for optimizing the polishing process. This study conducts a comprehensive literature review and in-depth analysis to systematically summarize the effects of SiO2 polishing slurry on semiconductor materials during CMP, and deeply reveals the corresponding action mechanisms. Specifically, it focuses on the influences of key components in SiO2 slurry, which including SiO2 abrasives, alkaline pH regulators, oxidants, and other additives, on the CMP performance of semiconductor materials. Through theoretical analysis, the research elaborates on the chemical reactions of each component at the molecular or atomic level and clarifies the micro-mechanisms of interaction between abrasives, chemical components, and semiconductor material surfaces during the polishing process. This review not only establishes a theoretical framework for understanding the relationship between SiO2 polishing slurry and IC semiconductor materials but also provides constructive References for optimizing the polishing process of large-sized silicon wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"503-514"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sustainability has emerged as a defining challenge for semiconductor fabs, where enormous energy demand, high-value equipment, and growing spatial constraints converge. Although prior studies have emphasized environmental considerations, they often lack actionable solutions aligned with fab-level operations. This paper advances the concept of the Sustainable Fab, articulated through three dimensions: environmental responsibility, cost efficiency, and optimized space utilization. Environmentally, we demonstrate practical reductions in utility consumption by implementing liquefied natural gas (LNG) flow control schemes and rationalizing hot N2 delivery without compromising process safety. For cost efficiency, we highlight strategies such as extending the lifespan of legacy vertical-NAND multilayered oxide/nitride layer deposition (MOLD) process tools through targeted retrofits and improving dual tank liquid refill (DTLR) systems to reduce unit counts, thereby lowering both capital investment and sub-fab infrastructure demand. From the perspective of space utilization, we introduce new density-based metrics—equipment station density (ESD) and facility station density (FSD)—to evaluate the transfer of productivity gains from tools to the fab level, and propose form factor–guided equipment designs to mitigate footprint mismatches. Collectively, these strategies provide an integrated framework that embeds sustainability into process, equipment, and facility domains, enabling scalable pathways for long-term competitiveness in semiconductor manufacturing.
{"title":"Toward Sustainable Fab Operation: Environment, Cost, and Space Optimization in Semiconductor Manufacturing","authors":"Mingyo Byeon;Dongjoon Myung;Seungcheol Han;Moonseok Jang;Jin-Hyuk Kim;Changsoo Lee;Chulhwan Choi","doi":"10.1109/TSM.2026.3694871","DOIUrl":"https://doi.org/10.1109/TSM.2026.3694871","url":null,"abstract":"Sustainability has emerged as a defining challenge for semiconductor fabs, where enormous energy demand, high-value equipment, and growing spatial constraints converge. Although prior studies have emphasized environmental considerations, they often lack actionable solutions aligned with fab-level operations. This paper advances the concept of the Sustainable Fab, articulated through three dimensions: environmental responsibility, cost efficiency, and optimized space utilization. Environmentally, we demonstrate practical reductions in utility consumption by implementing liquefied natural gas (LNG) flow control schemes and rationalizing hot N2 delivery without compromising process safety. For cost efficiency, we highlight strategies such as extending the lifespan of legacy vertical-NAND multilayered oxide/nitride layer deposition (MOLD) process tools through targeted retrofits and improving dual tank liquid refill (DTLR) systems to reduce unit counts, thereby lowering both capital investment and sub-fab infrastructure demand. From the perspective of space utilization, we introduce new density-based metrics—equipment station density (ESD) and facility station density (FSD)—to evaluate the transfer of productivity gains from tools to the fab level, and propose form factor–guided equipment designs to mitigate footprint mismatches. Collectively, these strategies provide an integrated framework that embeds sustainability into process, equipment, and facility domains, enabling scalable pathways for long-term competitiveness in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"647-658"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The accuracy of the resonant frequency directly determines the fundamental performance and application value of the microelectromechanical systems (MEMS) resonator. However, current methods exhibit inherent limitations, including the cumbersome and time-consuming nature of finite element simulation techniques, as well as the difficulty of traditional machine learning methods in effectively learning physical laws during prediction, which may lead to results that contradict established physical principles. This paper proposes a physically constrained dual-channel neural network framework (PhyC-DCF), which aims to address the issue of prediction results contradicting physical principles by embedding physical prior knowledge, providing an efficient and accurate resonant frequency prediction tool for MEMS resonators. PhyC-DCF comprises a target resonant mode channel and an auxiliary resonant mode channel, which predict their respective resonant frequencies. The auxiliary channel integrates target features through resonant mode coupling mechanism, enabling complementary feature learning. Subsequently, a hybrid loss with physical constraints exploits resonator physics to guide training. The PhyC-DCF not only reduces error metrics but also effectively suppresses physically inconsistent phenomena such as frequency inversion, thereby providing an efficient and reliable computational tool for resonator design.
{"title":"Physically Constrained Dual-Channel Neural Network Framework for MEMS Frequency Prediction","authors":"Zhiming Yang;Wei Zhao;Yongkang Liu;Haochen Lyu;Yuandong Gu","doi":"10.1109/TSM.2026.3707110","DOIUrl":"https://doi.org/10.1109/TSM.2026.3707110","url":null,"abstract":"The accuracy of the resonant frequency directly determines the fundamental performance and application value of the microelectromechanical systems (MEMS) resonator. However, current methods exhibit inherent limitations, including the cumbersome and time-consuming nature of finite element simulation techniques, as well as the difficulty of traditional machine learning methods in effectively learning physical laws during prediction, which may lead to results that contradict established physical principles. This paper proposes a physically constrained dual-channel neural network framework (PhyC-DCF), which aims to address the issue of prediction results contradicting physical principles by embedding physical prior knowledge, providing an efficient and accurate resonant frequency prediction tool for MEMS resonators. PhyC-DCF comprises a target resonant mode channel and an auxiliary resonant mode channel, which predict their respective resonant frequencies. The auxiliary channel integrates target features through resonant mode coupling mechanism, enabling complementary feature learning. Subsequently, a hybrid loss with physical constraints exploits resonator physics to guide training. The PhyC-DCF not only reduces error metrics but also effectively suppresses physically inconsistent phenomena such as frequency inversion, thereby providing an efficient and reliable computational tool for resonator design.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"636-646"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid development of semiconductor technology and the continuous scaling down of circuit feature sizes, hotspot detection has become an increasingly critical task in the workflow. Although most deep learning models have been widely applied to this task, many still suffer from low accuracy and a high number of false alarms when dealing with class-imbalanced datasets. To address these issues, we propose a deep learning model based on dual-branch feature extraction and attention enhancement. This model consists of two parallel feature extraction branches. The first leverages a MetaDCNeXt architecture to capture spatial structural features of hotspots, while the second employs a multi-DenseConvSE architecture to extract semantic features through dense connections and channel attention. A positional convolutional block attention module is used to fuse the outputs from both branches, suppressing redundant information and emphasizing critical features. Experimental results on the ICCAD 2012 benchmark demonstrate that our model achieves the lowest average number of false alarms and the highest average F1 score, with its overall performance significantly surpassing all compared detectors.
{"title":"Lithographic Hotspot Detection Based on Dual-Branch Feature Fusion and Attention Augmentation","authors":"Hui Xu;Yunhong Huo;Guoshuai Wang;Ruijun Ma;Wenjun Wang;Chenlong Zhou;Zhengfeng Huang","doi":"10.1109/TSM.2026.3704426","DOIUrl":"https://doi.org/10.1109/TSM.2026.3704426","url":null,"abstract":"With the rapid development of semiconductor technology and the continuous scaling down of circuit feature sizes, hotspot detection has become an increasingly critical task in the workflow. Although most deep learning models have been widely applied to this task, many still suffer from low accuracy and a high number of false alarms when dealing with class-imbalanced datasets. To address these issues, we propose a deep learning model based on dual-branch feature extraction and attention enhancement. This model consists of two parallel feature extraction branches. The first leverages a MetaDCNeXt architecture to capture spatial structural features of hotspots, while the second employs a multi-DenseConvSE architecture to extract semantic features through dense connections and channel attention. A positional convolutional block attention module is used to fuse the outputs from both branches, suppressing redundant information and emphasizing critical features. Experimental results on the ICCAD 2012 benchmark demonstrate that our model achieves the lowest average number of false alarms and the highest average F1 score, with its overall performance significantly surpassing all compared detectors.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"478-486"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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