Pub Date : 2026-08-01Epub Date: 2026-06-15DOI: 10.1109/TSM.2026.3703561
Se Yun Jo;Sang Jeen Hong
In the semiconductor industry, the reproducibility and repeatability of manufacturing process are most important to ensure the product quality to be consistent. The in-situ dry-cleaning (ISD) process of plasma enhanced chemical vapor deposition (PECVD) is performed between the material deposition steps to eliminate contaminants and improve reproducibility. COF2 is one of the candidates for the alternative cleaning gas of conventional use of NF3 because of its low GWP value. In our previous studies, we investigated COF2 cleaning gas with remote plasma source (RPS) dry-cleaning process and proposed additive gas O2 to reduce cleaning inhibitor and enhance cleaning rate. In this study, a further investigation with additive gases of O2 and N2O to enhance cleaning efficiency. We found that the mixture of O2 and N2O can enhance the dry-cleaning efficiency with COF2. Chemical reaction mechanisms and production rate of species changes with numerical analysis were investigated to enhance the cleaning efficiency. We postulate that the higher cleaning rate gears from the increased amount of oxygen atom and radical production rate. Cleaning rates of SiO2 films with NF3 and COF2 were also experimentally compared, and we suggested that the use of COF2 with the additive mixture of O2 and N2O is evident to replace NF3 for the dry-cleaning gas for the environmental consideration with low GWP.
{"title":"Enhancement of PECVD Chamber Dry-Cleaning With Carbonyl Fluoride by Additive Gases","authors":"Se Yun Jo;Sang Jeen Hong","doi":"10.1109/TSM.2026.3703561","DOIUrl":"https://doi.org/10.1109/TSM.2026.3703561","url":null,"abstract":"In the semiconductor industry, the reproducibility and repeatability of manufacturing process are most important to ensure the product quality to be consistent. The in-situ dry-cleaning (ISD) process of plasma enhanced chemical vapor deposition (PECVD) is performed between the material deposition steps to eliminate contaminants and improve reproducibility. COF2 is one of the candidates for the alternative cleaning gas of conventional use of NF3 because of its low GWP value. In our previous studies, we investigated COF2 cleaning gas with remote plasma source (RPS) dry-cleaning process and proposed additive gas O2 to reduce cleaning inhibitor and enhance cleaning rate. In this study, a further investigation with additive gases of O2 and N2O to enhance cleaning efficiency. We found that the mixture of O2 and N2O can enhance the dry-cleaning efficiency with COF2. Chemical reaction mechanisms and production rate of species changes with numerical analysis were investigated to enhance the cleaning efficiency. We postulate that the higher cleaning rate gears from the increased amount of oxygen atom and radical production rate. Cleaning rates of SiO2 films with NF3 and COF2 were also experimentally compared, and we suggested that the use of COF2 with the additive mixture of O2 and N2O is evident to replace NF3 for the dry-cleaning gas for the environmental consideration with low GWP.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"659-669"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-03-18DOI: 10.1109/TSM.2026.3694257
Seunghyon Kang;Hyeonghun Kim;Boris Kramer
This work presents the application of parametric Operator Inference (OpInf)—a nonintrusive reduced-order modeling (ROM) technique that learns a low-dimensional representation of a high-fidelity model—to the numerical model of the purging process in semiconductor manufacturing. Leveraging the data-driven nature of the OpInf framework, we aim to forecast the flow field within a plasma-enhanced chemical vapor deposition (PECVD) chamber using computational fluid dynamics (CFD) simulation data. Our model simplifies the system by excluding plasma dynamics and chemical reactions, while still capturing the key features of the purging flow behavior. The parametric OpInf framework learns nine ROMs based on varying argon mass flow rates at the inlet and different outlet pressures. It then interpolates these ROMs to predict the system’s behavior for 25 parameter combinations, including 16 scenarios that are not seen in training. The parametric OpInf ROMs, trained on 36% of the data and tested on 64%, demonstrate accuracy across the entire parameter domain, with a maximum error of 9.32%. Furthermore, the ROM achieves an approximate 142-fold speedup in online computations compared to the full-order model CFD simulation. These OpInf ROMs may be used for fast and accurate predictions of the purging flow in the PECVD chamber, which could facilitate effective particle contamination control in semiconductor manufacturing.
{"title":"Parametric Operator Inference to Simulate the Purging Process in Semiconductor Manufacturing","authors":"Seunghyon Kang;Hyeonghun Kim;Boris Kramer","doi":"10.1109/TSM.2026.3694257","DOIUrl":"https://doi.org/10.1109/TSM.2026.3694257","url":null,"abstract":"This work presents the application of parametric Operator Inference (OpInf)—a nonintrusive reduced-order modeling (ROM) technique that learns a low-dimensional representation of a high-fidelity model—to the numerical model of the purging process in semiconductor manufacturing. Leveraging the data-driven nature of the OpInf framework, we aim to forecast the flow field within a plasma-enhanced chemical vapor deposition (PECVD) chamber using computational fluid dynamics (CFD) simulation data. Our model simplifies the system by excluding plasma dynamics and chemical reactions, while still capturing the key features of the purging flow behavior. The parametric OpInf framework learns nine ROMs based on varying argon mass flow rates at the inlet and different outlet pressures. It then interpolates these ROMs to predict the system’s behavior for 25 parameter combinations, including 16 scenarios that are not seen in training. The parametric OpInf ROMs, trained on 36% of the data and tested on 64%, demonstrate accuracy across the entire parameter domain, with a maximum error of 9.32%. Furthermore, the ROM achieves an approximate 142-fold speedup in online computations compared to the full-order model CFD simulation. These OpInf ROMs may be used for fast and accurate predictions of the purging flow in the PECVD chamber, which could facilitate effective particle contamination control in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"625-635"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ultra-thin and flexible chips are essential for high-performance flexible electronic devices, whose large-scale fabrication relies on reliable ultra-thin wafers. Circuit probing test of ultra-thin wafers plays a crucial role in screening functional chips prior to packaging; however, wafer warpage and fragility pose significant challenges to such testing. In this study, the stress distribution in ultra-thin wafers temporarily supported during circuit probing is analyzed based on layered elasticity theory. A wafer failure phase diagram is subsequently established, from which a selection strategy for temporary support materials is proposed to enhance the mechanical resistance of ultra-thin wafers against probing forces. The analysis reveals that higher Young’s modulus and thinner temporary supports enable safer probing. Using the optimized support configuration, successful circuit probing tests are performed on 8-inch, 10-$upmu $ m-thick self-made dummy wafers and pyroelectric infrared control wafers. No visible cracks are observed on the ultra-thin wafers after the test under a scanning electron microscope. The proposed strategy is expected to pave the way for the large-scale application of ultra-thin and flexible chips.
{"title":"Wafer-Scale Circuit Probing Test for Flexible Ultra-Thin Chips Enabled by Temporary Support","authors":"Yu Song;Xin Song;Tianbo Wang;Wei Jian;Xiyi Liao;Neng Gao;Ying Chen;Xue Feng","doi":"10.1109/TSM.2026.3705495","DOIUrl":"https://doi.org/10.1109/TSM.2026.3705495","url":null,"abstract":"Ultra-thin and flexible chips are essential for high-performance flexible electronic devices, whose large-scale fabrication relies on reliable ultra-thin wafers. Circuit probing test of ultra-thin wafers plays a crucial role in screening functional chips prior to packaging; however, wafer warpage and fragility pose significant challenges to such testing. In this study, the stress distribution in ultra-thin wafers temporarily supported during circuit probing is analyzed based on layered elasticity theory. A wafer failure phase diagram is subsequently established, from which a selection strategy for temporary support materials is proposed to enhance the mechanical resistance of ultra-thin wafers against probing forces. The analysis reveals that higher Young’s modulus and thinner temporary supports enable safer probing. Using the optimized support configuration, successful circuit probing tests are performed on 8-inch, 10-<inline-formula> <tex-math>$upmu $ </tex-math></inline-formula>m-thick self-made dummy wafers and pyroelectric infrared control wafers. No visible cracks are observed on the ultra-thin wafers after the test under a scanning electron microscope. The proposed strategy is expected to pave the way for the large-scale application of ultra-thin and flexible chips.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"464-471"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-06-12DOI: 10.1109/TSM.2026.3702942
Jaein Jeong;Eun a Ko;Youngjeong Kim
An investigation into the origin and control strategies for a distinct defect characterized by radial wafer maps was conducted during the spin-on hard-mask (SOH), photo resist (PR), and spin-on dielectric (SOD) coating processes. It was found that this defect is closely associated with wafer review or critical dimension (CD) measurements using a scanning electron microscope (SEM) instrument prior to the coating process, and appears in the form of micro-bubbles. To elucidate the formation dynamics, surface contamination analysis, contact angle, thermal desorption, and potential measurements were performed. The results indicated a mechanism for bubble generation resulting from locally inhomogeneous wafer surface hydrophobization caused by carbon-compound-based contamination in a vacuum SEM chamber. The hydrophobization leads to bubble nucleation and air entrapment during the acceleration coating stage. As preventive measures, the organic contamination source has been reduced by cleaning the SEM chamber, and it has also been demonstrated that implementing enhanced double reducing resist consumption (RRC) in the photolithography process is an effective solution.
{"title":"Investigation of Radial Micro-Bubble Defects Caused by Organic Contamination","authors":"Jaein Jeong;Eun a Ko;Youngjeong Kim","doi":"10.1109/TSM.2026.3702942","DOIUrl":"https://doi.org/10.1109/TSM.2026.3702942","url":null,"abstract":"An investigation into the origin and control strategies for a distinct defect characterized by radial wafer maps was conducted during the spin-on hard-mask (SOH), photo resist (PR), and spin-on dielectric (SOD) coating processes. It was found that this defect is closely associated with wafer review or critical dimension (CD) measurements using a scanning electron microscope (SEM) instrument prior to the coating process, and appears in the form of micro-bubbles. To elucidate the formation dynamics, surface contamination analysis, contact angle, thermal desorption, and potential measurements were performed. The results indicated a mechanism for bubble generation resulting from locally inhomogeneous wafer surface hydrophobization caused by carbon-compound-based contamination in a vacuum SEM chamber. The hydrophobization leads to bubble nucleation and air entrapment during the acceleration coating stage. As preventive measures, the organic contamination source has been reduced by cleaning the SEM chamber, and it has also been demonstrated that implementing enhanced double reducing resist consumption (RRC) in the photolithography process is an effective solution.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"388-394"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-07-06DOI: 10.1109/TSM.2026.3710173
Kangjian Cheng;Jingyan Huang;Wen Siang Lew
Temperature nonuniformity during rapid thermal processing (RTP) induces localized thermal stress and plastic distortion, leading to lithographic overlay errors and yield degradation. In this work, we report a systematic methodology to detect and mitigate process-induced wafer distortion and residual overlay errors without compromising film thickness uniformity. In-plane distortion (IPD) data are used to quantitatively correlate nonuniform residual wafer shape changes with downstream overlay performance with high accuracy. By optimizing the pyrometer T7 offset, residual overlay is reduced to 24.2% and 20.2% of the original values in the X and Y directions, respectively. While conventional tuning typically compromises wafer edge thickness, the incorporation of a side gas injector enables simultaneous improvement in oxide thickness uniformity from 1.33% to 0.18%. This integrated approach demonstrates a practical method for enhancing RTP control and improving overlay performance in advanced semiconductor manufacturing.
{"title":"Mitigating Process-Induced Wafer Distortion for Enhanced Overlay and Thickness Uniformity","authors":"Kangjian Cheng;Jingyan Huang;Wen Siang Lew","doi":"10.1109/TSM.2026.3710173","DOIUrl":"https://doi.org/10.1109/TSM.2026.3710173","url":null,"abstract":"Temperature nonuniformity during rapid thermal processing (RTP) induces localized thermal stress and plastic distortion, leading to lithographic overlay errors and yield degradation. In this work, we report a systematic methodology to detect and mitigate process-induced wafer distortion and residual overlay errors without compromising film thickness uniformity. In-plane distortion (IPD) data are used to quantitatively correlate nonuniform residual wafer shape changes with downstream overlay performance with high accuracy. By optimizing the pyrometer T7 offset, residual overlay is reduced to 24.2% and 20.2% of the original values in the X and Y directions, respectively. While conventional tuning typically compromises wafer edge thickness, the incorporation of a side gas injector enables simultaneous improvement in oxide thickness uniformity from 1.33% to 0.18%. This integrated approach demonstrates a practical method for enhancing RTP control and improving overlay performance in advanced semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"524-530"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-03-16DOI: 10.1109/TSM.2026.3673999
Mukund Shenoy;Farhad Ameri
Root-cause analysis (RCA) in surface-mount assembly must support rapid containment and verification while remaining auditable under imperfect evidence. We present an uncertainty-aware neurosymbolic pipeline in which a neural evidence layer converts per-board observations into probabilities for defect class, stage-wise mechanism, and parameter risk, and a deterministic semantic layer assembles and ranks defect–mechanism–parameter-violation hypotheses over an explicit causal mapping. The output is an RCA packet: a small ranked hypothesis set with evidence and provenance pointers (observation value, specification bounds, timestamp, and model version). We evaluate on a synthetic multi-shift dataset with correlated variation and graded ground truth, reporting set-level agreement (hit rate, Jaccard similarity, exact match), triage behavior (mean reciprocal rank), and edge-level fidelity with a cycle sanity check.
{"title":"Uncertainty-Aware Neurosymbolic Root-Cause Analysis for Surface-Mount Assembly","authors":"Mukund Shenoy;Farhad Ameri","doi":"10.1109/TSM.2026.3673999","DOIUrl":"https://doi.org/10.1109/TSM.2026.3673999","url":null,"abstract":"Root-cause analysis (RCA) in surface-mount assembly must support rapid containment and verification while remaining auditable under imperfect evidence. We present an uncertainty-aware neurosymbolic pipeline in which a neural evidence layer converts per-board observations into probabilities for defect class, stage-wise mechanism, and parameter risk, and a deterministic semantic layer assembles and ranks defect–mechanism–parameter-violation hypotheses over an explicit causal mapping. The output is an RCA packet: a small ranked hypothesis set with evidence and provenance pointers (observation value, specification bounds, timestamp, and model version). We evaluate on a synthetic multi-shift dataset with correlated variation and graded ground truth, reporting set-level agreement (hit rate, Jaccard similarity, exact match), triage behavior (mean reciprocal rank), and edge-level fidelity with a cycle sanity check.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"402-409"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-03-11DOI: 10.1109/TSM.2026.3691744
Thi Thu Ha Vu;Tan Hung Vo;Jaeyeop Choi;Sudip Mondal;Junghwan Oh
C-scan images in scanning acoustic microscopy (SAM) are crucial for ensuring the reliability and accuracy of semiconductor devices. These images provide detailed cross-sectional views of devices, allowing for precise identification and analysis of internal structures and defects without causing any damage. Recent studies have extensively employed C-scan imaging to enhance quality control processes, significantly improving the overall effectiveness of non-destructive testing (NDT). However, most samples typically possess flat surfaces and are examined under optimal scanning conditions. This article addresses the challenge of uneven or deformed sample surfaces that result in low-quality C-scan images. Specifically, we developed a surface segmentation model utilizing B-scan images from the SAM system and a fine-tuned version of the latest You Only Look Once (YOLO) architecture. Subsequently, the A-scan was recalculated to reconstruct the C-scan image. To evaluate the feasibility of this approach, we posed two research questions: 1) Can the improved YOLOv11-seg network effectively perform surface segmentation? and 2) How is the quality of the C-scan image improved after reconstruction? The results indicate that our enhanced model achieves promising performance in surface segmentation of B-scan images, with a mean Average Precision $mAP_{0.5-0.95}$ of approximately 0.938 for bounding boxes and 0.901 for masks. This study proposes an effective solution for the NDT of semiconductor samples with uneven surfaces that ensures high-quality C-scan images, supports quality control processes, and enhances the overall effectiveness of non-destructive evaluation methodologies.
扫描声学显微镜（SAM）中的c扫描图像对于确保半导体器件的可靠性和准确性至关重要。这些图像提供了设备的详细横截面视图，允许在不造成任何损坏的情况下精确识别和分析内部结构和缺陷。最近的研究广泛使用c扫描成像来加强质量控制过程，显著提高了无损检测（NDT）的整体有效性。然而，大多数样品通常具有平坦的表面，并在最佳扫描条件下进行检查。本文解决了导致低质量c扫描图像的不均匀或变形样品表面的挑战。具体来说，我们开发了一个表面分割模型，利用来自SAM系统的b扫描图像和最新的You Only Look Once （YOLO）架构的微调版本。随后，重新计算a扫描图像，重建c扫描图像。为了评估该方法的可行性，我们提出了两个研究问题：1)改进的YOLOv11-seg网络能否有效地进行表面分割？2)重建后c扫描图像质量如何提高？结果表明，我们的增强模型在b扫描图像的表面分割中取得了很好的效果，边界框的平均平均精度$mAP_{0.5-0.95}$约为0.938，蒙版的平均平均精度$为0.901。本研究为具有不均匀表面的半导体样品的无损检测提出了一种有效的解决方案，该解决方案可确保高质量的c扫描图像，支持质量控制过程，并提高无损评估方法的整体有效性。
{"title":"High-Precision Acoustic Image Reconstruction for Uneven Surfaces Using a YOLO-Based Approach","authors":"Thi Thu Ha Vu;Tan Hung Vo;Jaeyeop Choi;Sudip Mondal;Junghwan Oh","doi":"10.1109/TSM.2026.3691744","DOIUrl":"https://doi.org/10.1109/TSM.2026.3691744","url":null,"abstract":"C-scan images in scanning acoustic microscopy (SAM) are crucial for ensuring the reliability and accuracy of semiconductor devices. These images provide detailed cross-sectional views of devices, allowing for precise identification and analysis of internal structures and defects without causing any damage. Recent studies have extensively employed C-scan imaging to enhance quality control processes, significantly improving the overall effectiveness of non-destructive testing (NDT). However, most samples typically possess flat surfaces and are examined under optimal scanning conditions. This article addresses the challenge of uneven or deformed sample surfaces that result in low-quality C-scan images. Specifically, we developed a surface segmentation model utilizing B-scan images from the SAM system and a fine-tuned version of the latest You Only Look Once (YOLO) architecture. Subsequently, the A-scan was recalculated to reconstruct the C-scan image. To evaluate the feasibility of this approach, we posed two research questions: 1) Can the improved YOLOv11-seg network effectively perform surface segmentation? and 2) How is the quality of the C-scan image improved after reconstruction? The results indicate that our enhanced model achieves promising performance in surface segmentation of B-scan images, with a mean Average Precision <inline-formula> <tex-math>$mAP_{0.5-0.95}$ </tex-math></inline-formula> of approximately 0.938 for bounding boxes and 0.901 for masks. This study proposes an effective solution for the NDT of semiconductor samples with uneven surfaces that ensures high-quality C-scan images, supports quality control processes, and enhances the overall effectiveness of non-destructive evaluation methodologies.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"441-452"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-08-07DOI: 10.1109/TSM.2026.3708019
Jeanne Paulette Bickford;Ralf Buengener;Delphine Le Cunff;Reshmi Mitra;Stefan Radloff
{"title":"Guest Editorial Special Section on the 2025 SEMI Advanced Semiconductor Manufacturing Conference","authors":"Jeanne Paulette Bickford;Ralf Buengener;Delphine Le Cunff;Reshmi Mitra;Stefan Radloff","doi":"10.1109/TSM.2026.3708019","DOIUrl":"https://doi.org/10.1109/TSM.2026.3708019","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"378-380"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11644736","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-08-01Epub Date: 2026-07-01DOI: 10.1109/TSM.2026.3709162
Sam Bertelson;Roberto Dailey;Jinki Kim;Dragan Djurdjanovic
Accuracy of Virtual Metrology (VM) models, selection of wafers for physical metrology, and VM model adaptation are all vital areas of semiconductor manufacturing research which share a complex interdependence between each other. These interdependencies dictate the need for a unified framework which addresses VM modeling, uncertainty-aware selection of wafers for physical metrology, and adaptations of that model based on the newly obtained physical metrology results. In this paper, we propose a linear Gaussian dynamic model-based framework which models and tracks the behavior of VM model parameters over time, quantifies the uncertainty of VM model parameters and the VM model itself, and provides a theoretical framework for optimization of the selection of wafers which need to be physically inspected. We demonstrate the efficacy and superiority of this integrated VM modeling and upkeeping framework over the existing heuristic solutions using a uniquely large dataset obtained from an industrial plasma etch process performed on 114,774 wafers in a major 300 mm wafer semiconductor fab.
{"title":"Uncertainty Aware Virtual Metrology (VM) Framework Enabling Optimized Physical Metrology Policy and VM Model Adaptations","authors":"Sam Bertelson;Roberto Dailey;Jinki Kim;Dragan Djurdjanovic","doi":"10.1109/TSM.2026.3709162","DOIUrl":"https://doi.org/10.1109/TSM.2026.3709162","url":null,"abstract":"Accuracy of Virtual Metrology (VM) models, selection of wafers for physical metrology, and VM model adaptation are all vital areas of semiconductor manufacturing research which share a complex interdependence between each other. These interdependencies dictate the need for a unified framework which addresses VM modeling, uncertainty-aware selection of wafers for physical metrology, and adaptations of that model based on the newly obtained physical metrology results. In this paper, we propose a linear Gaussian dynamic model-based framework which models and tracks the behavior of VM model parameters over time, quantifies the uncertainty of VM model parameters and the VM model itself, and provides a theoretical framework for optimization of the selection of wafers which need to be physically inspected. We demonstrate the efficacy and superiority of this integrated VM modeling and upkeeping framework over the existing heuristic solutions using a uniquely large dataset obtained from an industrial plasma etch process performed on 114,774 wafers in a major 300 mm wafer semiconductor fab.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"565-571"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the mitigation of dopant deactivation in heavily phosphorus-doped silicon via phosphorus-nitrogen co-implantation. Dopant-vacancy complexes formed during sequential thermal processes are responsible for a reduction in carrier concentration, thereby narrowing the thermal process window. Nitrogen preferentially binds vacancies relative to phosphorus. Therefore, co-implantation suppresses the formation of phosphorus-vacancy complexes. Hall measurements show reduced deactivation in co-implanted samples. FTIR identifies features consistent with N2V2 formation at higher annealing temperatures. Raman spectroscopy shows reduced intensity of the 520 cm−1 c-Si peak in co-implanted samples, consistent with a degraded crystallinity and reduced mobility. SIMS shows broader phosphorus profiles after the second anneal, with slightly greater broadening in co-implanted samples, and a mid-depth nitrogen signal drop attributable to matrix effects on ion yield. TEM images show additional near-surface dark-contrast features in the co-implanted samples, qualitatively consistent with residual defects or local strain fields. These results indicate that nitrogen co-implantation mitigates deactivation under practical thermal budgets, albeit introducing a trade-off in carrier transport due to impurity/defect scattering.
{"title":"Mitigation of Dopant Deactivation in Heavily Phosphorus-Doped Silicon via Nitrogen Co-Implantation","authors":"Chang-Shan Shen;Wei-Chi Aeneas Hsu;Ming-Chun Hsu;Tsun-Hsu Chang","doi":"10.1109/TSM.2026.3707590","DOIUrl":"https://doi.org/10.1109/TSM.2026.3707590","url":null,"abstract":"This paper investigates the mitigation of dopant deactivation in heavily phosphorus-doped silicon via phosphorus-nitrogen co-implantation. Dopant-vacancy complexes formed during sequential thermal processes are responsible for a reduction in carrier concentration, thereby narrowing the thermal process window. Nitrogen preferentially binds vacancies relative to phosphorus. Therefore, co-implantation suppresses the formation of phosphorus-vacancy complexes. Hall measurements show reduced deactivation in co-implanted samples. FTIR identifies features consistent with N2V2 formation at higher annealing temperatures. Raman spectroscopy shows reduced intensity of the 520 cm−1 c-Si peak in co-implanted samples, consistent with a degraded crystallinity and reduced mobility. SIMS shows broader phosphorus profiles after the second anneal, with slightly greater broadening in co-implanted samples, and a mid-depth nitrogen signal drop attributable to matrix effects on ion yield. TEM images show additional near-surface dark-contrast features in the co-implanted samples, qualitatively consistent with residual defects or local strain fields. These results indicate that nitrogen co-implantation mitigates deactivation under practical thermal budgets, albeit introducing a trade-off in carrier transport due to impurity/defect scattering.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"515-523"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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