Pub Date : 2026-02-06DOI: 10.1109/TSM.2025.3648625
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2025.3648625","DOIUrl":"https://doi.org/10.1109/TSM.2025.3648625","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11373124","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-Electro-Mechanical System (MEMS) devices show better performance as compared to solid-state devices in terms of radio frequency (RF) response, like insertion loss and isolation. However, MEMS devices face reliability issues, and stress is one of the main concerns. MEMS devices involve many non-traditional fabrication steps, like releasing hanging structures. Released MEMS structures show built-in stress from the fabrication process. This stress can cause them to bend, curl, or buckle. Especially in the case of Radio Frequency (RF) MEMS switches, curling buckling increases the pull-in voltage. In the literature, to address stress-related buckling, thermal annealing was applied at different temperatures after release. However, post-release annealing reduces the stress and results in curled-up and unstable structures. The present paper explores a novel and innovative method for thermally annealing structures at an appropriate stage to reduce stress and buckling in released cantilever structures. Annealing at the appropriate step results in a significant reduction in cantilever bending and warping, indicating effective stress relaxation and yielding straight, mechanically stable cantilevers. After controlling the stress and buckling, the pull-in voltage is reduced to 40 V, which is in close agreement with the simulated results. The measured insertion loss of the switch is –0.4 dB, and isolation is –22 dB for the DC to 20 GHz frequency range.
{"title":"Buckling and Stress-Controlled RF MEMS Structures Using Annealing","authors":"Khushbu Singh Raghav;Amit Kumar;Prashant Sharma;Prateek Kothari;Mahesh Angira;Deepak Bansal","doi":"10.1109/TSM.2025.3646670","DOIUrl":"https://doi.org/10.1109/TSM.2025.3646670","url":null,"abstract":"Micro-Electro-Mechanical System (MEMS) devices show better performance as compared to solid-state devices in terms of radio frequency (RF) response, like insertion loss and isolation. However, MEMS devices face reliability issues, and stress is one of the main concerns. MEMS devices involve many non-traditional fabrication steps, like releasing hanging structures. Released MEMS structures show built-in stress from the fabrication process. This stress can cause them to bend, curl, or buckle. Especially in the case of Radio Frequency (RF) MEMS switches, curling buckling increases the pull-in voltage. In the literature, to address stress-related buckling, thermal annealing was applied at different temperatures after release. However, post-release annealing reduces the stress and results in curled-up and unstable structures. The present paper explores a novel and innovative method for thermally annealing structures at an appropriate stage to reduce stress and buckling in released cantilever structures. Annealing at the appropriate step results in a significant reduction in cantilever bending and warping, indicating effective stress relaxation and yielding straight, mechanically stable cantilevers. After controlling the stress and buckling, the pull-in voltage is reduced to 40 V, which is in close agreement with the simulated results. The measured insertion loss of the switch is –0.4 dB, and isolation is –22 dB for the DC to 20 GHz frequency range.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"28-35"},"PeriodicalIF":2.3,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/TSM.2025.3646674
Jae Hwan Shin;Hyunbeen Kim;Jin Hwan Park;Young-Woo Lee
As chiplet technologies such as 2.5D/3D rapidly advance, chiplet testing approaches are becoming increasingly challenging. Specifically, stacking multiple chips or high bandwidth memory (HBM) in a single package increases the I/O pin count, leading to longer test times and multi-site test performance degradation due to increased test complexity and resource constraints. In turn, this results in higher testing costs as additional time and equipment are required to maintain test efficiency. In this paper, we propose a novel test interface integrating digital and analog compression modules to achieve high parallelism and precise fault detection. The proposed architecture incorporates a device under test (DUT) off masking sequence and a fault detection scheme, which enhances production efficiency while optimizing limited test resources by reusing analog test instruments that were not previously used in digital functional testing. This approach reduces overall test resource requirements and supports cost-effective parallel testing without additional equipment. Experimental results include an analysis of the architecture’s operational reliability under process variations and demonstrate a reduction in test resources and an average 82.2% decrease in test data volume on the ISCAS’89 and OpenCores benchmarks compared to prior work.
{"title":"Scalable Multi-Site Test Architecture for Chiplet-Based Systems on ATE Platforms","authors":"Jae Hwan Shin;Hyunbeen Kim;Jin Hwan Park;Young-Woo Lee","doi":"10.1109/TSM.2025.3646674","DOIUrl":"https://doi.org/10.1109/TSM.2025.3646674","url":null,"abstract":"As chiplet technologies such as 2.5D/3D rapidly advance, chiplet testing approaches are becoming increasingly challenging. Specifically, stacking multiple chips or high bandwidth memory (HBM) in a single package increases the I/O pin count, leading to longer test times and multi-site test performance degradation due to increased test complexity and resource constraints. In turn, this results in higher testing costs as additional time and equipment are required to maintain test efficiency. In this paper, we propose a novel test interface integrating digital and analog compression modules to achieve high parallelism and precise fault detection. The proposed architecture incorporates a device under test (DUT) off masking sequence and a fault detection scheme, which enhances production efficiency while optimizing limited test resources by reusing analog test instruments that were not previously used in digital functional testing. This approach reduces overall test resource requirements and supports cost-effective parallel testing without additional equipment. Experimental results include an analysis of the architecture’s operational reliability under process variations and demonstrate a reduction in test resources and an average 82.2% decrease in test data volume on the ISCAS’89 and OpenCores benchmarks compared to prior work.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"139-147"},"PeriodicalIF":2.3,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-19DOI: 10.1109/TSM.2025.3646324
Shih-Cheng Hu;Tee Lin;Omid Ali Zargar;Chen-Lin Cho;Yang-Cheng Shih;Graham Leggett
Studies have shown that when the door of a Front Opening Unified Pod (FOUP) opens, the moisture or airborne molecular contamination (AMC) in the microenvironment can be influenced by the equipment layout, forming a skewed flow field. This skewed flow field can allow contaminants to enter the FOUP, adversely affecting the yield of the semiconductor manufacturing process. To effectively eliminate contaminants inside the FOUP, in addition to the common method of purging the FOUP, a laminar air curtain (LAC) device can be added to the FOUP door. This device introduces compressed dry air (CDA) at the interface between the microenvironment and the FOUP, forming flow barrier. This method effectively controls the cleanliness and humidity inside the FOUP. Currently, with the use of the laminar air curtain device, the humidity inside the FOUP significantly decreases. However, when the air reaches the bottom of the wafer box, it tends to diffuse outward, allowing contaminants to invade. To enhance the barrier effect of the air curtain, increasing the flow rate of the injected air is considered, but this can cause deformation of the perforated plate. Since the laminar air curtain device is installed near the door of the Load-Port Unit (LPU), the deformed perforated plate might collide with the LPU door, causing structural damage, generating particles, or displacing the laminar air curtain device, thus compromising its ability to effectively block contaminants from entering the FOUP. The previously developed filter-type laminar air curtain device has met the high flow rate (700 L/min) requirements and improved issues related to deformation and particle generation caused by high flow rates. However, comparative testing of performance across multiple samples in mass production is lacking. Therefore, this study will optimize the configuration of the filter-type laminar air curtain device, including the use of a perforated plate at the outlet and an airflow diffusion device inside the structure. After mass production, we will conduct performance comparisons, including indicators such as airflow uniformity and particle concentration. We expect that advancements in this research and technology will promote broader application of the filter-type air curtain device in the semiconductor industry.
{"title":"Performance of Filter-Type Laminar Air Curtains When the FOUP Door Opened","authors":"Shih-Cheng Hu;Tee Lin;Omid Ali Zargar;Chen-Lin Cho;Yang-Cheng Shih;Graham Leggett","doi":"10.1109/TSM.2025.3646324","DOIUrl":"https://doi.org/10.1109/TSM.2025.3646324","url":null,"abstract":"Studies have shown that when the door of a Front Opening Unified Pod (FOUP) opens, the moisture or airborne molecular contamination (AMC) in the microenvironment can be influenced by the equipment layout, forming a skewed flow field. This skewed flow field can allow contaminants to enter the FOUP, adversely affecting the yield of the semiconductor manufacturing process. To effectively eliminate contaminants inside the FOUP, in addition to the common method of purging the FOUP, a laminar air curtain (LAC) device can be added to the FOUP door. This device introduces compressed dry air (CDA) at the interface between the microenvironment and the FOUP, forming flow barrier. This method effectively controls the cleanliness and humidity inside the FOUP. Currently, with the use of the laminar air curtain device, the humidity inside the FOUP significantly decreases. However, when the air reaches the bottom of the wafer box, it tends to diffuse outward, allowing contaminants to invade. To enhance the barrier effect of the air curtain, increasing the flow rate of the injected air is considered, but this can cause deformation of the perforated plate. Since the laminar air curtain device is installed near the door of the Load-Port Unit (LPU), the deformed perforated plate might collide with the LPU door, causing structural damage, generating particles, or displacing the laminar air curtain device, thus compromising its ability to effectively block contaminants from entering the FOUP. The previously developed filter-type laminar air curtain device has met the high flow rate (700 L/min) requirements and improved issues related to deformation and particle generation caused by high flow rates. However, comparative testing of performance across multiple samples in mass production is lacking. Therefore, this study will optimize the configuration of the filter-type laminar air curtain device, including the use of a perforated plate at the outlet and an airflow diffusion device inside the structure. After mass production, we will conduct performance comparisons, including indicators such as airflow uniformity and particle concentration. We expect that advancements in this research and technology will promote broader application of the filter-type air curtain device in the semiconductor industry.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"82-90"},"PeriodicalIF":2.3,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-15DOI: 10.1109/TSM.2025.3643948
Zimeng Wang;Jaehyun Kim;Sanghee Han;Alp Akçay;Heeyeop Chae;Juseong Lee
Accurate endpoint detection is critical in semiconductor plasma etching. Optical emission spectroscopy data contains information about the endpoint, but its analysis requires significant domain knowledge, and it contains large noise when the open area ratio is small. This paper proposes an interpretable data-driven endpoint detection method for small open area etching, leveraging transfer learning. First, we propose a formal metric quantifying the significance of endpoint trend in each wavelength signal and select the wavelength signals that are most sensitive to endpoint variations. Second, we devise an asymmetric autoencoder to uncover the endpoint trend in the noisy signals. Its asymmetric architecture incorporates nonlinear characteristics while ensuring the latent feature reflects the endpoint trends of the individual signals. Experimental results show that the model that learned the large open area etching (11.1%) can detect the endpoints of the small open area etching (0.5%) with the relative mean absolute error less than 0.6%, and amplify the signal-to-noise ratio by a factor of 2-3. Furthermore, the analysis of the selected wavelengths provides deeper insights into the underlying physical processes. The proposed method can be applied with minimal domain knowledge, while its results allow for exploring physical interpretations.
{"title":"Data-Driven Endpoint Detection for Small Open Area Etching Using Interpretable Transfer Learning","authors":"Zimeng Wang;Jaehyun Kim;Sanghee Han;Alp Akçay;Heeyeop Chae;Juseong Lee","doi":"10.1109/TSM.2025.3643948","DOIUrl":"https://doi.org/10.1109/TSM.2025.3643948","url":null,"abstract":"Accurate endpoint detection is critical in semiconductor plasma etching. Optical emission spectroscopy data contains information about the endpoint, but its analysis requires significant domain knowledge, and it contains large noise when the open area ratio is small. This paper proposes an interpretable data-driven endpoint detection method for small open area etching, leveraging transfer learning. First, we propose a formal metric quantifying the significance of endpoint trend in each wavelength signal and select the wavelength signals that are most sensitive to endpoint variations. Second, we devise an asymmetric autoencoder to uncover the endpoint trend in the noisy signals. Its asymmetric architecture incorporates nonlinear characteristics while ensuring the latent feature reflects the endpoint trends of the individual signals. Experimental results show that the model that learned the large open area etching (11.1%) can detect the endpoints of the small open area etching (0.5%) with the relative mean absolute error less than 0.6%, and amplify the signal-to-noise ratio by a factor of 2-3. Furthermore, the analysis of the selected wavelengths provides deeper insights into the underlying physical processes. The proposed method can be applied with minimal domain knowledge, while its results allow for exploring physical interpretations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"74-81"},"PeriodicalIF":2.3,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work reports the successful integration and processing of hundreds of GaN on Silicon wafer lots devoted to 100V Monolithic GaN power device within a standard 8-inch silicon fab primarily dedicated to BCD/CMOS technology production. By addressing key challenges related to gallium cross-contamination and equipment compatibility with thicker GaN on Si substrates, a comprehensive contamination management strategy was developed and implemented. This strategy includes dedicated equipment classification, backside wafer protection, optimized cleaning procedures for GaN etching tools, and rigorous monitoring using TXRF measurements. The approach enabled reliable, high-mechanical yield of GaN wafer device fabrication without impacting existing BCD/CMOS production lines, demonstrating the feasibility of coexisting GaN and silicon technologies in a shared manufacturing environment. This achievement paves the way for cost-effective scaling of GaN power device production within mainstream semiconductor fabs.
{"title":"Feasibility Demonstration of GaN on Si Process for R&D and Manufacturing on Existing 200mm Si-Fab","authors":"Luisito Livellara;Michele Molgg;Guido Pietrogrande;Selene Colombo;Daria Doria;Ivana Patoprsta;Costanza Adamo;Alessia Azzopardo;Paolo Colpani","doi":"10.1109/TSM.2025.3642930","DOIUrl":"https://doi.org/10.1109/TSM.2025.3642930","url":null,"abstract":"This work reports the successful integration and processing of hundreds of GaN on Silicon wafer lots devoted to 100V Monolithic GaN power device within a standard 8-inch silicon fab primarily dedicated to BCD/CMOS technology production. By addressing key challenges related to gallium cross-contamination and equipment compatibility with thicker GaN on Si substrates, a comprehensive contamination management strategy was developed and implemented. This strategy includes dedicated equipment classification, backside wafer protection, optimized cleaning procedures for GaN etching tools, and rigorous monitoring using TXRF measurements. The approach enabled reliable, high-mechanical yield of GaN wafer device fabrication without impacting existing BCD/CMOS production lines, demonstrating the feasibility of coexisting GaN and silicon technologies in a shared manufacturing environment. This achievement paves the way for cost-effective scaling of GaN power device production within mainstream semiconductor fabs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"148-155"},"PeriodicalIF":2.3,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-10DOI: 10.1109/TSM.2025.3642343
Linyu Wei;Jueping Cai
The defect of the lighting-emitting diode (LED) chip is inevitable in the manufacturing process, which makes it necessary to classify the defective LED-chips with a robust inspection system to guarantee high production efficiency. Recently, convolutional neural networks (CNN) have attracted considerable attention in defect classification. With the miniaturization of chip size, it is difficult to recognize the defective chip using the traditional deep CNN, which obtains the large receptive field of the last layer so that the spatial details are ignored and small defects cannot be detected. To address this issue, we propose a multi-scale content-aware enhancement dual-branch CNN for LED-chip defect classification, which is a shallow network with a strong cross-layer feature extraction ability. Aiming at recognizing different sizes of the defect and filtering the noise, a multi-scale content-aware enhancement module is proposed to highlight the important features and inhibit the noise with three different receptive fields, which is beneficial for the detailed and semantic information extraction. Furthermore, a joint loss is adopted to improve the classification ability and facilitate the recognition of difficult samples. Experiments show that the proposed model achieves high recognition accuracy of 95.258% with a low model complexity, which is superior to state-of-the-art methods.
{"title":"Multi-Scale Content-Aware Enhancement Dual-Branch CNN for LED-Chip Defect Classification","authors":"Linyu Wei;Jueping Cai","doi":"10.1109/TSM.2025.3642343","DOIUrl":"https://doi.org/10.1109/TSM.2025.3642343","url":null,"abstract":"The defect of the lighting-emitting diode (LED) chip is inevitable in the manufacturing process, which makes it necessary to classify the defective LED-chips with a robust inspection system to guarantee high production efficiency. Recently, convolutional neural networks (CNN) have attracted considerable attention in defect classification. With the miniaturization of chip size, it is difficult to recognize the defective chip using the traditional deep CNN, which obtains the large receptive field of the last layer so that the spatial details are ignored and small defects cannot be detected. To address this issue, we propose a multi-scale content-aware enhancement dual-branch CNN for LED-chip defect classification, which is a shallow network with a strong cross-layer feature extraction ability. Aiming at recognizing different sizes of the defect and filtering the noise, a multi-scale content-aware enhancement module is proposed to highlight the important features and inhibit the noise with three different receptive fields, which is beneficial for the detailed and semantic information extraction. Furthermore, a joint loss is adopted to improve the classification ability and facilitate the recognition of difficult samples. Experiments show that the proposed model achieves high recognition accuracy of 95.258% with a low model complexity, which is superior to state-of-the-art methods.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"62-73"},"PeriodicalIF":2.3,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/TSM.2025.3636948
Shih-Cheng Hu;Tee Lin;Omid Ali Zargar;Yi-Chang Lin;Yang-Cheng Shih;Graham Leggett
With rapid advancements in technology, Taiwan has become a global leader in semiconductor manufacturing. Over the past decade, process technologies have continually advanced, reaching the latest 1.2 nm node. However, as feature sizes shrink, the complexity of processes increases, leading to more stringent requirements for the stability of the manufacturing environment. Cleanroom environments have become increasingly critical in semiconductor manufacturing, significantly impacting production capacity and yield. In the equipment front-end module (EFEM), we observed that when the front opening unified pod (FOUP) door is opened, internal pressure differentials can cause air ingress into the microenvironment. This ingested air may carry moisture and oxygen, which, upon entering the FOUP, can damage the wafers, leading to decreased yield. In real-world scenarios, we found that despite the use of laminar air curtain devices, wafer box yields remained unstable due to the influence of inclined airflow. To simulate this situation, our experiment utilized flow field visualization to observe the effects of different air curtain flow rates (0.3 m/s,0.4 m/s and 0.5 m/s) and environmental wind speeds (0.3 m/s and 0.5 m/s) on inclined airflows (7°, 15°, and 30°) when the FOUP door is opened. While flow field visualization provided clear images of airflow directions, it could not determine whether the ingested air contained contaminants harmful to the wafers. Therefore, we supplemented our experiment with relative humidity monitoring data to identify whether the ingested air originated from the external environment or the air curtain device itself, providing effective recommendations based on the findings.
{"title":"Analyzing the Impact of Inclined Airflow Within the EFEM on the Lateral Flow Around the FOUP Using Flow Visualization Techniques","authors":"Shih-Cheng Hu;Tee Lin;Omid Ali Zargar;Yi-Chang Lin;Yang-Cheng Shih;Graham Leggett","doi":"10.1109/TSM.2025.3636948","DOIUrl":"https://doi.org/10.1109/TSM.2025.3636948","url":null,"abstract":"With rapid advancements in technology, Taiwan has become a global leader in semiconductor manufacturing. Over the past decade, process technologies have continually advanced, reaching the latest 1.2 nm node. However, as feature sizes shrink, the complexity of processes increases, leading to more stringent requirements for the stability of the manufacturing environment. Cleanroom environments have become increasingly critical in semiconductor manufacturing, significantly impacting production capacity and yield. In the equipment front-end module (EFEM), we observed that when the front opening unified pod (FOUP) door is opened, internal pressure differentials can cause air ingress into the microenvironment. This ingested air may carry moisture and oxygen, which, upon entering the FOUP, can damage the wafers, leading to decreased yield. In real-world scenarios, we found that despite the use of laminar air curtain devices, wafer box yields remained unstable due to the influence of inclined airflow. To simulate this situation, our experiment utilized flow field visualization to observe the effects of different air curtain flow rates (0.3 m/s,0.4 m/s and 0.5 m/s) and environmental wind speeds (0.3 m/s and 0.5 m/s) on inclined airflows (7°, 15°, and 30°) when the FOUP door is opened. While flow field visualization provided clear images of airflow directions, it could not determine whether the ingested air contained contaminants harmful to the wafers. Therefore, we supplemented our experiment with relative humidity monitoring data to identify whether the ingested air originated from the external environment or the air curtain device itself, providing effective recommendations based on the findings.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"53-61"},"PeriodicalIF":2.3,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/TSM.2025.3633070
Dongkyum Kim;Jiwon Seo;Jun-Ho Choi;Munam Kim;Bumsuk Jung;Sang Jeen Hong;Jeongsoon Lee
The widespread use of fluorinated gases in semiconductor manufacturing has raised significant environmental concerns due to their high global warming potential (GWP). To address this issue, we developed a systematic methodology for screening and evaluating low-GWP F-gases based on density functional theory (DFT) calculations. The infrared absorption cross-section (ACS) spectra and radiative efficiencies (RE) of candidate gases were predicted and systematically corrected using an empirical scaling factor derived from the correlation between calculated and experimentally measured RE values. This correction significantly improved the accuracy of GWP predictions. The methodology was successfully validated against representative F-gases, yielding GWP1oo estimates that closely align with reported values for high-GWP gases (GWP1oo=2,240), mid-GWP gases (GWP1oo=87), and low-GWP gases (below GWP1oo=10). Notably, several candidate gases, such as COF2, CF3OCFCF2, CF3C(O)CF(CF3)2, and C6F6, exhibited estimated GWP1oo values of 1.79, 2.69, 3.03, and 7.56, respectively, which are consistent with reported values. They were re-confirmed by the proposed method as promising low-GWP alternatives to conventional high-GWP etching and cleaning gases. By adopting a practical, accessible DFT methodology, this approach delivers reliable comparisons of GWP values among candidate gases and supports rapid, on-site GWP assessments without requiring specialized expertise.
{"title":"A Computational Method for Screening Low-GWP Fluorinated Gases in Semiconductor Manufacturing","authors":"Dongkyum Kim;Jiwon Seo;Jun-Ho Choi;Munam Kim;Bumsuk Jung;Sang Jeen Hong;Jeongsoon Lee","doi":"10.1109/TSM.2025.3633070","DOIUrl":"https://doi.org/10.1109/TSM.2025.3633070","url":null,"abstract":"The widespread use of fluorinated gases in semiconductor manufacturing has raised significant environmental concerns due to their high global warming potential (GWP). To address this issue, we developed a systematic methodology for screening and evaluating low-GWP F-gases based on density functional theory (DFT) calculations. The infrared absorption cross-section (ACS) spectra and radiative efficiencies (RE) of candidate gases were predicted and systematically corrected using an empirical scaling factor derived from the correlation between calculated and experimentally measured RE values. This correction significantly improved the accuracy of GWP predictions. The methodology was successfully validated against representative F-gases, yielding GWP1oo estimates that closely align with reported values for high-GWP gases (GWP1oo=2,240), mid-GWP gases (GWP1oo=87), and low-GWP gases (below GWP1oo=10). Notably, several candidate gases, such as COF2, CF3OCFCF2, CF3C(O)CF(CF3)2, and C6F6, exhibited estimated GWP1oo values of 1.79, 2.69, 3.03, and 7.56, respectively, which are consistent with reported values. They were re-confirmed by the proposed method as promising low-GWP alternatives to conventional high-GWP etching and cleaning gases. By adopting a practical, accessible DFT methodology, this approach delivers reliable comparisons of GWP values among candidate gases and supports rapid, on-site GWP assessments without requiring specialized expertise.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"156-164"},"PeriodicalIF":2.3,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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