Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367028
F. Baiardi, L. Ricci
One of the key obstacles to the widespread adoption of massively parallel computers is the lack of programming environments to support the development of software that can achieve both portability and high performance. The paper discusses alternative methodologies to define static and dynamic tools of this environment. While the main problems posed by a static tool are input dependant behaviour and the definition of a formal and abstract representation of the user program, dynamic tools introduce overhead to collect data about the program behaviour to drive their policy. Proper integration between the two kinds of tools is fundamental to be able to select the most appropriate solution for a given program. The definition and the design of these tools can be largely simplified through the introduction of a virtual machine to be mapped onto different physical machines and that enables the development of software tools and applications that can be ported across different machines.<>
{"title":"General purpose massively parallel systems: the role of programming environments","authors":"F. Baiardi, L. Ricci","doi":"10.1109/MPCS.1994.367028","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367028","url":null,"abstract":"One of the key obstacles to the widespread adoption of massively parallel computers is the lack of programming environments to support the development of software that can achieve both portability and high performance. The paper discusses alternative methodologies to define static and dynamic tools of this environment. While the main problems posed by a static tool are input dependant behaviour and the definition of a formal and abstract representation of the user program, dynamic tools introduce overhead to collect data about the program behaviour to drive their policy. Proper integration between the two kinds of tools is fundamental to be able to select the most appropriate solution for a given program. The definition and the design of these tools can be largely simplified through the introduction of a virtual machine to be mapped onto different physical machines and that enables the development of software tools and applications that can be ported across different machines.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"63 1","pages":"584-598"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86074397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367046
J. Schwemmlein, R. Posch, K. C. Posch
This paper presents a distributed computing architecture capable of performing long integer arithmetic. Special attention is given to module multiplication. To avoid carry propagation delays, the design makes use of RNS arithmetic. In RNS, additions and multiplications can be computed in parallel. Several VLSI processing elements are grouped together, each holding one RNS digit. These devices exchange information on a data bus. Instructions sequenced by an additional chip control synchronized execution. Thus, the system can be seen as a SIMD architecture performing modular arithmetic. Some instructions differ from a pure SIMD concept. The system is tuned for special purpose computations. As a sample application suitable for the presented chip set, an RSA like enciphering method (MRSA) is shown.<>
{"title":"High performance modular arithmetic using an RNS based chipset","authors":"J. Schwemmlein, R. Posch, K. C. Posch","doi":"10.1109/MPCS.1994.367046","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367046","url":null,"abstract":"This paper presents a distributed computing architecture capable of performing long integer arithmetic. Special attention is given to module multiplication. To avoid carry propagation delays, the design makes use of RNS arithmetic. In RNS, additions and multiplications can be computed in parallel. Several VLSI processing elements are grouped together, each holding one RNS digit. These devices exchange information on a data bus. Instructions sequenced by an additional chip control synchronized execution. Thus, the system can be seen as a SIMD architecture performing modular arithmetic. Some instructions differ from a pure SIMD concept. The system is tuned for special purpose computations. As a sample application suitable for the presented chip set, an RSA like enciphering method (MRSA) is shown.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"31 1","pages":"444-451"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72990799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367086
G. Németh
The management of the various cooperation modes and timing requirements in the case of a large number of tasks poses interesting theoretical problems in massively parallel environments. These systems are in general fully distributed ones, preventing coherent observability. Moreover, their configurations may change dynamically because of failures and/or modifications. Thus no optimal algorithms can be constructed for the effective utilization of the resources available. The influence of the granularity level, cooperation modes and timing requirements are scrutinized in order to identify areas for further research. It is shown that the resource allocation procedure should be partitioned into distinct phases both in time and space.<>
{"title":"Routing, scheduling, timing and intractability","authors":"G. Németh","doi":"10.1109/MPCS.1994.367086","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367086","url":null,"abstract":"The management of the various cooperation modes and timing requirements in the case of a large number of tasks poses interesting theoretical problems in massively parallel environments. These systems are in general fully distributed ones, preventing coherent observability. Moreover, their configurations may change dynamically because of failures and/or modifications. Thus no optimal algorithms can be constructed for the effective utilization of the resources available. The influence of the granularity level, cooperation modes and timing requirements are scrutinized in order to identify areas for further research. It is shown that the resource allocation procedure should be partitioned into distinct phases both in time and space.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"67 1","pages":"114-124"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77830532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367089
A. Elleuch, T. Muntean
Process migration is known as the run time relocation of a process within a network of processors. This capability is mainly used for efficient management of resources in a distributed system. This paper deals with the construction of process migration mechanisms for Massively Parallel Systems (MPS). In particular, we are interested in the correction of communications in presence of migration. Many distributed systems have proposed mechanisms for process migration where different approaches are used to ensure transparency and correctness of the delivery of messages. In MPS, more than achieving correctness and transparency, the emphasis is put also on supporting scalability of the machine architecture, and on efficiency by minimising the overhead introduced by the use of the migration mechanisms at run-time. According to these criteria we propose three migration protocols for correct message passing mechanisms.<>
{"title":"Process migration protocols for massively parallel systems","authors":"A. Elleuch, T. Muntean","doi":"10.1109/MPCS.1994.367089","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367089","url":null,"abstract":"Process migration is known as the run time relocation of a process within a network of processors. This capability is mainly used for efficient management of resources in a distributed system. This paper deals with the construction of process migration mechanisms for Massively Parallel Systems (MPS). In particular, we are interested in the correction of communications in presence of migration. Many distributed systems have proposed mechanisms for process migration where different approaches are used to ensure transparency and correctness of the delivery of messages. In MPS, more than achieving correctness and transparency, the emphasis is put also on supporting scalability of the machine architecture, and on efficiency by minimising the overhead introduced by the use of the migration mechanisms at run-time. According to these criteria we propose three migration protocols for correct message passing mechanisms.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"38 1","pages":"84-95"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78023876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367071
R. Posch
In most cases performance of parallel machines is proven with special applications that enable for adequate granularity, and thus are able to show the performance. Looking at common machine types, the involved techniques do not solve the problem of fast communication among processing elements. In fact, nearly any of these types is capable of really fine grain granularity. In most real applications this is not a big problem. But in a few cases this becomes critical. The presented approach shows how to cope with fast communication among processing elements. This is done through the use of massive parallelism on a single chip, or on a set of chips. In this case optimum communication speed can be assumed and thus fast processing within a very small area becomes the design goal. This design goal is met in the special case with dynamic logic enabling for a large number of very small processing elements.<>
{"title":"Massive parallelism on a chip-VLSI aspects involving dynamic logic","authors":"R. Posch","doi":"10.1109/MPCS.1994.367071","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367071","url":null,"abstract":"In most cases performance of parallel machines is proven with special applications that enable for adequate granularity, and thus are able to show the performance. Looking at common machine types, the involved techniques do not solve the problem of fast communication among processing elements. In fact, nearly any of these types is capable of really fine grain granularity. In most real applications this is not a big problem. But in a few cases this becomes critical. The presented approach shows how to cope with fast communication among processing elements. This is done through the use of massive parallelism on a single chip, or on a set of chips. In this case optimum communication speed can be assumed and thus fast processing within a very small area becomes the design goal. This design goal is met in the special case with dynamic logic enabling for a large number of very small processing elements.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"182 1","pages":"230-237"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80318762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367072
E. Apolloni, F. Arcieri, E. Nardelli, M. Talamo
In this paper we report about our experiences in research projects dealing with the use of parallel system technology for the management of land information. From these experiences we have derived a characterization in terms of user requirements, system requirements and system architecture. The basic feature of a system dealing with planning and decision making problems in the context of land management is the possibility to support incremental constraint definition and modeling activities. In this way it is possible to decide which actions have to be done in an "on-line" way, i.e. interactively and on the basis of dynamically changing data. We point out which functionalities have be set at the system level, and which ones can be set at the application level. According to the present user profile, we also introduce a target architecture for an on-line decision support system that is based on the view building mechanism.<>
{"title":"Experiences in using parallel systems for land information management","authors":"E. Apolloni, F. Arcieri, E. Nardelli, M. Talamo","doi":"10.1109/MPCS.1994.367072","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367072","url":null,"abstract":"In this paper we report about our experiences in research projects dealing with the use of parallel system technology for the management of land information. From these experiences we have derived a characterization in terms of user requirements, system requirements and system architecture. The basic feature of a system dealing with planning and decision making problems in the context of land management is the possibility to support incremental constraint definition and modeling activities. In this way it is possible to decide which actions have to be done in an \"on-line\" way, i.e. interactively and on the basis of dynamically changing data. We point out which functionalities have be set at the system level, and which ones can be set at the application level. According to the present user profile, we also introduce a target architecture for an on-line decision support system that is based on the view building mechanism.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"82 1","pages":"223-228"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87179080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367047
R. Albrecht
The goal of this article is to present a general theoretical framework for modelling the logical and physical structures underlying computer architectures. The reasoning is based on general system theory and the mathematical theory of constructive computation. Fundamental are discrete functional systems, their partitions, and algorithms on them. For modelling processes in general "time sets" are introduced and the mutual dependences of processes are discussed. In correspondence to the mathematical objects considered, a model of physical computational systems is given. From this a whole range of architectural concepts can be derived.<>
{"title":"Modelling of computer architectures","authors":"R. Albrecht","doi":"10.1109/MPCS.1994.367047","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367047","url":null,"abstract":"The goal of this article is to present a general theoretical framework for modelling the logical and physical structures underlying computer architectures. The reasoning is based on general system theory and the mathematical theory of constructive computation. Fundamental are discrete functional systems, their partitions, and algorithms on them. For modelling processes in general \"time sets\" are introduced and the mutual dependences of processes are discussed. In correspondence to the mathematical objects considered, a model of physical computational systems is given. From this a whole range of architectural concepts can be derived.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"32 1","pages":"434-442"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91300049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367039
S. Srinivas
This paper presents the results of a research project undertaken to study the parallelization and vectorization of various important scientific codes on the Alliant FX/2800 supercomputer system. A selection of scientific codes from benchmark suites such LINPACK, LAPACK, BLAS, NAPACK, EISPACK, and FFTPACK was made and these codes were parallelized and vectorized using the four optimization modes on the Alliant, namely, global optimization, vectorization, concurrentization (parallelization), and vector-concurrentization. The optimization results are summarized by means of performance measures called optimization ratios, which basically indicate the degree of vectorization and parallelization that can be applied to each code. Driver routines were used to obtain runtime results in the different modes. Another important component of this project is do study the effect of caching the data on the performance of the programs. The results from this study can be used to select a routine that can be optimized well and also to select the appropriate optimization method so that the overall performance of the program can be improved.<>
{"title":"A study of the parallelization and vectorization of scientific codes on the Alliant FX/2800","authors":"S. Srinivas","doi":"10.1109/MPCS.1994.367039","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367039","url":null,"abstract":"This paper presents the results of a research project undertaken to study the parallelization and vectorization of various important scientific codes on the Alliant FX/2800 supercomputer system. A selection of scientific codes from benchmark suites such LINPACK, LAPACK, BLAS, NAPACK, EISPACK, and FFTPACK was made and these codes were parallelized and vectorized using the four optimization modes on the Alliant, namely, global optimization, vectorization, concurrentization (parallelization), and vector-concurrentization. The optimization results are summarized by means of performance measures called optimization ratios, which basically indicate the degree of vectorization and parallelization that can be applied to each code. Driver routines were used to obtain runtime results in the different modes. Another important component of this project is do study the effect of caching the data on the performance of the programs. The results from this study can be used to select a routine that can be optimized well and also to select the appropriate optimization method so that the overall performance of the program can be improved.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"23 1","pages":"514-517"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85390674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367053
M. Fiallos-Aguilar
In this paper we deal with new high precision arithmetic units (AUs). These AUs are specialized in the computation of one arithmetic operation (division, addition, etc.), but when hundreds of them are interconnected by a reconfigurable network, a parallel architecture that uses massive digit-level pipelining between floating-point arithmetic units (allowing fast computation of scientific jobs) becomes interesting. In this paper we present several new AUs for the fast computation of arithmetic expressions that will be used on a high precision massively parallel computer.<>
{"title":"High precision arithmetic units for fine-grain massively parallel computing","authors":"M. Fiallos-Aguilar","doi":"10.1109/MPCS.1994.367053","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367053","url":null,"abstract":"In this paper we deal with new high precision arithmetic units (AUs). These AUs are specialized in the computation of one arithmetic operation (division, addition, etc.), but when hundreds of them are interconnected by a reconfigurable network, a parallel architecture that uses massive digit-level pipelining between floating-point arithmetic units (allowing fast computation of scientific jobs) becomes interesting. In this paper we present several new AUs for the fast computation of arithmetic expressions that will be used on a high precision massively parallel computer.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"43 1","pages":"403-407"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83327783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367044
Enrico Nardelli, Carmine D'Amico, Coppito
We give a first formulation of a model for evaluating performances of a message passing architecture parallel machine in the context of spatial data processing. We consider 2-dimensional data of the type 'region' and analyze operations of union and intersection between them. On the basis of the characteristics of manipulation algorithms and of the architecture we individuate as the best way of implementing them, we propose and validate through experiments a model able to estimate time required to execute union or intersection operations between two regions of arbitrary shape as a function of a small number of parameters describing input data. Though derived on a specific machine, the model obtained is of general validity, since only the values of numerical constants are dependant by the machine used. Such a model is the first necessary step in tackling the issue of query optimization for spatial data in a parallel environment. The work is a part of a more general research programme aiming at studying the best approach to take advantage from parallel architectures for spatial data processing.<>
{"title":"A model for performance evaluation of message passing architectures in spatial data processing","authors":"Enrico Nardelli, Carmine D'Amico, Coppito","doi":"10.1109/MPCS.1994.367044","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367044","url":null,"abstract":"We give a first formulation of a model for evaluating performances of a message passing architecture parallel machine in the context of spatial data processing. We consider 2-dimensional data of the type 'region' and analyze operations of union and intersection between them. On the basis of the characteristics of manipulation algorithms and of the architecture we individuate as the best way of implementing them, we propose and validate through experiments a model able to estimate time required to execute union or intersection operations between two regions of arbitrary shape as a function of a small number of parameters describing input data. Though derived on a specific machine, the model obtained is of general validity, since only the values of numerical constants are dependant by the machine used. Such a model is the first necessary step in tackling the issue of query optimization for spatial data in a parallel environment. The work is a part of a more general research programme aiming at studying the best approach to take advantage from parallel architectures for spatial data processing.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"100 1","pages":"460-470"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76796325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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