Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367070
B. Zavidovique
Understanding what the problems are in robot-vision architecture, requires a better comparison of major features. But a zoology of vision machines is questioned when, aiming for a well informed architectural feature choice, a rapid presentation of technological trends in the field is proposed. Then an approach closer to physics prompts to a classification from a control point of view: it reveals some duality between operations and communications. A few visual operations are distinguished provided technology is not trailing behind. But emphasis should be put on communication networks, although they do not show any image processing specificity currently, and the conclusion addresses some limits in that respect.<>
{"title":"Technology against vision architectures","authors":"B. Zavidovique","doi":"10.1109/MPCS.1994.367070","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367070","url":null,"abstract":"Understanding what the problems are in robot-vision architecture, requires a better comparison of major features. But a zoology of vision machines is questioned when, aiming for a well informed architectural feature choice, a rapid presentation of technological trends in the field is proposed. Then an approach closer to physics prompts to a classification from a control point of view: it reveals some duality between operations and communications. A few visual operations are distinguished provided technology is not trailing behind. But emphasis should be put on communication networks, although they do not show any image processing specificity currently, and the conclusion addresses some limits in that respect.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"13 1","pages":"239-257"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87834812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367054
L. Verdoscia, R. Vaccaro
This paper presents a static dataflow graph model, where only data tokens are allowed to flow. The proposed model is formally described, and the dataflow graph is obtained by employing only actors with homogeneous I/O conditions. Each actor, which executes an elemental operation, is characterized by having one output and two input arcs. Even though no control tokens are allowed, so that no T-gate, merge, and switch actors are present in this model, it is always possible to represent conditional and iterative structures whose behavior is well-behaved. As homogeneous I/O conditions are a severe restriction to represent the flow of a computation and the token flow in such dataflow graphs is completely asynchronous, proof is given to guarantee their determinacy.<>
{"title":"Conditional and iterative structures using a homogeneous static dataflow graph model","authors":"L. Verdoscia, R. Vaccaro","doi":"10.1109/MPCS.1994.367054","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367054","url":null,"abstract":"This paper presents a static dataflow graph model, where only data tokens are allowed to flow. The proposed model is formally described, and the dataflow graph is obtained by employing only actors with homogeneous I/O conditions. Each actor, which executes an elemental operation, is characterized by having one output and two input arcs. Even though no control tokens are allowed, so that no T-gate, merge, and switch actors are present in this model, it is always possible to represent conditional and iterative structures whose behavior is well-behaved. As homogeneous I/O conditions are a severe restriction to represent the flow of a computation and the token flow in such dataflow graphs is completely asynchronous, proof is given to guarantee their determinacy.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"34 1","pages":"391-401"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90200339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367040
A. De Gloria, P. Faraboschi
This paper deals with the design of parallel architectures dedicated to specific applications and mainly focuses on the relationships between software and hardware tradeoffs, putting the emphasis on parallel architecture for non-numeric applications. The analysis covers both medium and massive parallelism. Medium level parallelism is seen through the analysis of VLIW architectures where code-generation takes an important role for achieving high performance. In particular we show the main design steps of a parallel architecture for Prolog. High level parallelism in non-numeric applications is introduced through the presentation of a dedicated architecture for the solution of NP-complete problems with the Boltzmann Machine model. Also in this case, we present the problems related to the design of the architecture and the interaction between hardware and software components.<>
{"title":"Application specific parallel architectures","authors":"A. De Gloria, P. Faraboschi","doi":"10.1109/MPCS.1994.367040","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367040","url":null,"abstract":"This paper deals with the design of parallel architectures dedicated to specific applications and mainly focuses on the relationships between software and hardware tradeoffs, putting the emphasis on parallel architecture for non-numeric applications. The analysis covers both medium and massive parallelism. Medium level parallelism is seen through the analysis of VLIW architectures where code-generation takes an important role for achieving high performance. In particular we show the main design steps of a parallel architecture for Prolog. High level parallelism in non-numeric applications is introduced through the presentation of a dedicated architecture for the solution of NP-complete problems with the Boltzmann Machine model. Also in this case, we present the problems related to the design of the architecture and the interaction between hardware and software components.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"29 1","pages":"497-512"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81071297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367032
S. Srinivas, N. Biswas
The paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exist two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear lime complexity, and provides a large reduction in run-time as compared to an existing algorithm. This is well confirmed from the experimental results obtained by executing a large number of randomly generated data exchange tables. Another significant feature of the algorithm is that the bit size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.<>
{"title":"A fast algorithm for data exchange in reconfigurable tree structures","authors":"S. Srinivas, N. Biswas","doi":"10.1109/MPCS.1994.367032","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367032","url":null,"abstract":"The paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exist two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear lime complexity, and provides a large reduction in run-time as compared to an existing algorithm. This is well confirmed from the experimental results obtained by executing a large number of randomly generated data exchange tables. Another significant feature of the algorithm is that the bit size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"16 1","pages":"554-563"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79852233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367038
M. Giordano, M. Furnari, A. Massarotti
In this paper we describe the design criteria for a Parallel Symbolic Language for Vision Analysis. The essential feature of a such language is the use of the notion of structured parallelism in order to capture all the forms of parallelism used in vision analysis. After introducing the need for Symbolic Parallel languages for the vision analysis, we show how PARALATION LISP can be extended to manage it in a user transparent way. Then, we describe the design criteria used for our Parallel Symbolic Vision Analysis Language project and the current implementation status.<>
{"title":"A parallel symbolic language for vision analysis","authors":"M. Giordano, M. Furnari, A. Massarotti","doi":"10.1109/MPCS.1994.367038","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367038","url":null,"abstract":"In this paper we describe the design criteria for a Parallel Symbolic Language for Vision Analysis. The essential feature of a such language is the use of the notion of structured parallelism in order to capture all the forms of parallelism used in vision analysis. After introducing the need for Symbolic Parallel languages for the vision analysis, we show how PARALATION LISP can be extended to manage it in a user transparent way. Then, we describe the design criteria used for our Parallel Symbolic Vision Analysis Language project and the current implementation status.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"262 1","pages":"518-522"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79668946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367090
A.M. Sjostrom
Computing is often viewed as a tool and a computing system is typically treated as a toolbox of applications for performing operations such as calculations and data storage and transfer. Currently, humans develop these application tools and apply, or specify how to apply, them. Recognizing that computing is a fundamental discipline challenges us to accept the notion that a computing system could play other roles than merely serving as a toolbox. An active player will require massive parallelism and mechanisms for abstracting over interactions.<>
{"title":"Communication in distributed computing environments","authors":"A.M. Sjostrom","doi":"10.1109/MPCS.1994.367090","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367090","url":null,"abstract":"Computing is often viewed as a tool and a computing system is typically treated as a toolbox of applications for performing operations such as calculations and data storage and transfer. Currently, humans develop these application tools and apply, or specify how to apply, them. Recognizing that computing is a fundamental discipline challenges us to accept the notion that a computing system could play other roles than merely serving as a toolbox. An active player will require massive parallelism and mechanisms for abstracting over interactions.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"33 4 1","pages":"78-83"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89938811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367059
S. Dandamudi
In distributed task ready queue organizations, task routing refers to how ready tasks are assigned to processors in the system and task scheduling refers to how these tasks are scheduled on the assigned processor. In this paper, we consider the interaction between task routing and task scheduling strategies and their impact on the performance of the distributed task queue organization. We consider four task routing strategies two adaptive and two non-adaptive-and five task scheduling policies-two preemptive and three run-to-completion policies. We show that, when adaptive task routing is employed, the scheduling policy has only a marginal impact on performance and preemptive round robin policies tend to perform worse than the FCFS policy.<>
{"title":"Performance implications of task routing and task scheduling strategies for multiprocessor systems","authors":"S. Dandamudi","doi":"10.1109/MPCS.1994.367059","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367059","url":null,"abstract":"In distributed task ready queue organizations, task routing refers to how ready tasks are assigned to processors in the system and task scheduling refers to how these tasks are scheduled on the assigned processor. In this paper, we consider the interaction between task routing and task scheduling strategies and their impact on the performance of the distributed task queue organization. We consider four task routing strategies two adaptive and two non-adaptive-and five task scheduling policies-two preemptive and three run-to-completion policies. We show that, when adaptive task routing is employed, the scheduling policy has only a marginal impact on performance and preemptive round robin policies tend to perform worse than the FCFS policy.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"51 1","pages":"348-353"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72713066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367088
B. Park
Linear size expanders have been studied in many fields for their practical use, which is the possibility to connect large numbers of device chips in parallel communication systems. One of the critical points in parallel computer designs has been very high cost of communication between processors and memories. Currently, linear size expanders can be used to construct theoretically optimal interconnection networks with reducing large constant factors. This paper presents an improvement on constructing concentrators using an (n, k, 2rs)/(r/sup 2/-s/sup 2/) expander, which realizes the reduction of the size in a superconcentrator by a constant factor.<>
{"title":"Improved bounds on linear size expander","authors":"B. Park","doi":"10.1109/MPCS.1994.367088","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367088","url":null,"abstract":"Linear size expanders have been studied in many fields for their practical use, which is the possibility to connect large numbers of device chips in parallel communication systems. One of the critical points in parallel computer designs has been very high cost of communication between processors and memories. Currently, linear size expanders can be used to construct theoretically optimal interconnection networks with reducing large constant factors. This paper presents an improvement on constructing concentrators using an (n, k, 2rs)/(r/sup 2/-s/sup 2/) expander, which realizes the reduction of the size in a superconcentrator by a constant factor.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"40 1","pages":"96-101"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78310798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367043
V. Varshavsky, T. Chu
After describing the main idea of self-timing, the authors consider the advantages and costs of the application of self-timing. They discuss the synchronisation of processes in self-timed systems.<>
在介绍了自定时的主要思想后，作者考虑了应用自定时的优点和成本。他们讨论自定时系统中过程的同步性。
{"title":"SELF-TIMING-tools for hardware support of parallel, concurrent and event-driven process control","authors":"V. Varshavsky, T. Chu","doi":"10.1109/MPCS.1994.367043","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367043","url":null,"abstract":"After describing the main idea of self-timing, the authors consider the advantages and costs of the application of self-timing. They discuss the synchronisation of processes in self-timed systems.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"329 1","pages":"472-476"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75323390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-02DOI: 10.1109/MPCS.1994.367023
M. Valerio, L. Moser, P. Melliar-Smith
We propose a novel method of scheduling memory access on a non blocking interconnection network that provides only one-to-one communication. Conflicts at the switches can be avoided if the accesses are scheduled so that no two processors attempt to access the same memory at the same time. We show how such a scheduling problem can be mapped to an edge coloring problem for a directed graph and present algorithms for solving that problem. We give examples of the application of the algorithm and present simulation results.<>
{"title":"Avoiding memory contention on tightly coupled multiprocessors","authors":"M. Valerio, L. Moser, P. Melliar-Smith","doi":"10.1109/MPCS.1994.367023","DOIUrl":"https://doi.org/10.1109/MPCS.1994.367023","url":null,"abstract":"We propose a novel method of scheduling memory access on a non blocking interconnection network that provides only one-to-one communication. Conflicts at the switches can be avoided if the accesses are scheduled so that no two processors attempt to access the same memory at the same time. We show how such a scheduling problem can be mapped to an edge coloring problem for a directed graph and present algorithms for solving that problem. We give examples of the application of the algorithm and present simulation results.<<ETX>>","PeriodicalId":64175,"journal":{"name":"专用汽车","volume":"216 1","pages":"643-654"},"PeriodicalIF":0.0,"publicationDate":"1994-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75606070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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