Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704541
C. Jian, M. Jusheng, W. Gang-Qiang, T. Xiangyun
The influences of several factors on the etching rates of Cu in FeCl/sub 3/ etchant are studied with a spray etching apparatus in this paper. The Cu etching surfaces are analyzed by XRD, and it is shown that there is a CuCl passivation film on the etching surface. A brief explanation is offered based on the relationship between etching rate and etching time. It indicates that cations influence the etching rate as the effects of different chlorides on etching rates have been studied. Additionally, the quantity of copper dissolved in FeCl/sub 3/ etchant and regeneration of spent etchants are also investigated in this paper.
{"title":"Effects on etching rates of copper in ferric chloride solutions","authors":"C. Jian, M. Jusheng, W. Gang-Qiang, T. Xiangyun","doi":"10.1109/IEMTIM.1998.704541","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704541","url":null,"abstract":"The influences of several factors on the etching rates of Cu in FeCl/sub 3/ etchant are studied with a spray etching apparatus in this paper. The Cu etching surfaces are analyzed by XRD, and it is shown that there is a CuCl passivation film on the etching surface. A brief explanation is offered based on the relationship between etching rate and etching time. It indicates that cations influence the etching rate as the effects of different chlorides on etching rates have been studied. Additionally, the quantity of copper dissolved in FeCl/sub 3/ etchant and regeneration of spent etchants are also investigated in this paper.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117169820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704517
M. Wada
As an encapsulant for flip chip packages, underfill materials play an important role for the purpose of protection from thermal stress and environmental stress. We have developed an excellent reliability underfill material based on the following concepts: (1) cured underfill material coefficient of thermal expansion (CTE) which is close to that of the solder ball; (2) excellent adhesion to plastic circuit board; (3) little change in material properties after moisture uptake. The material can be cured for 60 min, has JEDEC level 3 reliability and passes 1000 cycle temperature cycling tests. In order to shorten the cure schedule of this material, we have studied the following: (a) an additive agent with hydrophobic structure; (b) a catalyst. Based on these studies, we have developed a shorter cure (30 min.) type underfill.
{"title":"Development of high reliability underfill material","authors":"M. Wada","doi":"10.1109/IEMTIM.1998.704517","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704517","url":null,"abstract":"As an encapsulant for flip chip packages, underfill materials play an important role for the purpose of protection from thermal stress and environmental stress. We have developed an excellent reliability underfill material based on the following concepts: (1) cured underfill material coefficient of thermal expansion (CTE) which is close to that of the solder ball; (2) excellent adhesion to plastic circuit board; (3) little change in material properties after moisture uptake. The material can be cured for 60 min, has JEDEC level 3 reliability and passes 1000 cycle temperature cycling tests. In order to shorten the cure schedule of this material, we have studied the following: (a) an additive agent with hydrophobic structure; (b) a catalyst. Based on these studies, we have developed a shorter cure (30 min.) type underfill.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127262176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704538
M. Usui, M. Hikita, R. Yoshimura, N. Matsuura, N. Sato, A. Ohki, T. Kagawa, K. Tateno, K. Katsura, Y. Ando
ParaBIT (parallel inter-board optical interconnection technology) is promising for high-throughput interconnections in advanced switching and computer systems. We have developed a new optical coupling technique for ParaBIT modules using polymeric optical waveguide films. This technique provides good optical coupling in ParaBIT modules, and is also very useful for multi-channel optical coupling. In this paper, we describe the design, structure, and characteristics of this optical coupling technique.
{"title":"An optical coupling technique for parallel optical interconnection modules using polymeric optical waveguide films","authors":"M. Usui, M. Hikita, R. Yoshimura, N. Matsuura, N. Sato, A. Ohki, T. Kagawa, K. Tateno, K. Katsura, Y. Ando","doi":"10.1109/IEMTIM.1998.704538","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704538","url":null,"abstract":"ParaBIT (parallel inter-board optical interconnection technology) is promising for high-throughput interconnections in advanced switching and computer systems. We have developed a new optical coupling technique for ParaBIT modules using polymeric optical waveguide films. This technique provides good optical coupling in ParaBIT modules, and is also very useful for multi-channel optical coupling. In this paper, we describe the design, structure, and characteristics of this optical coupling technique.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124840667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704632
N. Yamanaka, A. Harada, K. Kaizu, T. Kawamura
This paper describes a newly developed MCM-D microprocessor module for advanced ATM switching systems. The Si-substrate MCM-D technology, which integrates a Motorola 68030 microprocessor, interface control, and peripheral control custom VLSIs, high-speed SRAMs and FPGAs (field programmable gate arrays), is employed. This is made possible by high density packaging with the stacked high-speed RAM technique, and reduces module size by 7/8 compared to conventional surface mounting schemes. In addition, a uniquely structured thermal management technique is employed. MCM heat flows to the printed motherboard power supply layer through via holes. Using this technique, module volume can be dramatically reduced. This microprocessor module technology and MCM technology has been developed to advance the development of practical B-ISDN ATM switching systems.
{"title":"An MCM-D module using newly structured thermal management technique","authors":"N. Yamanaka, A. Harada, K. Kaizu, T. Kawamura","doi":"10.1109/IEMTIM.1998.704632","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704632","url":null,"abstract":"This paper describes a newly developed MCM-D microprocessor module for advanced ATM switching systems. The Si-substrate MCM-D technology, which integrates a Motorola 68030 microprocessor, interface control, and peripheral control custom VLSIs, high-speed SRAMs and FPGAs (field programmable gate arrays), is employed. This is made possible by high density packaging with the stacked high-speed RAM technique, and reduces module size by 7/8 compared to conventional surface mounting schemes. In addition, a uniquely structured thermal management technique is employed. MCM heat flows to the printed motherboard power supply layer through via holes. Using this technique, module volume can be dramatically reduced. This microprocessor module technology and MCM technology has been developed to advance the development of practical B-ISDN ATM switching systems.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115993942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704671
K. Nakakuki, Y. Takahashi, Y. Iguchi, K. Anasako, H. Shimamura
We developed a heat dissipation structure for face-down bonded surface acoustic wave (SAW) filter packages. This structure enables compact packages at low cost. Heat dissipation from the transmission (Tx) SAW filter and filter sealing are important factors in enhancing package reliability. Tx and reception (Rx) SAW filters were bonded on a printed wiring board (PWB) with a branching circuit, and the filters were sealed with a metallic lid using conductive adhesive. High thermal conductivity adhesive was used to fill between the Tx SAW filter and the metallic lid, enabling the heat of the Tx SAW filter to be dissipated. The filter properties of the package using this high thermal conductivity adhesive were not changed after 500 hour operation with 5 W input RF signals. Results following the performance of thermal shock tests also confirmed characteristics indicating an extremely tight seal, with a rate of helium leakage of only 10/sup -8/ atm/spl middot/cc/s. Thus, as indicated in detail by these results, we concluded that the structure which we developed has been proven to be suitable for application to SAW filter packages.
{"title":"Development of heat dissipation structure for face-down bonded devices","authors":"K. Nakakuki, Y. Takahashi, Y. Iguchi, K. Anasako, H. Shimamura","doi":"10.1109/IEMTIM.1998.704671","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704671","url":null,"abstract":"We developed a heat dissipation structure for face-down bonded surface acoustic wave (SAW) filter packages. This structure enables compact packages at low cost. Heat dissipation from the transmission (Tx) SAW filter and filter sealing are important factors in enhancing package reliability. Tx and reception (Rx) SAW filters were bonded on a printed wiring board (PWB) with a branching circuit, and the filters were sealed with a metallic lid using conductive adhesive. High thermal conductivity adhesive was used to fill between the Tx SAW filter and the metallic lid, enabling the heat of the Tx SAW filter to be dissipated. The filter properties of the package using this high thermal conductivity adhesive were not changed after 500 hour operation with 5 W input RF signals. Results following the performance of thermal shock tests also confirmed characteristics indicating an extremely tight seal, with a rate of helium leakage of only 10/sup -8/ atm/spl middot/cc/s. Thus, as indicated in detail by these results, we concluded that the structure which we developed has been proven to be suitable for application to SAW filter packages.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116589605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704516
S.R. Wathne, K. Wathne
Reflow technology has undergone some major changes in recent times. This is largely due to the requirements in the industry to improve process control. Three major factors contribute to achieve this: temperature, time and atmosphere. Not only must each segment be controlled, but it must all be done simultaneously, as each interacts with the other. It is no longer tolerable for one of the ingredients to be held to specifications while the other is not. Current furnaces are therefore drastically different from the common convection furnace designed for the SMT circuit industry. They must be compact and must be environmentally friendly, i.e. use less electricity, and less nitrogen or forming gas. For the processing of plastic BGAs, for example, a cycle rate of 10 seconds or less must be achieved and this should be accomplished in single file. The furnace must be less than 5 feet long. This paper discusses how to achieve these aims.
{"title":"Thermal dynamics and BGA ball reflow","authors":"S.R. Wathne, K. Wathne","doi":"10.1109/IEMTIM.1998.704516","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704516","url":null,"abstract":"Reflow technology has undergone some major changes in recent times. This is largely due to the requirements in the industry to improve process control. Three major factors contribute to achieve this: temperature, time and atmosphere. Not only must each segment be controlled, but it must all be done simultaneously, as each interacts with the other. It is no longer tolerable for one of the ingredients to be held to specifications while the other is not. Current furnaces are therefore drastically different from the common convection furnace designed for the SMT circuit industry. They must be compact and must be environmentally friendly, i.e. use less electricity, and less nitrogen or forming gas. For the processing of plastic BGAs, for example, a cycle rate of 10 seconds or less must be achieved and this should be accomplished in single file. The furnace must be less than 5 feet long. This paper discusses how to achieve these aims.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124615272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704506
Y. Matsuda, T. Takai, Y. Okada, P. Lall, C. Koehler, T. Tessier, D. Olsen
The just about chip size package (JACS-Pak) design was developed for portable product applications. The package elements are solder bumped die, an epoxy underfill resin with inorganic filler, a low cost double-sided, semi-rigid epoxy glass or flex substrate, and solder ball terminals. This paper focuses on the board level reliability of the JACS-Pak package and benchmarks it with respect to standard ball grid array (BGA) packages, such as the glob top-BGA (GT-BGA) and the over molded pad array carrier (OMPAC). The samples (packages solder reflow attached to PCBs) are subjected to the liquid-to-liquid thermal shock testing from -55 to 125/spl deg/C at a rate of 5.8 cycles per hour. The results are compared to the thermal fatigue performance of standard 196 I/O GT-BGA and the 1.5 mm pitch OMPAC package. In addition, temperature cycling, temperature-humidity bias (THB), high temperature storage life (HTSL), and autoclave reliability tests were performed on the JACS-Pak package with excellent results.
{"title":"Reliability study of the laminate-based flip-chip chip scale package","authors":"Y. Matsuda, T. Takai, Y. Okada, P. Lall, C. Koehler, T. Tessier, D. Olsen","doi":"10.1109/IEMTIM.1998.704506","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704506","url":null,"abstract":"The just about chip size package (JACS-Pak) design was developed for portable product applications. The package elements are solder bumped die, an epoxy underfill resin with inorganic filler, a low cost double-sided, semi-rigid epoxy glass or flex substrate, and solder ball terminals. This paper focuses on the board level reliability of the JACS-Pak package and benchmarks it with respect to standard ball grid array (BGA) packages, such as the glob top-BGA (GT-BGA) and the over molded pad array carrier (OMPAC). The samples (packages solder reflow attached to PCBs) are subjected to the liquid-to-liquid thermal shock testing from -55 to 125/spl deg/C at a rate of 5.8 cycles per hour. The results are compared to the thermal fatigue performance of standard 196 I/O GT-BGA and the 1.5 mm pitch OMPAC package. In addition, temperature cycling, temperature-humidity bias (THB), high temperature storage life (HTSL), and autoclave reliability tests were performed on the JACS-Pak package with excellent results.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114632131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704536
G. Nakagawa, T. Yamamoto, S. Sasaki, N. Yamamoto, K. Tanaka, M. Norimatsu, M. Kobayashi, K. Miura, M. Yano
We report a planar integration scheme for a corner-illuminated photodiode (PD) on a planar lightwave circuit (PLC) platform for highly uniform optical coupling for receiver-PDs and monitor-PDs. We adjusted the marker on the PD to the waveguide on the PLC and the marker on the platform, and deviations from the center position are small, to within /spl plusmn/10 /spl mu/m. The corner-illuminated PD has large lateral tolerance of 65 /spl mu/m for the receiver-PD and 160 /spl mu/m for the monitor-PD. These result in high monitor current uniformity. High average coupling efficiency was obtained for the receiver-PD, with a loss of 0.7/spl plusmn/0.3 dB. As for the monitor-PD, uniform currents of 312/spl plusmn/45 /spl mu/A (/spl plusmn/0.7 dB in optical power) at -2 dBm optical power was obtained. The deviation of optical coupling between the LD and monitor-PD is estimated to be almost 0 dB, judging from deviation of the optical coupling between the LD and the PLC waveguide which is evaluated to be /spl plusmn/0.7 dB. We have confirmed that the corner-illuminated PD and its alignment method are promising for highly uniform characteristics with a surface mounting configuration.
{"title":"Simple assembly scheme of a corner-illuminated PD on a hybridly integrated planar lightwave circuit (PLC) platform","authors":"G. Nakagawa, T. Yamamoto, S. Sasaki, N. Yamamoto, K. Tanaka, M. Norimatsu, M. Kobayashi, K. Miura, M. Yano","doi":"10.1109/IEMTIM.1998.704536","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704536","url":null,"abstract":"We report a planar integration scheme for a corner-illuminated photodiode (PD) on a planar lightwave circuit (PLC) platform for highly uniform optical coupling for receiver-PDs and monitor-PDs. We adjusted the marker on the PD to the waveguide on the PLC and the marker on the platform, and deviations from the center position are small, to within /spl plusmn/10 /spl mu/m. The corner-illuminated PD has large lateral tolerance of 65 /spl mu/m for the receiver-PD and 160 /spl mu/m for the monitor-PD. These result in high monitor current uniformity. High average coupling efficiency was obtained for the receiver-PD, with a loss of 0.7/spl plusmn/0.3 dB. As for the monitor-PD, uniform currents of 312/spl plusmn/45 /spl mu/A (/spl plusmn/0.7 dB in optical power) at -2 dBm optical power was obtained. The deviation of optical coupling between the LD and monitor-PD is estimated to be almost 0 dB, judging from deviation of the optical coupling between the LD and the PLC waveguide which is evaluated to be /spl plusmn/0.7 dB. We have confirmed that the corner-illuminated PD and its alignment method are promising for highly uniform characteristics with a surface mounting configuration.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130242033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704514
J. Shibata, M. Horita, N. Izumi, T. Shikano, M. Okada, Y. Noguchi, K. Imamura, H. Fukunaga, M. Yasunaga, T. Hirai, T. Hashimoto, Y. Takemoto
A fine pitch ball grid array (FBGA) has been developed which is suitable mainly for logic devices such as micro control units (MCU) and application specific integrated circuits (ASIC) for consumer portable electronic instruments. The FBGA has a construction in which a die is attached to a glass-epoxy interposer with a single layer conductor. Wire bonding and transfer molding are applied in the same manner as lead frame type packages. The FBGA has a smaller body and higher performance than conventional packages. The package structure, assembly process, performance and reliability test results are introduced.
{"title":"Development of fine pitch ball grid array","authors":"J. Shibata, M. Horita, N. Izumi, T. Shikano, M. Okada, Y. Noguchi, K. Imamura, H. Fukunaga, M. Yasunaga, T. Hirai, T. Hashimoto, Y. Takemoto","doi":"10.1109/IEMTIM.1998.704514","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704514","url":null,"abstract":"A fine pitch ball grid array (FBGA) has been developed which is suitable mainly for logic devices such as micro control units (MCU) and application specific integrated circuits (ASIC) for consumer portable electronic instruments. The FBGA has a construction in which a die is attached to a glass-epoxy interposer with a single layer conductor. Wire bonding and transfer molding are applied in the same manner as lead frame type packages. The FBGA has a smaller body and higher performance than conventional packages. The package structure, assembly process, performance and reliability test results are introduced.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115390602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704634
Y. Kyouogku, Y. Yamaguti, K. Ohkubo
In order to meet the demand for higher density and greater capacity, a three dimensional memory module has been developed. NEC has developed a new type of 3D memory module which uses single memory module stacking technology. It satisfies the demands for higher packaging density using a simple structure. The reliability of the single memory modules and 3D memory module was tested using 16 Mb DRAM chips. The results suggest that our 3D memory modules have good reliability. With our dual in-line memory modules (DIMM), no breaks in the solder bonds between single memory modules and motherboard were observed over 3000 cycles of thermal cycling testing.
{"title":"3-dimensional memory module assembly technology","authors":"Y. Kyouogku, Y. Yamaguti, K. Ohkubo","doi":"10.1109/IEMTIM.1998.704634","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704634","url":null,"abstract":"In order to meet the demand for higher density and greater capacity, a three dimensional memory module has been developed. NEC has developed a new type of 3D memory module which uses single memory module stacking technology. It satisfies the demands for higher packaging density using a simple structure. The reliability of the single memory modules and 3D memory module was tested using 16 Mb DRAM chips. The results suggest that our 3D memory modules have good reliability. With our dual in-line memory modules (DIMM), no breaks in the solder bonds between single memory modules and motherboard were observed over 3000 cycles of thermal cycling testing.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123584029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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