Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704668
K. Hirano, S. Nakatani, H. Handa, H. Takehara
Recently, it has become more important to take the thermal dispersion of circuit boards into account. We have developed a new composite substrate with high thermal conductivity (HTC-CS) which is suitable for power modules. The main points of development of the substrate are: (1) newly developed composite materials with high thermal conductivity; (2) use of the lead frame (L/F) as a conductive layer; (3) use of thermally conductive sheets (TCSs) and realization of a simple procedure. Alumina and epoxy resin were mixed to make a slurry and were made into sheets by the doctor blade method. The sheet (TCS) was flexible while the resin was not hardened. The TCS was laid on the L/F and heated under pressure. The TCS moved into the gaps in the L/F patterns and the surface became flat; simultaneously, the resin in the TCS hardened to produce a rigid substrate. The substrate thermal conductivity was above 5 W/mK. The substrate was applied to intelligent power modules (IPM). These IPMs showed good reliability. In addition, it is simple to insert a shield layer in the substrate using the TCS procedure, and the substrate has high noise stability.
{"title":"A new composite substrate with high thermal conductivity for power modules","authors":"K. Hirano, S. Nakatani, H. Handa, H. Takehara","doi":"10.1109/IEMTIM.1998.704668","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704668","url":null,"abstract":"Recently, it has become more important to take the thermal dispersion of circuit boards into account. We have developed a new composite substrate with high thermal conductivity (HTC-CS) which is suitable for power modules. The main points of development of the substrate are: (1) newly developed composite materials with high thermal conductivity; (2) use of the lead frame (L/F) as a conductive layer; (3) use of thermally conductive sheets (TCSs) and realization of a simple procedure. Alumina and epoxy resin were mixed to make a slurry and were made into sheets by the doctor blade method. The sheet (TCS) was flexible while the resin was not hardened. The TCS was laid on the L/F and heated under pressure. The TCS moved into the gaps in the L/F patterns and the surface became flat; simultaneously, the resin in the TCS hardened to produce a rigid substrate. The substrate thermal conductivity was above 5 W/mK. The substrate was applied to intelligent power modules (IPM). These IPMs showed good reliability. In addition, it is simple to insert a shield layer in the substrate using the TCS procedure, and the substrate has high noise stability.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124076289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704631
K. Amami, S. Yuhaku, T. Shiraishi, Y. Bessho, K. Eda, T. Ishida
We have developed an advanced MCM (multichip module) using the SBB/sup TM/ (stud-bump bonding) flip-chip technique on an ALIVH/sup TM/ (any layer inner via hole) structure substrate. The SBB technique is an advanced flip-chip bonding technique for high density MCM, which can mount bare LSI chips directly on substrates. The bonding portion structure is composed of Au bumps with two-stepped construction and conductive adhesives. The conductive adhesive is very flexible in bond, thus relaxing thermal and mechanical stresses. The ALIVH substrate is a high density and high performance multilayered printed wiring board with any layer inner via hole structure, CO/sub 2/ laser via hole processing technology and interconnection technology which employs conductive paste. We had good results for several reliability tests in the advanced MCM-L test vehicles. In particular, in the thermal shock test, the increase in connection resistance in the advanced MCM-Ls was smaller than that of MCM-Ls which used ordinary organic substrates instead of the ALIVH substrate. We manufactured a CCD camera module using these MCM-Ls. LSI chips were mounted on the six-layered ALIVH substrate. The MCM-Ls obtained was downsized (60% down) and lighter in weight (30% reduction) when compared with the conventional module, and the electrical characteristics of the newly manufactured CCD camera module were equal to those of the conventional module.
{"title":"Advanced MCM-Ls for consumer electronics","authors":"K. Amami, S. Yuhaku, T. Shiraishi, Y. Bessho, K. Eda, T. Ishida","doi":"10.1109/IEMTIM.1998.704631","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704631","url":null,"abstract":"We have developed an advanced MCM (multichip module) using the SBB/sup TM/ (stud-bump bonding) flip-chip technique on an ALIVH/sup TM/ (any layer inner via hole) structure substrate. The SBB technique is an advanced flip-chip bonding technique for high density MCM, which can mount bare LSI chips directly on substrates. The bonding portion structure is composed of Au bumps with two-stepped construction and conductive adhesives. The conductive adhesive is very flexible in bond, thus relaxing thermal and mechanical stresses. The ALIVH substrate is a high density and high performance multilayered printed wiring board with any layer inner via hole structure, CO/sub 2/ laser via hole processing technology and interconnection technology which employs conductive paste. We had good results for several reliability tests in the advanced MCM-L test vehicles. In particular, in the thermal shock test, the increase in connection resistance in the advanced MCM-Ls was smaller than that of MCM-Ls which used ordinary organic substrates instead of the ALIVH substrate. We manufactured a CCD camera module using these MCM-Ls. LSI chips were mounted on the six-layered ALIVH substrate. The MCM-Ls obtained was downsized (60% down) and lighter in weight (30% reduction) when compared with the conventional module, and the electrical characteristics of the newly manufactured CCD camera module were equal to those of the conventional module.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121163652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704701
F. Ueno, T. Motomura, H. Hirai, O. Shimada, Y. Sonoda, Y. Fukuoka
We have developed a new FCA (flip chip attach) technology based on a new concept. Bump formation is very important in FCA technology. In conventional FCA technology, bumps are formed on bare chips, and an additional process to LSI manufacturing processes is required for bump formation on the wafer to complete the semiconductor device functional circuits. However, bumps in the new technology are formed on the PWB. Consequently, it is possible to use bare chips supplied by any semiconductor device maker. We have developed two kinds of bump formation technologies based on a newly developed concept. The first is a method using silver paste bumps produced by thick film printing technology (presented at 1996 IMC), and the second is a method using electroplated copper bumps for fine pitch interconnections. In this process, copper bumps are formed on PWB electrode pads by electroplating. Then, underfill resin is dispensed to the bare chip assembly area of the PWB. After bare chip I/O pads are positioned on the bumps, the bare chip is pressed and heated. The underfill resin is then rapidly hardened to retain the bump interconnections between the PWB pads and the bare chip I/O pads. This FCA technology can supply a very simple process and structure. We examined the reliability of this FCA technology by temperature cycling and temperature humidity tests. This FCA technology is very useful for realization of a high density module with fine pitch I/O devices with I/O pitch under 200 /spl mu/m.
{"title":"New flip chip attach technology for fine pitch interconnections using electroplated copper bumps formed on a substrate","authors":"F. Ueno, T. Motomura, H. Hirai, O. Shimada, Y. Sonoda, Y. Fukuoka","doi":"10.1109/IEMTIM.1998.704701","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704701","url":null,"abstract":"We have developed a new FCA (flip chip attach) technology based on a new concept. Bump formation is very important in FCA technology. In conventional FCA technology, bumps are formed on bare chips, and an additional process to LSI manufacturing processes is required for bump formation on the wafer to complete the semiconductor device functional circuits. However, bumps in the new technology are formed on the PWB. Consequently, it is possible to use bare chips supplied by any semiconductor device maker. We have developed two kinds of bump formation technologies based on a newly developed concept. The first is a method using silver paste bumps produced by thick film printing technology (presented at 1996 IMC), and the second is a method using electroplated copper bumps for fine pitch interconnections. In this process, copper bumps are formed on PWB electrode pads by electroplating. Then, underfill resin is dispensed to the bare chip assembly area of the PWB. After bare chip I/O pads are positioned on the bumps, the bare chip is pressed and heated. The underfill resin is then rapidly hardened to retain the bump interconnections between the PWB pads and the bare chip I/O pads. This FCA technology can supply a very simple process and structure. We examined the reliability of this FCA technology by temperature cycling and temperature humidity tests. This FCA technology is very useful for realization of a high density module with fine pitch I/O devices with I/O pitch under 200 /spl mu/m.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132538949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704667
K. Goto, T. Oguma, Y. Fukuoka
The authors have developed the B/sup 2/it printed circuit board. The technology was reported initially in a paper at the IMC meeting in April 1996. Since that time, this technology has been applied to a variety of boards. Among these boards, we report in this paper the B/sup 2/it application to semiconductor packaging. The product has /spl phi/0.2/spl sim/0.1 mm bumps (fine bumps). In order to produce a multilayer high density printed circuit board, we need to add up each layer with conductive bumps over the base layer, which we call the en bloc laminate process. By repeating the en bloc laminate process multiple times, multilayers and stacked arrays are possible. Signals can go down to internal layers directly from surface pad via bumps. This is effective for substrates such as BGA type packages. With the use of the B/sup 2/it/sup TM/ method, it is possible to omit the outer layer plating process. This is an advantage for fine line patterning, because etching the copper foil alone enables circuit patterning. In addition, we introduced two types of liquid photoresist process: the ED method, and the spin coater liquid photoresist process.
{"title":"High density printed circuit board using B/sup 2/it/sup TM/ technology","authors":"K. Goto, T. Oguma, Y. Fukuoka","doi":"10.1109/IEMTIM.1998.704667","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704667","url":null,"abstract":"The authors have developed the B/sup 2/it printed circuit board. The technology was reported initially in a paper at the IMC meeting in April 1996. Since that time, this technology has been applied to a variety of boards. Among these boards, we report in this paper the B/sup 2/it application to semiconductor packaging. The product has /spl phi/0.2/spl sim/0.1 mm bumps (fine bumps). In order to produce a multilayer high density printed circuit board, we need to add up each layer with conductive bumps over the base layer, which we call the en bloc laminate process. By repeating the en bloc laminate process multiple times, multilayers and stacked arrays are possible. Signals can go down to internal layers directly from surface pad via bumps. This is effective for substrates such as BGA type packages. With the use of the B/sup 2/it/sup TM/ method, it is possible to omit the outer layer plating process. This is an advantage for fine line patterning, because etching the copper foil alone enables circuit patterning. In addition, we introduced two types of liquid photoresist process: the ED method, and the spin coater liquid photoresist process.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131529013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704501
T. Ishida
Key future semiconductor packaging technology lies in bare-chip packaging technology and high-density circuit board technology. In bare-chip packaging technology, flip-chip packaging has been developed, while in high-density PCB technology, newly-designed substrate structures such as the build-up substrate have been developed. Matsushita have been developing stud-bump bonding (SBB) technology as a bare-chip packaging technology, and the any layer inner via hole (ALIVH) substrate as a high-density PCB. The overall development of packaging technology resulted in the development of the P201KYPER mobile phone with a weight less than 100 g for the first time in 1996 using the ALIVH substrate, and in 1997, we developed the P205HYPER mobile phone with a weight less than 80 g for the first time. The application of SBB and ALIVH technology offered early realization of these products, showing how great a role packaging technology plays in the development of electronic equipment. Considering business objectives to increase the market share by a strong product with higher performance or distinctive characteristics, the importance of semiconductor packaging technology is set to increase dramatically in future. This paper describes the concept, content and roadmap of the technology development, mostly in connection with the packaging technology developed by Matsushita.
{"title":"Advanced substrate and packaging technology","authors":"T. Ishida","doi":"10.1109/IEMTIM.1998.704501","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704501","url":null,"abstract":"Key future semiconductor packaging technology lies in bare-chip packaging technology and high-density circuit board technology. In bare-chip packaging technology, flip-chip packaging has been developed, while in high-density PCB technology, newly-designed substrate structures such as the build-up substrate have been developed. Matsushita have been developing stud-bump bonding (SBB) technology as a bare-chip packaging technology, and the any layer inner via hole (ALIVH) substrate as a high-density PCB. The overall development of packaging technology resulted in the development of the P201KYPER mobile phone with a weight less than 100 g for the first time in 1996 using the ALIVH substrate, and in 1997, we developed the P205HYPER mobile phone with a weight less than 80 g for the first time. The application of SBB and ALIVH technology offered early realization of these products, showing how great a role packaging technology plays in the development of electronic equipment. Considering business objectives to increase the market share by a strong product with higher performance or distinctive characteristics, the importance of semiconductor packaging technology is set to increase dramatically in future. This paper describes the concept, content and roadmap of the technology development, mostly in connection with the packaging technology developed by Matsushita.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"132 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704537
A. Ohki, M. Usui, N. Sato, N. Matsuura, K. Katsura, Y. Ando
ParaBIT (parallel inter-board optical interconnection technology) is a promising candidate for large-capacity board-to-board interconnection. In ParaBIT module assembly, a new multichip diebonding technique is needed, because precise optical device chip mounting is required for efficient optical coupling at the E/O (electric/optic conversion) and O/E (optic/electric conversion) interfaces. In this paper, we have proposed a new technique, called TMB (transferred multichip bonding), for the precise mounting of multiple optical device chips. We have also described the detailed procedures of TMB and demonstrated its use in ParaBIT module assembly.
{"title":"Fabrication of a parallel inter-board optical interconnection module using transferred multichip bonding","authors":"A. Ohki, M. Usui, N. Sato, N. Matsuura, K. Katsura, Y. Ando","doi":"10.1109/IEMTIM.1998.704537","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704537","url":null,"abstract":"ParaBIT (parallel inter-board optical interconnection technology) is a promising candidate for large-capacity board-to-board interconnection. In ParaBIT module assembly, a new multichip diebonding technique is needed, because precise optical device chip mounting is required for efficient optical coupling at the E/O (electric/optic conversion) and O/E (optic/electric conversion) interfaces. In this paper, we have proposed a new technique, called TMB (transferred multichip bonding), for the precise mounting of multiple optical device chips. We have also described the detailed procedures of TMB and demonstrated its use in ParaBIT module assembly.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121655626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704552
T. Nishio, Y. Yamada, K. Koyamada
The rapid improvement in computer performance is intensifying the component thermal problem. It is becoming increasingly important for an optimal thermal design that thermal simulation is part of the design. Simplification of the thermal simulation model is inevitable as an enormous number of finite elements are required when the original CAD data set is adopted for modeling. However, the reduction of calculation time by model simplification and the maintenance of calculation accuracy are contradictory. Conventionally, model simplification is by empirical judgment, but a rational simplification technique using boundary conditions and material properties results in a more accurate and reliable calculation. Although simplification of the LSI component modeling method has been proposed by the Delphi project, it is difficult to apply other than to components, such as a keyboard. This paper proposes a new technique to generate the compact model of a keyboard with the required accuracy. First, some candidates for the simplified configurations are prepared. A genetic algorithm is proposed to identify the variables such as the boundary conditions and thermal conductivities that are most important in a high accuracy calculation. Finally, the optimum compact model which has the required accuracy is selected from the simplified models.
{"title":"A compact modeling approach using a genetic algorithm for accurate thermal simulation","authors":"T. Nishio, Y. Yamada, K. Koyamada","doi":"10.1109/IEMTIM.1998.704552","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704552","url":null,"abstract":"The rapid improvement in computer performance is intensifying the component thermal problem. It is becoming increasingly important for an optimal thermal design that thermal simulation is part of the design. Simplification of the thermal simulation model is inevitable as an enormous number of finite elements are required when the original CAD data set is adopted for modeling. However, the reduction of calculation time by model simplification and the maintenance of calculation accuracy are contradictory. Conventionally, model simplification is by empirical judgment, but a rational simplification technique using boundary conditions and material properties results in a more accurate and reliable calculation. Although simplification of the LSI component modeling method has been proposed by the Delphi project, it is difficult to apply other than to components, such as a keyboard. This paper proposes a new technique to generate the compact model of a keyboard with the required accuracy. First, some candidates for the simplified configurations are prepared. A genetic algorithm is proposed to identify the variables such as the boundary conditions and thermal conductivities that are most important in a high accuracy calculation. Finally, the optimum compact model which has the required accuracy is selected from the simplified models.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132705777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704625
M. Amagai
A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in chip scale packages (CSP) mounted on PCBs. The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. Finite element models, incorporating the viscoplastic flow and evolution equations, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the viscoplastic deformation was studied for a tapeless lead-on-chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints, while a dwell time in excess of 10 minutes per half cycle does not result in an increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between experiment and model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated and the primary factors affecting solder fatigue life were subsequently presented. Furthermore, a simplified model was proposed to predict solder fatigue life in CSPs.
{"title":"Chip scale package (CSP) solder joint reliability and modeling","authors":"M. Amagai","doi":"10.1109/IEMTIM.1998.704625","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704625","url":null,"abstract":"A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in chip scale packages (CSP) mounted on PCBs. The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. Finite element models, incorporating the viscoplastic flow and evolution equations, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the viscoplastic deformation was studied for a tapeless lead-on-chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints, while a dwell time in excess of 10 minutes per half cycle does not result in an increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between experiment and model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated and the primary factors affecting solder fatigue life were subsequently presented. Furthermore, a simplified model was proposed to predict solder fatigue life in CSPs.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123573109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704529
R. Sato, S. Matsuda, K. Kata
D/sup 2/BGA (die dimension BGA) is an NEC CSP, consisting of die, flexible printed circuit tape, resin, solder bumps and reinforcement resin. Assembly consists of bonding, lamination, encapsulation, solder ball placement and singulation. The bonding technique uses IBB (inner bump bonding) technology. IBB is similar to ILB (inner lead bonding), using an ultrasonic thermocompression single point bonder for TAB. Instead of the TAB inner lead, inner bumps are bonded to an Al pad. The polyimide film is drilled on the Cu trace by laser ablation. The inner bumps are made of an electrodeposited Cu core and Au plating. Various factors affected the Al-Au intermetallic bond: (1) inner bump shape; (2) inner bump deformation; (3) polyimide base film thickness; and (4) the adhesive properties. The Au layer deformation ratio was one of the most important factors; in the three bonded parts, the Au layer, Cu core and Cu trace, Au layer deformation affected bonding quality most significantly. A lower Au layer deformation ratio resulted in poorer bonding. A low Cu core deformation ratio resulted in a high Au layer deformation ratio and gave a good intermetallic bond between the Au plated Cu bump and the Al pad. Flexible PC tape had a thermoplastic polyimide adhesive layer on the die side, and the bonding area was reinforced by the adhesive layer during the bonding operation. The adhesive properties were also found to affect the intermetallic bond. Lower adhesive strength caused damage to the Al pad or Si chip during bonding. Strong flexible PC tape-die surface adhesion resulted in highly reliable bonding.
{"title":"Inner bump bonding technology for CSP","authors":"R. Sato, S. Matsuda, K. Kata","doi":"10.1109/IEMTIM.1998.704529","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704529","url":null,"abstract":"D/sup 2/BGA (die dimension BGA) is an NEC CSP, consisting of die, flexible printed circuit tape, resin, solder bumps and reinforcement resin. Assembly consists of bonding, lamination, encapsulation, solder ball placement and singulation. The bonding technique uses IBB (inner bump bonding) technology. IBB is similar to ILB (inner lead bonding), using an ultrasonic thermocompression single point bonder for TAB. Instead of the TAB inner lead, inner bumps are bonded to an Al pad. The polyimide film is drilled on the Cu trace by laser ablation. The inner bumps are made of an electrodeposited Cu core and Au plating. Various factors affected the Al-Au intermetallic bond: (1) inner bump shape; (2) inner bump deformation; (3) polyimide base film thickness; and (4) the adhesive properties. The Au layer deformation ratio was one of the most important factors; in the three bonded parts, the Au layer, Cu core and Cu trace, Au layer deformation affected bonding quality most significantly. A lower Au layer deformation ratio resulted in poorer bonding. A low Cu core deformation ratio resulted in a high Au layer deformation ratio and gave a good intermetallic bond between the Au plated Cu bump and the Al pad. Flexible PC tape had a thermoplastic polyimide adhesive layer on the die side, and the bonding area was reinforced by the adhesive layer during the bonding operation. The adhesive properties were also found to affect the intermetallic bond. Lower adhesive strength caused damage to the Al pad or Si chip during bonding. Strong flexible PC tape-die surface adhesion resulted in highly reliable bonding.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128414231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704524
O. Suzuki, H. Yoshii, K. Suzuki
We have developed a next generation underfill encapsulant material for a compression bonding chip assembly process that is based on epoxy resin. As it has a high moisture resistance, we selected phenol resin as the curing agent for epoxy resin. The underfill material can be very significant for improvement of the flip chip assembly process for chip scale packages (CSP), multichip modules (MCM), and typical small packages. This compression bonding chip assembly process is very significant for low cost realization with high level production. However, the conventional underfill material could not adapt to the new assembly process which has a fast-cure process with the polymerization of the underfill. In this paper, we present specific experimental results for our underfill in this new flip-chip assembly process.
{"title":"High reliability and compression flow underfill encapsulant for flip-chip applications","authors":"O. Suzuki, H. Yoshii, K. Suzuki","doi":"10.1109/IEMTIM.1998.704524","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704524","url":null,"abstract":"We have developed a next generation underfill encapsulant material for a compression bonding chip assembly process that is based on epoxy resin. As it has a high moisture resistance, we selected phenol resin as the curing agent for epoxy resin. The underfill material can be very significant for improvement of the flip chip assembly process for chip scale packages (CSP), multichip modules (MCM), and typical small packages. This compression bonding chip assembly process is very significant for low cost realization with high level production. However, the conventional underfill material could not adapt to the new assembly process which has a fast-cure process with the polymerization of the underfill. In this paper, we present specific experimental results for our underfill in this new flip-chip assembly process.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129262339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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