Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704527
H. Tohyama, S. Ozawa, Y. Kitayama, T. Yamashita, Y. Nakamura
We have developed new direct bonding technology using anisotropic conductive film (ACF) connections between two chips. We applied this bonding technology in ultra fine pitch interconnections at 40 /spl mu/m between an LED array and a driver IC, and realized a minimized LED print head. The key point of direct bonding technology is assurance of connection reliability which can be improved by two important factors. One is the elastic recovery quantity of conductive particles between the connection electrodes, and the other is the adhesive strength of the chip bonding area. As a result of analysis with particular attention paid to these factors, we found two further features: (1) an elastic recovery quantity usually obtained by using soft conductive particles which was included in ACF, in the case of electrodes with variable form and hardness; (2) adhesive strength increased when accompanied with a rise in the curing temperature. We tested this technology by interconnection of 192 connection pads lined in 40 /spl mu/m pitch, and achieved good bonding reliability in temperature and relative humidity cycling tests. This new bonding technology is effective in ultra-fine pitch direct bonding, so that this technology can be widely applied to various types of device chip. In this paper, the details of the technology and the connection reliability are reported.
{"title":"The fine pitch direct bonding technology for chip interconnection","authors":"H. Tohyama, S. Ozawa, Y. Kitayama, T. Yamashita, Y. Nakamura","doi":"10.1109/IEMTIM.1998.704527","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704527","url":null,"abstract":"We have developed new direct bonding technology using anisotropic conductive film (ACF) connections between two chips. We applied this bonding technology in ultra fine pitch interconnections at 40 /spl mu/m between an LED array and a driver IC, and realized a minimized LED print head. The key point of direct bonding technology is assurance of connection reliability which can be improved by two important factors. One is the elastic recovery quantity of conductive particles between the connection electrodes, and the other is the adhesive strength of the chip bonding area. As a result of analysis with particular attention paid to these factors, we found two further features: (1) an elastic recovery quantity usually obtained by using soft conductive particles which was included in ACF, in the case of electrodes with variable form and hardness; (2) adhesive strength increased when accompanied with a rise in the curing temperature. We tested this technology by interconnection of 192 connection pads lined in 40 /spl mu/m pitch, and achieved good bonding reliability in temperature and relative humidity cycling tests. This new bonding technology is effective in ultra-fine pitch direct bonding, so that this technology can be widely applied to various types of device chip. In this paper, the details of the technology and the connection reliability are reported.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704533
H. Noro, S. Ito, M. Kuwamura, M. Mizutani
Flip chip packaging using plastic substrates is gaining popularity in the IC packaging market. However, the process has not been standardized as a real mass production system. We have newly developed a flip chip packaging technology using a nonconductive underfill resin sheet. The process flow of the new flip chip packaging is as follows. First, the underfill sheet is laminated to the substrate. Next, the bumped die is aligned and attached to the substrate, which is covered with the underfill sheet under appropriate heat and pressure conditions. The bumps under the die penetrate by displacing resin and eventually reach the metal land of the substrate. Finally, curing of the underfill sheet and metal connections is done. We have studied the possibility of application of this packaging technology to diversified bump and land combinations with changing underfill components and process parameters. The electrical stability under several stress test conditions such as JEDEC Level-3 and TST has been evaluated in this study. After this evaluation, we found that the packages which were built with the appropriate resin components and process parameters show good performance for all of these reliability tests, almost regardless of bump and land materials.
{"title":"A study of new flip chip packaging process for diversified bump and land combination","authors":"H. Noro, S. Ito, M. Kuwamura, M. Mizutani","doi":"10.1109/IEMTIM.1998.704533","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704533","url":null,"abstract":"Flip chip packaging using plastic substrates is gaining popularity in the IC packaging market. However, the process has not been standardized as a real mass production system. We have newly developed a flip chip packaging technology using a nonconductive underfill resin sheet. The process flow of the new flip chip packaging is as follows. First, the underfill sheet is laminated to the substrate. Next, the bumped die is aligned and attached to the substrate, which is covered with the underfill sheet under appropriate heat and pressure conditions. The bumps under the die penetrate by displacing resin and eventually reach the metal land of the substrate. Finally, curing of the underfill sheet and metal connections is done. We have studied the possibility of application of this packaging technology to diversified bump and land combinations with changing underfill components and process parameters. The electrical stability under several stress test conditions such as JEDEC Level-3 and TST has been evaluated in this study. After this evaluation, we found that the packages which were built with the appropriate resin components and process parameters show good performance for all of these reliability tests, almost regardless of bump and land materials.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"423 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115929604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704624
I. Hazeyama, K. Ikuina, M. Kimura, Y. Shimada
In order to realize high-density wiring and to increase the reliability of chip interconnection to printed wiring boards (PWBs), we have developed glass ceramic chip size packages (CSPs). A 64M-DRAM chip was connected to the glass ceramic substrate via Au bumps by a flip chip bonding technique with high interconnection reliability, and the substrate was mounted on a PWB via solder ball bumps. To evaluate the reliability of the glass ceramic CSP, a thermal stress simulation was performed and the analysis indicated that thin glass ceramic CSPs were highly reliable. This finding was supported by thermal cycle testing using actual glass ceramic CSPs and identically structured alumina CSPs. The thin glass ceramic CSPs passed 1000 cycles, although failures were detected on the alumina CSPs between 500 and 1000 cycles. These failures were analyzed and it was confirmed that fatigue fractures occurred in the solder ball bumps due to coefficient of thermal expansion (CTE) mismatch and substrate rigidity.
{"title":"Flip chip bonding reliability of advanced glass ceramic chip size package","authors":"I. Hazeyama, K. Ikuina, M. Kimura, Y. Shimada","doi":"10.1109/IEMTIM.1998.704624","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704624","url":null,"abstract":"In order to realize high-density wiring and to increase the reliability of chip interconnection to printed wiring boards (PWBs), we have developed glass ceramic chip size packages (CSPs). A 64M-DRAM chip was connected to the glass ceramic substrate via Au bumps by a flip chip bonding technique with high interconnection reliability, and the substrate was mounted on a PWB via solder ball bumps. To evaluate the reliability of the glass ceramic CSP, a thermal stress simulation was performed and the analysis indicated that thin glass ceramic CSPs were highly reliable. This finding was supported by thermal cycle testing using actual glass ceramic CSPs and identically structured alumina CSPs. The thin glass ceramic CSPs passed 1000 cycles, although failures were detected on the alumina CSPs between 500 and 1000 cycles. These failures were analyzed and it was confirmed that fatigue fractures occurred in the solder ball bumps due to coefficient of thermal expansion (CTE) mismatch and substrate rigidity.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117021532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704633
C. Val
Trends in interconnection techniques from 2D to 3D modules are presented. Historically, the different 3D interconnection techniques have been applied to memory modules for two reasons: market forces and simplicity. The development and manufacturing of 3D modules, firstly at Thomson-CSF from 1988 and subsequently at 3D PLUS from October 1995, addressed a variety of applications, including memory modules, calculation nodes, and microsystems. These different applications and perspectives are presented in this paper.
{"title":"The future of 3D packaging","authors":"C. Val","doi":"10.1109/IEMTIM.1998.704633","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704633","url":null,"abstract":"Trends in interconnection techniques from 2D to 3D modules are presented. Historically, the different 3D interconnection techniques have been applied to memory modules for two reasons: market forces and simplicity. The development and manufacturing of 3D modules, firstly at Thomson-CSF from 1988 and subsequently at 3D PLUS from October 1995, addressed a variety of applications, including memory modules, calculation nodes, and microsystems. These different applications and perspectives are presented in this paper.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115268448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704675
A. Nagai, K. Takemura, K. Isaka, O. Watanabe, K. Kojima, K. Matsuda, I. Watanabe
We have developed new anisotropic conductive adhesive films (ACFs) for flip-chip interconnection to organic substrates such as printed wiring boards (PWBs). In order to reduce thermal and mechanical stress and strain induced by CTE (coefficient of thermal expansion) mismatches between chip and organic substrate, the elastic modulus of the ACF adhesive resin was lowered. In addition, the ACF adhesion strength was enhanced by optimizing the adhesive resin formulation. As a result, the modified ACF in flip-chip interconnection between gold bumps of a chip and Ni/Au coated pads on an FR-4 PWB shows stable contact resistance of lower than 10 m/spl Omega/ even after exposure to various environmental tests such as a thermal cycling test (-55/spl deg/C/+125/spl deg/C, 1000 cycles) and a pressure cooker test (121/spl deg/C, 2 atm, 168 hr) following an IR reflow treatment (twice). In addition, the excellent connection reliability was confirmed by in-situ measurement of contact resistance on a thermal cycling test (-55/spl deg/C/+125/spl deg/C, 1,000 cycles) and a high temperature humidity test (85/spl deg/C/85%RH, 1,000 hr) following IR reflow treatment (twice).
{"title":"Anisotropic conductive adhesive films for flip-chip interconnection onto organic substrates","authors":"A. Nagai, K. Takemura, K. Isaka, O. Watanabe, K. Kojima, K. Matsuda, I. Watanabe","doi":"10.1109/IEMTIM.1998.704675","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704675","url":null,"abstract":"We have developed new anisotropic conductive adhesive films (ACFs) for flip-chip interconnection to organic substrates such as printed wiring boards (PWBs). In order to reduce thermal and mechanical stress and strain induced by CTE (coefficient of thermal expansion) mismatches between chip and organic substrate, the elastic modulus of the ACF adhesive resin was lowered. In addition, the ACF adhesion strength was enhanced by optimizing the adhesive resin formulation. As a result, the modified ACF in flip-chip interconnection between gold bumps of a chip and Ni/Au coated pads on an FR-4 PWB shows stable contact resistance of lower than 10 m/spl Omega/ even after exposure to various environmental tests such as a thermal cycling test (-55/spl deg/C/+125/spl deg/C, 1000 cycles) and a pressure cooker test (121/spl deg/C, 2 atm, 168 hr) following an IR reflow treatment (twice). In addition, the excellent connection reliability was confirmed by in-situ measurement of contact resistance on a thermal cycling test (-55/spl deg/C/+125/spl deg/C, 1,000 cycles) and a high temperature humidity test (85/spl deg/C/85%RH, 1,000 hr) following IR reflow treatment (twice).","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115485903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704618
K. Terashima, T. Toyoda
The overmolded plastic pad array carrier (OMPAC) is becoming a standard carrier in packaging technology. The OMPAC type surface mount package, however, has a drawback: popcorning during reflow soldering to mount to the motherboard. This phenomenon is ascribed to rapid expansion of water inside the plastic materials, which easily absorb moisture. The popcorning is readily confirmed as a delamination and/or a crack in a plastic package that reaches the outside of that package. Many studies of the package structure and assembly processes have been undertaken to eliminate the popcorn phenomenon. In this study, we investigated the raw materials to eliminate the popcorn phenomenon without changing the conventional OMPAC structure and assembly process. For the OMPAC PCB material, new materials with high glass transition temperature and/or low moisture absorption are investigated in comparison with the glass reinforced BT (bismaleimide triazine) resin most commonly used. For the mold compound, a new type of biphenyl material is studied in comparison with the customary multifunctional epoxy mold compound used. Since the popcorn phenomenon occurs between die and PCB, the die attach epoxy between them plays a very important part in the elimination of popcorning. For this purpose, we found a material with high glass transition temperature and excellent adhesive strength between die and PCB. Using this adequate combination of PCB, mold compound, and die attach epoxy, we realized an excellent package which exceeds JEDEC level 2 moisture sensitivity.
{"title":"Investigation of the popcorn phenomenon in overmolded plastic pad array carriers","authors":"K. Terashima, T. Toyoda","doi":"10.1109/IEMTIM.1998.704618","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704618","url":null,"abstract":"The overmolded plastic pad array carrier (OMPAC) is becoming a standard carrier in packaging technology. The OMPAC type surface mount package, however, has a drawback: popcorning during reflow soldering to mount to the motherboard. This phenomenon is ascribed to rapid expansion of water inside the plastic materials, which easily absorb moisture. The popcorning is readily confirmed as a delamination and/or a crack in a plastic package that reaches the outside of that package. Many studies of the package structure and assembly processes have been undertaken to eliminate the popcorn phenomenon. In this study, we investigated the raw materials to eliminate the popcorn phenomenon without changing the conventional OMPAC structure and assembly process. For the OMPAC PCB material, new materials with high glass transition temperature and/or low moisture absorption are investigated in comparison with the glass reinforced BT (bismaleimide triazine) resin most commonly used. For the mold compound, a new type of biphenyl material is studied in comparison with the customary multifunctional epoxy mold compound used. Since the popcorn phenomenon occurs between die and PCB, the die attach epoxy between them plays a very important part in the elimination of popcorning. For this purpose, we found a material with high glass transition temperature and excellent adhesive strength between die and PCB. Using this adequate combination of PCB, mold compound, and die attach epoxy, we realized an excellent package which exceeds JEDEC level 2 moisture sensitivity.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114390741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704708
S. Ogata, M. Kanai, T. Takei
Recent studies have provided Pb-free solder and soldering technology for use in electronic assemblies for interconnections in order to avoid water pollution due to the Pb in Sn-Pb solder. Pb-free solder characteristics must be evaluated rapidly and exactly for use in real products. This paper describes a new evaluation method for the wetting balance test of Pb-free solder alloys for use in reflow soldering processes.
{"title":"Wetting balance evaluation by SP tension method for Pb free solder paste","authors":"S. Ogata, M. Kanai, T. Takei","doi":"10.1109/IEMTIM.1998.704708","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704708","url":null,"abstract":"Recent studies have provided Pb-free solder and soldering technology for use in electronic assemblies for interconnections in order to avoid water pollution due to the Pb in Sn-Pb solder. Pb-free solder characteristics must be evaluated rapidly and exactly for use in real products. This paper describes a new evaluation method for the wetting balance test of Pb-free solder alloys for use in reflow soldering processes.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114838615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704626
H. Tenmei, T. Yamazaki, Y. Narizuka
A low-cost and high-density circuit board process is developed using Cu electroplating, which flattens uneven surfaces. A circuit board is made using the following process: (1) via-holes are made on a polyimide surface acting as an insulation layer; (2) the metal (Cr/Cu) used to supply the electroplating current is deposited by sputtering; (3) reversed line patterns are made by photolithography; (4) reversed line patterns and via-holes are plugged by simultaneous Cu electroplating; and (5) resist and metal are stripped. This new approach can reduce the number of processes compared with previous methods. However, one problem is that voids occur in the via-holes that have been plugged by the Cu electroplating process. We controlled the electroplating current density and electroplating bath conditions to plug the via-holes without voids. In addition, we fabricated a circuit board with two layers of lines. As a result, this new process has been shown to be capable of manufacturing a high-density circuit board.
{"title":"Study on planarizing process for high aspect ratio via-holes using for electroplating and apply to process for Cu/polyimide multilayer substrates","authors":"H. Tenmei, T. Yamazaki, Y. Narizuka","doi":"10.1109/IEMTIM.1998.704626","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704626","url":null,"abstract":"A low-cost and high-density circuit board process is developed using Cu electroplating, which flattens uneven surfaces. A circuit board is made using the following process: (1) via-holes are made on a polyimide surface acting as an insulation layer; (2) the metal (Cr/Cu) used to supply the electroplating current is deposited by sputtering; (3) reversed line patterns are made by photolithography; (4) reversed line patterns and via-holes are plugged by simultaneous Cu electroplating; and (5) resist and metal are stripped. This new approach can reduce the number of processes compared with previous methods. However, one problem is that voids occur in the via-holes that have been plugged by the Cu electroplating process. We controlled the electroplating current density and electroplating bath conditions to plug the via-holes without voids. In addition, we fabricated a circuit board with two layers of lines. As a result, this new process has been shown to be capable of manufacturing a high-density circuit board.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125230673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704670
M. Shiraishi
A magnetoresistive (MR) head with the driver IC chip on a circuit integrated suspension structure has been developed. The structural characteristics of this MR head include an optimally designed circuit integrated suspension and a small bare driver IC chip with solder bumps. The driver lC chip is located very close to the MR head slider on the suspension. This structure minimizes parasitic resistance, capacitance and inductance on the lines of the suspension between the driver lC chip and the MR head slider. Higher speed magnetic write and read data rates have been achieved. This paper presents the flip chip bonding of the driver lC chip to the circuit integrated suspension. Due to the compactness of the IC assembly, we could achieve performances such as greater mechanical fly height and resonance during magnetic data seek on the hard disk, and faster electrical data rates.
{"title":"Chip on suspension MR head","authors":"M. Shiraishi","doi":"10.1109/IEMTIM.1998.704670","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704670","url":null,"abstract":"A magnetoresistive (MR) head with the driver IC chip on a circuit integrated suspension structure has been developed. The structural characteristics of this MR head include an optimally designed circuit integrated suspension and a small bare driver IC chip with solder bumps. The driver lC chip is located very close to the MR head slider on the suspension. This structure minimizes parasitic resistance, capacitance and inductance on the lines of the suspension between the driver lC chip and the MR head slider. Higher speed magnetic write and read data rates have been achieved. This paper presents the flip chip bonding of the driver lC chip to the circuit integrated suspension. Due to the compactness of the IC assembly, we could achieve performances such as greater mechanical fly height and resonance during magnetic data seek on the hard disk, and faster electrical data rates.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128251807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-15DOI: 10.1109/IEMTIM.1998.704504
J. Simon
The requirements for wafer-level CSP technology concerning reliability and cost are discussed. A simple cost calculation based on cost per I/O for single chip packaging demonstrates the advantage of wafer-level CSP-type packaging and gives a cost limit for wafer-level packaging technologies. The geometrical limitations are noted. The reliability requirements for successful implementation are described. A wafer-level packaging concept called Diepack is used to study the requirements for wafer-level packaging. It is shown that wafer-level CSP-type packaging can be achieved with "simple" technologies for small dice.
{"title":"Future waferlevel CSP packaging","authors":"J. Simon","doi":"10.1109/IEMTIM.1998.704504","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704504","url":null,"abstract":"The requirements for wafer-level CSP technology concerning reliability and cost are discussed. A simple cost calculation based on cost per I/O for single chip packaging demonstrates the advantage of wafer-level CSP-type packaging and gives a cost limit for wafer-level packaging technologies. The geometrical limitations are noted. The reliability requirements for successful implementation are described. A wafer-level packaging concept called Diepack is used to study the requirements for wafer-level packaging. It is shown that wafer-level CSP-type packaging can be achieved with \"simple\" technologies for small dice.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130117063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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