The long-term reliability of the Static Random Access Memory (SRAM) is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistors are vulnerable to negative bias temperature instability (NBTI). In contrast, the back end of the line (BEoL) interconnects are prone to electromigration (EM), further aggravated in interconnect-dominant advanced technology nodes. To comply with the safety-critical standards, understanding the combined transistor and interconnect aging mechanisms in the SRAM array and effective testing methods is required. A precise aging model is a prerequisite for effective aging testing and mitigation. For this aim and at the FEoL, unlike the previous aging modeling that considered only a threshold voltage shift, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model. Further, at the BEoL, we use measurement-calibrated physical modeling for the EM. This integrative approach enables more comprehensive analyses and provides deeper insights into the combined effects of NBTI and EM on the degradation of SRAM functionality, considering the entire macro, including the bit-cell array and periphery circuitry in both the Fully Depleted Silicon On Insulator (FDSOI) and Fin Field-Effect Transistor (FinFET) technologies.
{"title":"Effect of Transistor and Interconnect Scaling on Aging in Advanced SRAM","authors":"Zhe Zhang;Mahta Mayahinia;Christian Weis;Norbert Wehn;Mehdi Tahoori;Sani Nassif;Grigor Tshagharyan;Gurgen Harutyunyan;Yervant Zorian","doi":"10.1109/TDMR.2026.3693656","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3693656","url":null,"abstract":"The long-term reliability of the Static Random Access Memory (SRAM) is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistors are vulnerable to negative bias temperature instability (NBTI). In contrast, the back end of the line (BEoL) interconnects are prone to electromigration (EM), further aggravated in interconnect-dominant advanced technology nodes. To comply with the safety-critical standards, understanding the combined transistor and interconnect aging mechanisms in the SRAM array and effective testing methods is required. A precise aging model is a prerequisite for effective aging testing and mitigation. For this aim and at the FEoL, unlike the previous aging modeling that considered only a threshold voltage shift, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model. Further, at the BEoL, we use measurement-calibrated physical modeling for the EM. This integrative approach enables more comprehensive analyses and provides deeper insights into the combined effects of NBTI and EM on the degradation of SRAM functionality, considering the entire macro, including the bit-cell array and periphery circuitry in both the Fully Depleted Silicon On Insulator (FDSOI) and Fin Field-Effect Transistor (FinFET) technologies.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"917-926"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-10-12DOI: 10.1109/TDMR.2026.3739661
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2026.3739661","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3739661","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11733521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-07-22DOI: 10.1109/TDMR.2026.3716119
Sandeep Kumar;Deven H. Patil;Vanshika Ghai;Sunil Rathore;Govind Bajpai;S. Dasgupta;Navjeet Bagga
The device integrity critically depends on the co-optimization of the electrostatic control and thermal management in device design and reliability. This work considers nanosheet-based Complementary FET (CFET) as a baseline configuration, with n-FET (N) sheets stacked atop p-FET (P) sheets. In CFET structure, the source/drain (S/D) spacer material and its length critically influence the device electrostatics and self-heating. To address this coupled behavior, using well-calibrated TCAD models, the critically engineered role of asymmetric dielectric spacer lengths made of dissimilar materials is investigated to co-optimize the device’s electro-thermal characteristics. The asymmetric lengths of the source-side spacer (L${}_{mathrm {SPS}}$ ) and drain-side spacer (L${}_{mathrm {SPD}}$ ) vary from 3 nm to 7 nm, with 5 nm as the baseline value calibrated against experimental data. Increasing LSPS degrades ON current (I${}_{mathrm {ON}}$ ) by 26.17% in nFET and 22.61% in pFET due to SHE. In turn, the figure of merit (FoM), defined as ION/Cgg, and the cut-off frequency (f${}_{mathrm {T}}$ ) improve by 15.03% (12.1%) and 17.58% (13.92%), respectively, in nFET (pFET) when LSPD increases while keeping LSPS fixed at 5 nm. Further, a semi-empirical model is developed to determine the differential change in ION of the proposed asymmetric spacer configurations. Finally, a single-transistor (1T) CFET-based inverter and a FO4 cell are designed to analyze the impact of proposed asymmetric spacer configurations on the speed-power trade-off, using HfO2 and SiO2 spacer materials to optimize fringe coupling, self-heating, and overshoot. Thus, the proposed study provides a pivotal design knob for achieving balanced electrostatic control, transient stability, and thermal reliability in scaled CFET devices.
{"title":"Electro-Thermal Reliability Assessment of an Asymmetric Spacer Complementary FET: Device to Circuit Co-Optimization","authors":"Sandeep Kumar;Deven H. Patil;Vanshika Ghai;Sunil Rathore;Govind Bajpai;S. Dasgupta;Navjeet Bagga","doi":"10.1109/TDMR.2026.3716119","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3716119","url":null,"abstract":"The device integrity critically depends on the co-optimization of the electrostatic control and thermal management in device design and reliability. This work considers nanosheet-based Complementary FET (CFET) as a baseline configuration, with n-FET (N) sheets stacked atop p-FET (P) sheets. In CFET structure, the source/drain (S/D) spacer material and its length critically influence the device electrostatics and self-heating. To address this coupled behavior, using well-calibrated TCAD models, the critically engineered role of asymmetric dielectric spacer lengths made of dissimilar materials is investigated to co-optimize the device’s electro-thermal characteristics. The asymmetric lengths of the source-side spacer (L<inline-formula> <tex-math>${}_{mathrm {SPS}}$ </tex-math></inline-formula>) and drain-side spacer (L<inline-formula> <tex-math>${}_{mathrm {SPD}}$ </tex-math></inline-formula>) vary from 3 nm to 7 nm, with 5 nm as the baseline value calibrated against experimental data. Increasing L<sub>SPS</sub> degrades ON current (I<inline-formula> <tex-math>${}_{mathrm {ON}}$ </tex-math></inline-formula>) by 26.17% in nFET and 22.61% in pFET due to SHE. In turn, the figure of merit (FoM), defined as I<sub>ON</sub>/C<sub>gg,</sub> and the cut-off frequency (f<inline-formula> <tex-math>${}_{mathrm {T}}$ </tex-math></inline-formula>) improve by 15.03% (12.1%) and 17.58% (13.92%), respectively, in nFET (pFET) when L<sub>SPD</sub> increases while keeping L<sub>SPS</sub> fixed at 5 nm. Further, a semi-empirical model is developed to determine the differential change in I<sub>ON</sub> of the proposed asymmetric spacer configurations. Finally, a single-transistor (1T) CFET-based inverter and a FO4 cell are designed to analyze the impact of proposed asymmetric spacer configurations on the speed-power trade-off, using HfO<sub>2</sub> and SiO<sub>2</sub> spacer materials to optimize fringe coupling, self-heating, and overshoot. Thus, the proposed study provides a pivotal design knob for achieving balanced electrostatic control, transient stability, and thermal reliability in scaled CFET devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"959-966"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-07-16DOI: 10.1109/TDMR.2026.3714004
Sowon Kim;Je Won Park;Suyeon Kim;Dongyeong Kim;Shinwook Kim;Ryun Kang;Chaehyuk Lim;Hyerin Lee;Hyeona Seo;Jeonghyeon Yun;Juwon Lee;Geon Kim;Myoung Jin Lee
In this paper, we present a new physical mechanism related to the voltage drop induced by heavy-ion-induced Single Event Upset (SEU) in the device structure, and propose an analytical methodology for this effect in memory semiconductors using the Partial Insulator in a Buried Channel Array Transistor (Pi-BCAT). In previous studies, Pi-BCAT was shown to improve Gate-Induced Drain Leakage (GIDL) and Row Hammer Effect (RHE) characteristics compared to BCAT by inserting an insulator in the lower region of the BCAT Storage Node (SN). However, in a space environment, SEU can occur due to high energy particle strikes, and GIDL and RHE characteristics can be additionally degraded as a result. This can induce abnormal inversion (bit-flip) of stored information in memory semiconductors, critically affecting system reliability. Therefore, in this study, the effect of charge generated by heavy ion irradiation on the SN voltage drop of BCAT and Pi-BCAT is analyzed. In addition, trap, which has been regarded as a conventional reliability degradation factor, is reinterpreted, and it is shown that the SN voltage drop due to SEU can be mitigated through Trap-Assisted Tunneling Recombination (TAT Recombination), and this is defined as Trap-Assisted SEU Mitigation (TASM). When trap is present, electrons generated by heavy ions are annihilated by TAT Recombination, and it is confirmed that the SN voltage drop is improved by 73% compared to the case without trap. The proposed Pi-BCAT suppresses the funnel effect compared to the conventional BCAT, and improves the voltage drop variation amount by 39% by TASM operating effectively in the strengthened electric field region above Pi. Therefore, it is confirmed that the Pi-BCAT structure improves the SN voltage drop and enhances SEU tolerance compared to the conventional BCAT.
在本文中，我们提出了一种与重离子引起的单事件扰动（SEU）在器件结构中引起的电压降有关的新的物理机制，并提出了一种使用埋道阵列晶体管部分绝缘体（Pi-BCAT）的存储半导体中这种效应的分析方法。在先前的研究中，通过在BCAT存储节点（SN）的下部区域插入绝缘体，Pi-BCAT被证明可以改善栅极诱发漏漏（GIDL）和排锤效应（RHE）特性。然而，在空间环境中，由于高能粒子的撞击，可能会发生SEU，从而导致GIDL和RHE特性进一步退化。这会引起存储在存储器半导体中的信息的异常反转（位翻转），严重影响系统的可靠性。因此，本研究分析了重离子辐照产生的电荷对BCAT和Pi-BCAT的SN压降的影响。此外，对被认为是传统可靠性退化因素的陷阱进行了重新解释，并表明可以通过陷阱辅助隧道重组（trap - assisted Tunneling Recombination, TAT Recombination）来减轻由于SEU引起的SN电压下降，并将其定义为陷阱辅助SEU缓解（trap - assisted SEU Mitigation， TASM）。当存在陷阱时，重离子产生的电子被TAT复合湮灭，并证实SN电压降比不存在陷阱时提高了73%。与传统的BCAT相比，所提出的Pi-BCAT抑制了漏斗效应，并通过TASM在Pi以上的强化电场区域有效工作，将电压降变化量提高了39%。因此，与传统的BCAT相比，Pi-BCAT结构改善了SN压降，提高了SEU容差。
{"title":"Single Event Upset Mitigation in Buried Channel Array Transistors via Partial Insulating Layer (Pi) Structure and Trap-Assisted SEU Mitigation: Structural Proposal and Analytical Approach","authors":"Sowon Kim;Je Won Park;Suyeon Kim;Dongyeong Kim;Shinwook Kim;Ryun Kang;Chaehyuk Lim;Hyerin Lee;Hyeona Seo;Jeonghyeon Yun;Juwon Lee;Geon Kim;Myoung Jin Lee","doi":"10.1109/TDMR.2026.3714004","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3714004","url":null,"abstract":"In this paper, we present a new physical mechanism related to the voltage drop induced by heavy-ion-induced Single Event Upset (SEU) in the device structure, and propose an analytical methodology for this effect in memory semiconductors using the Partial Insulator in a Buried Channel Array Transistor (Pi-BCAT). In previous studies, Pi-BCAT was shown to improve Gate-Induced Drain Leakage (GIDL) and Row Hammer Effect (RHE) characteristics compared to BCAT by inserting an insulator in the lower region of the BCAT Storage Node (SN). However, in a space environment, SEU can occur due to high energy particle strikes, and GIDL and RHE characteristics can be additionally degraded as a result. This can induce abnormal inversion (bit-flip) of stored information in memory semiconductors, critically affecting system reliability. Therefore, in this study, the effect of charge generated by heavy ion irradiation on the SN voltage drop of BCAT and Pi-BCAT is analyzed. In addition, trap, which has been regarded as a conventional reliability degradation factor, is reinterpreted, and it is shown that the SN voltage drop due to SEU can be mitigated through Trap-Assisted Tunneling Recombination (TAT Recombination), and this is defined as Trap-Assisted SEU Mitigation (TASM). When trap is present, electrons generated by heavy ions are annihilated by TAT Recombination, and it is confirmed that the SN voltage drop is improved by 73% compared to the case without trap. The proposed Pi-BCAT suppresses the funnel effect compared to the conventional BCAT, and improves the voltage drop variation amount by 39% by TASM operating effectively in the strengthened electric field region above Pi. Therefore, it is confirmed that the Pi-BCAT structure improves the SN voltage drop and enhances SEU tolerance compared to the conventional BCAT.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1032-1043"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The degradation behavior of 1200 V planar-gate 4H-SiC MOSFETs under 10 MeV proton irradiation was investigated by combining Geant4 energy-deposition simulation, electrical characterization, deep-level transient spectroscopy (DLTS) analysis, and double-pulse switching tests. Irradiation was performed at a fluence of $1 times 10^{12}$ cm−2. The simulation results show that energy deposition in the sensitive regions is dominated by ionizing effects. After irradiation, the device exhibits a pronounced negative threshold-voltage shift and longer turn-off delay. In addition, both the $C_{mathrm {gs}}$ –$V_{mathrm {gs}}$ and $C_{mathrm {gd}}$ –$V_{mathrm {gs}}$ characteristics shift toward lower gate voltage. Trap extraction from electrical measurements further shows that the increase in oxide-trapped charge is much larger than that in interface-trap density, indicating that the degradation in the gate-oxide/near-interface region is mainly governed by oxide-trapped charge buildup. Meanwhile, the off-state leakage current increases significantly after irradiation. DLTS results further reveal significant increases in the concentrations of the deep-level traps E2 ($E_{mathrm {C}}-0.72$ eV) and E$3~(E_{mathrm {C}}-0.93$ eV), which are considered to participate in trap-assisted leakage transport under reverse bias and thus contribute to leakage degradation.
{"title":"Degradation Mechanism of 4H-SiC MOSFET Under 10-MeV Proton Irradiation","authors":"Hao Li;Le Zhong;Zhao Sun;Heyi Li;Yiping Xiao;Jing Qiao;Jiaming Zhou;Yuhang Wang;Yun Bai;Binghuang Duan;Chaoming Liu","doi":"10.1109/TDMR.2026.3716277","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3716277","url":null,"abstract":"The degradation behavior of 1200 V planar-gate 4H-SiC MOSFETs under 10 MeV proton irradiation was investigated by combining Geant4 energy-deposition simulation, electrical characterization, deep-level transient spectroscopy (DLTS) analysis, and double-pulse switching tests. Irradiation was performed at a fluence of <inline-formula> <tex-math>$1 times 10^{12}$ </tex-math></inline-formula> cm<sup>−2</sup>. The simulation results show that energy deposition in the sensitive regions is dominated by ionizing effects. After irradiation, the device exhibits a pronounced negative threshold-voltage shift and longer turn-off delay. In addition, both the <inline-formula> <tex-math>$C_{mathrm {gs}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V_{mathrm {gs}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$C_{mathrm {gd}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V_{mathrm {gs}}$ </tex-math></inline-formula> characteristics shift toward lower gate voltage. Trap extraction from electrical measurements further shows that the increase in oxide-trapped charge is much larger than that in interface-trap density, indicating that the degradation in the gate-oxide/near-interface region is mainly governed by oxide-trapped charge buildup. Meanwhile, the off-state leakage current increases significantly after irradiation. DLTS results further reveal significant increases in the concentrations of the deep-level traps E2 (<inline-formula> <tex-math>$E_{mathrm {C}}-0.72$ </tex-math></inline-formula> eV) and E<inline-formula> <tex-math>$3~(E_{mathrm {C}}-0.93$ </tex-math></inline-formula> eV), which are considered to participate in trap-assisted leakage transport under reverse bias and thus contribute to leakage degradation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1044-1050"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-02DOI: 10.1109/TDMR.2026.3699552
Ming Sha;Lei Shi;Wenjie Liu;Zhe Lv;Huanan Cui;Yuhuan Zhang;Qingyu Zeng;Xuxin Chen;Jianqun Yang;Weiqi Li;Yuhang Jing;Xingji Li
Stacked Aluminum Polymer Capacitors (SAPCs) exhibit high operating voltage, large capacitance, ultra-low equivalent series resistance (ESR), and stable performance across a wide temperature range. These characteristics position SAPCs as a strong candidate for high-reliability electronic systems. Despite their advantages, the absence of systematic studies on their failure mechanisms under humid stress limits further reliability improvements. This study integrates experimental analysis with first-principles simulations to clarify the degradation mechanisms of SAPCs in moist environments. Increased leakage current is primarily governed by defect-assisted electronic leakage in the $gamma $ -Al2O3 dielectric, while under humid conditions hydration-related phase transformation further accelerates this same process through local phase transformation and weak-point formation. The increase in ESR is associated with moisture-induced swelling of the cathode, compositional alterations, and interfacial mismatches. Based on these results, a cyclic voltammetry based rapid screening and preconditioning approach is proposed for SAPCs exposed to humid environments. The research provides a theoretical explanation for understanding the impact of moisture ingress on SAPCs’ performance and offers practical recommendations for managing reliability throughout production, storage, transportation, and testing.
{"title":"Research on the Degradation Mechanism of Stacked Aluminum Polymer Capacitors in Humid Environments","authors":"Ming Sha;Lei Shi;Wenjie Liu;Zhe Lv;Huanan Cui;Yuhuan Zhang;Qingyu Zeng;Xuxin Chen;Jianqun Yang;Weiqi Li;Yuhang Jing;Xingji Li","doi":"10.1109/TDMR.2026.3699552","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3699552","url":null,"abstract":"Stacked Aluminum Polymer Capacitors (SAPCs) exhibit high operating voltage, large capacitance, ultra-low equivalent series resistance (ESR), and stable performance across a wide temperature range. These characteristics position SAPCs as a strong candidate for high-reliability electronic systems. Despite their advantages, the absence of systematic studies on their failure mechanisms under humid stress limits further reliability improvements. This study integrates experimental analysis with first-principles simulations to clarify the degradation mechanisms of SAPCs in moist environments. Increased leakage current is primarily governed by defect-assisted electronic leakage in the <inline-formula> <tex-math>$gamma $ </tex-math></inline-formula>-Al<sub>2</sub>O<sub>3</sub> dielectric, while under humid conditions hydration-related phase transformation further accelerates this same process through local phase transformation and weak-point formation. The increase in ESR is associated with moisture-induced swelling of the cathode, compositional alterations, and interfacial mismatches. Based on these results, a cyclic voltammetry based rapid screening and preconditioning approach is proposed for SAPCs exposed to humid environments. The research provides a theoretical explanation for understanding the impact of moisture ingress on SAPCs’ performance and offers practical recommendations for managing reliability throughout production, storage, transportation, and testing.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"906-916"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-22DOI: 10.1109/TDMR.2026.3706105
JuHwan Kim;Junseop Lee;Changwoon Han
Insulated gate bipolar transistors (IGBTs) are widely used in electric vehicles (EVs), renewable energy systems, and power grids due to their high efficiency and power-handling capability. As these applications demand high reliability, accurate lifetime prediction is increasingly important. However, most existing lifetime prediction models (LPMs) target IGBT modules and remain predominantly statistical, relying on empirical fitting with limited physical insight and generalizability. Consequently, Physics-of-Failure (PoF)-based LPMs specifically developed for discrete IGBTs remain limited. This study addresses this gap by developing a PoF-based LPM focused on die-attach solder degradation as the dominant wear-out mechanism. Power-cycling experiments were conducted on discrete IGBTs employing 95.5Pb2Sn2.5Ag solder; devices were cycled to catastrophic failure under multiple junction temperature swing conditions, and scanning acoustic microscopy was used to assess solder degradation. An energy-based framework based on the volume-averaged inelastic strain energy density per cycle ($Delta W_{avg}$ ) was adopted. $Delta W_{avg}$ was computed via finite element analysis and used to calibrate the proposed LPM against experimental lifetimes. By leveraging physically motivated damage metrics, the approach is suited to lifetime prediction in settings where extensive field data are unavailable, supporting practical reliability assessment for discrete IGBTs.
{"title":"Development of Physics-of-Failure-Based Lifetime Prediction Model of Discrete IGBTs Under Power Cycling","authors":"JuHwan Kim;Junseop Lee;Changwoon Han","doi":"10.1109/TDMR.2026.3706105","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3706105","url":null,"abstract":"Insulated gate bipolar transistors (IGBTs) are widely used in electric vehicles (EVs), renewable energy systems, and power grids due to their high efficiency and power-handling capability. As these applications demand high reliability, accurate lifetime prediction is increasingly important. However, most existing lifetime prediction models (LPMs) target IGBT modules and remain predominantly statistical, relying on empirical fitting with limited physical insight and generalizability. Consequently, Physics-of-Failure (PoF)-based LPMs specifically developed for discrete IGBTs remain limited. This study addresses this gap by developing a PoF-based LPM focused on die-attach solder degradation as the dominant wear-out mechanism. Power-cycling experiments were conducted on discrete IGBTs employing 95.5Pb2Sn2.5Ag solder; devices were cycled to catastrophic failure under multiple junction temperature swing conditions, and scanning acoustic microscopy was used to assess solder degradation. An energy-based framework based on the volume-averaged inelastic strain energy density per cycle (<inline-formula> <tex-math>$Delta W_{avg}$ </tex-math></inline-formula>) was adopted. <inline-formula> <tex-math>$Delta W_{avg}$ </tex-math></inline-formula> was computed via finite element analysis and used to calibrate the proposed LPM against experimental lifetimes. By leveraging physically motivated damage metrics, the approach is suited to lifetime prediction in settings where extensive field data are unavailable, supporting practical reliability assessment for discrete IGBTs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"927-934"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-08-17DOI: 10.1109/TDMR.2026.3724258
Saurav Chanda;Srimanta Baishya;Rajesh Saha
This study investigates NanoSheet FET (NSFET) under the influence of heavy-ion radiation. A single, high-energy particle can alter device’s state or inflict temporary or permanent damage commonly known as a Single Event Effect (SEE). In this work, SEE at different incident angles and linear energy transfer (LET) circumstances have been measured in order to look into the radiation profile. Using 3D Sentaurus TCAD, investigation of the NSFET device at most sensitive regions when the heavy ion impregnates is looked into at different angles ($boldsymbol {theta }$ ) as well as azimuth ($boldsymbol {phi }$ ). This method makes it possible to assess how the device behaves for a variety of potential radiation directions that are pertinent to challenging operating conditions. Furthermore, several combinations of LET (2.41, 4.13, 4.94, 5.76, 10, 30, 50) is used to accurately assess the performance of the device at different $boldsymbol {theta }$ and $boldsymbol {phi }$ . For a broad range of LET, we have reported the transient drain current, collected charge, and heavy ion charge density. The results indicate that the maximum degradation occurs at $boldsymbol {phi } = 0^{circ }$ , $boldsymbol {theta } = 90^{circ }$ , $boldsymbol {phi } = 90^{circ }$ , $boldsymbol {theta } = 150^{circ }$ and $boldsymbol {phi } = 150^{circ }$ , $boldsymbol {theta } = 120^{circ }$ whereas the minimum response is observed at $boldsymbol {phi } = 90^{circ }$ , $boldsymbol {theta } = 60^{circ }$ and $boldsymbol {phi } = 90^{circ }$ , $boldsymbol {theta } = 90^{circ }$ . In order to demonstrate how sensitive these NSFETs are to angular radiation profiles, the analysis is further expanded to measure peak drain current and collected charge.
{"title":"Performance and Reliability Evaluation of Radiation Hardened NanoSheet FET","authors":"Saurav Chanda;Srimanta Baishya;Rajesh Saha","doi":"10.1109/TDMR.2026.3724258","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3724258","url":null,"abstract":"This study investigates NanoSheet FET (NSFET) under the influence of heavy-ion radiation. A single, high-energy particle can alter device’s state or inflict temporary or permanent damage commonly known as a Single Event Effect (SEE). In this work, SEE at different incident angles and linear energy transfer (LET) circumstances have been measured in order to look into the radiation profile. Using 3D Sentaurus TCAD, investigation of the NSFET device at most sensitive regions when the heavy ion impregnates is looked into at different angles (<inline-formula> <tex-math>$boldsymbol {theta }$ </tex-math></inline-formula>) as well as azimuth (<inline-formula> <tex-math>$boldsymbol {phi }$ </tex-math></inline-formula>). This method makes it possible to assess how the device behaves for a variety of potential radiation directions that are pertinent to challenging operating conditions. Furthermore, several combinations of LET (2.41, 4.13, 4.94, 5.76, 10, 30, 50) is used to accurately assess the performance of the device at different <inline-formula> <tex-math>$boldsymbol {theta }$ </tex-math></inline-formula> and <inline-formula> <tex-math>$boldsymbol {phi }$ </tex-math></inline-formula>. For a broad range of LET, we have reported the transient drain current, collected charge, and heavy ion charge density. The results indicate that the maximum degradation occurs at <inline-formula> <tex-math>$boldsymbol {phi } = 0^{circ }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {theta } = 90^{circ }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {phi } = 90^{circ }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {theta } = 150^{circ }$ </tex-math></inline-formula> and <inline-formula> <tex-math>$boldsymbol {phi } = 150^{circ }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {theta } = 120^{circ }$ </tex-math></inline-formula> whereas the minimum response is observed at <inline-formula> <tex-math>$boldsymbol {phi } = 90^{circ }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {theta } = 60^{circ }$ </tex-math></inline-formula> and <inline-formula> <tex-math>$boldsymbol {phi } = 90^{circ }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$boldsymbol {theta } = 90^{circ }$ </tex-math></inline-formula>. In order to demonstrate how sensitive these NSFETs are to angular radiation profiles, the analysis is further expanded to measure peak drain current and collected charge.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1025-1031"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-03-20DOI: 10.1109/TDMR.2026.3695152
Zehao Wu;Jing Zhang;Zeqi Huang;Lei Shen;Minchi Hu;Wangshen Wen;Peiyu Li;Zongxuan Xie;Chang Cai
In recent years, Convolutional Neural Networks (CNNs) have emerged as a cornerstone technology for image processing tasks in safety-critical domains. Although advanced Artificial Intelligence (AI) acceleration devices are ideal for space applications due to their high computational efficiency and flexibility, they remain highly susceptible to Single Event Upsets (SEUs) and are still constrained by limited resources. Thus, it becomes imperative to design CNN implementations for Field-Programmable Gate Array (FPGA) devices that achieve a delicate balance between low cost and high reliability. However, traditional hardening strategies often neglect the sensitivity of internal nodes, relying instead on global or coarse-grained module-level hardening strategies that significantly increase resource overhead and degrade timing performance. To address this issue, we propose a basic unit partitioning strategy that divides CNN accelerators into functionally independent circuit nodes. Within our fault analysis framework, we map fault locations to specific nodes using address mapping, enabling sensitivity analysis. Additionally, we implement fine-grained hardening on critical nodes identified through sensitivity analysis and compare this strategy against module-level coarse-grained hardening and full triple modular redundancy (TMR) strategies. Fault analysis results reveal that our strategy delivers excellent hardening effectiveness at a reduced cost. Our strategy achieves a 31.9% reduction in resource overhead and a 29.9% improvement in timing performance compared to Full_TMR, with comparable fault tolerance. Compared to module-level hardening strategies, our approach achieves higher hardening efficiency. The irradiation experiment results further validate the effectiveness of our strategy, achieving a $10.6times $ improvement in Mean Time To Failure (MTTF) compared to the unhardened baseline, which is comparable to that of full TMR. The proposed reliability evaluation method achieves high accuracy, with errors within ±4.3%. Overall, the proposed hardening strategy and reliability evaluation method present a significant advancement in designing robust and cost-effective systems, holding vast potential for adoption in safety-critical fields such as aerospace and autonomous driving.
{"title":"Critical Node Sensitivity Analysis and High-Reliability Design for CNN Accelerators on 16-nm FPGA Devices","authors":"Zehao Wu;Jing Zhang;Zeqi Huang;Lei Shen;Minchi Hu;Wangshen Wen;Peiyu Li;Zongxuan Xie;Chang Cai","doi":"10.1109/TDMR.2026.3695152","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3695152","url":null,"abstract":"In recent years, Convolutional Neural Networks (CNNs) have emerged as a cornerstone technology for image processing tasks in safety-critical domains. Although advanced Artificial Intelligence (AI) acceleration devices are ideal for space applications due to their high computational efficiency and flexibility, they remain highly susceptible to Single Event Upsets (SEUs) and are still constrained by limited resources. Thus, it becomes imperative to design CNN implementations for Field-Programmable Gate Array (FPGA) devices that achieve a delicate balance between low cost and high reliability. However, traditional hardening strategies often neglect the sensitivity of internal nodes, relying instead on global or coarse-grained module-level hardening strategies that significantly increase resource overhead and degrade timing performance. To address this issue, we propose a basic unit partitioning strategy that divides CNN accelerators into functionally independent circuit nodes. Within our fault analysis framework, we map fault locations to specific nodes using address mapping, enabling sensitivity analysis. Additionally, we implement fine-grained hardening on critical nodes identified through sensitivity analysis and compare this strategy against module-level coarse-grained hardening and full triple modular redundancy (TMR) strategies. Fault analysis results reveal that our strategy delivers excellent hardening effectiveness at a reduced cost. Our strategy achieves a 31.9% reduction in resource overhead and a 29.9% improvement in timing performance compared to Full_TMR, with comparable fault tolerance. Compared to module-level hardening strategies, our approach achieves higher hardening efficiency. The irradiation experiment results further validate the effectiveness of our strategy, achieving a <inline-formula> <tex-math>$10.6times $ </tex-math></inline-formula> improvement in Mean Time To Failure (MTTF) compared to the unhardened baseline, which is comparable to that of full TMR. The proposed reliability evaluation method achieves high accuracy, with errors within ±4.3%. Overall, the proposed hardening strategy and reliability evaluation method present a significant advancement in designing robust and cost-effective systems, holding vast potential for adoption in safety-critical fields such as aerospace and autonomous driving.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"822-831"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-09-11DOI: 10.1109/TDMR.2026.3732979
Haneen G. Hezayyin;Mahta Mayahinia;Mehdi Tahoori
Content Addressable Memories (CAMs) enable fast pattern matching and are widely used in modern systems. ReRAM-based CAMs (ReCAMs) offer high density, low power, and non-volatility; however, the interaction between intrinsic ReRAM defects and CMOS process variations introduces complex faulty behaviors that challenge conventional diagnosis. Moreover, ReCAM arrays are highly susceptible to process, voltage, and temperature (PVT) variations, whose impact is amplified in computation-in-memory (CiM) architectures due to analog sensing. Accurately localizing faulty cells in ReCAMs is particularly challenging because all cells in a row share the same match-line (ML), while only small ML voltage differences reveal location-dependent fault behavior. This paper presents a variation-aware Design-for-Testability (DfT) framework for precise ReCAM fault localization. The proposed DfT circuitry combines a tunable OpAmp and ADC with an iterative diagnosis flow that adaptively adjusts gain and sampling time in a multi-step process to improve diagnostic resolution under PVT variation. Results show that favorable voltage and temperature operating points can be exploited to accelerate diagnosis and reduce sensing overhead, while a partitioning-based diagnosis strategy reduces required gain by approximately 80% for large arrays. Across diverse fault scenarios and PVT corners, the proposed method localizes faults in only 2–8 diagnosis iterations and achieves approximately $2.29times $ lower diagnostic latency than March-based approaches, while incurring only 0.36% area overhead and up to 6.3% test-power overhead.
{"title":"PVTVAD: PVT-Variation-Aware Fault Diagnosis in ReRAM-Based CAM Arrays","authors":"Haneen G. Hezayyin;Mahta Mayahinia;Mehdi Tahoori","doi":"10.1109/TDMR.2026.3732979","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3732979","url":null,"abstract":"Content Addressable Memories (CAMs) enable fast pattern matching and are widely used in modern systems. ReRAM-based CAMs (ReCAMs) offer high density, low power, and non-volatility; however, the interaction between intrinsic ReRAM defects and CMOS process variations introduces complex faulty behaviors that challenge conventional diagnosis. Moreover, ReCAM arrays are highly susceptible to process, voltage, and temperature (PVT) variations, whose impact is amplified in computation-in-memory (CiM) architectures due to analog sensing. Accurately localizing faulty cells in ReCAMs is particularly challenging because all cells in a row share the same match-line (ML), while only small ML voltage differences reveal location-dependent fault behavior. This paper presents a variation-aware Design-for-Testability (DfT) framework for precise ReCAM fault localization. The proposed DfT circuitry combines a tunable OpAmp and ADC with an iterative diagnosis flow that adaptively adjusts gain and sampling time in a multi-step process to improve diagnostic resolution under PVT variation. Results show that favorable voltage and temperature operating points can be exploited to accelerate diagnosis and reduce sensing overhead, while a partitioning-based diagnosis strategy reduces required gain by approximately 80% for large arrays. Across diverse fault scenarios and PVT corners, the proposed method localizes faults in only 2–8 diagnosis iterations and achieves approximately <inline-formula> <tex-math>$2.29times $ </tex-math></inline-formula> lower diagnostic latency than March-based approaches, while incurring only 0.36% area overhead and up to 6.3% test-power overhead.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"733-742"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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