Drift of multi-level conductance states is a key reliability concern for resistive random access memory (RRAM) used in multi-level storage and in-memory computing applications. This work experimentally quantifies how repeated read operations and elevated-temperature storage reshape multiple conductive states in Al5%:HfO2-based RRAM cells. Systematic read-disturb and multi-temperature retention experiments are performed on one-transistor-one-resistor (1T1R) arrays, and their evolution is analyzed through intra-level transition matrices and a distance-weighted reshuffling factor $F_{r}$ that jointly capture internal reshuffling dynamics beyond median and spread. Read-disturb exhibits a pronounced voltage dependence, with increasing reshuffling as $V_{mathrm {RD}}$ rises, whereas retention shows a two-phase thermal evolution dominated by an early warm-up reshuffling followed by a slower isothermal regime. Comparing incremental step pulse and verify algorithm (ISPVA) and one-shot programming (OSP) under identical targets and read-stress conditions further shows that both algorithms experience redistribution, but with different directionality and level dependence. These results clarify the distinct statistical signatures of field- and temperature-induced drift and identify the programming algorithm, read-voltage budget, and warm-up handling as key design knobs to improve the number of reliable levels in multi-level RRAM arrays.
{"title":"Field- and Temperature-Induced Drift in Multi-Level Al-Doped HfO2 RRAM","authors":"Andrea Baroni;Jianan Wen;Eduardo Pérez;Keerthi Dorai Swamy Reddy;Max Uhlmann;Stefan Pechmann;Christian Wenger;Daniele Ielmini;Cristian Zambelli","doi":"10.1109/TDMR.2026.3700862","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3700862","url":null,"abstract":"Drift of multi-level conductance states is a key reliability concern for resistive random access memory (RRAM) used in multi-level storage and in-memory computing applications. This work experimentally quantifies how repeated read operations and elevated-temperature storage reshape multiple conductive states in Al5%:HfO<sub>2</sub>-based RRAM cells. Systematic read-disturb and multi-temperature retention experiments are performed on one-transistor-one-resistor (1T1R) arrays, and their evolution is analyzed through intra-level transition matrices and a distance-weighted reshuffling factor <inline-formula> <tex-math>$F_{r}$ </tex-math></inline-formula> that jointly capture internal reshuffling dynamics beyond median and spread. Read-disturb exhibits a pronounced voltage dependence, with increasing reshuffling as <inline-formula> <tex-math>$V_{mathrm {RD}}$ </tex-math></inline-formula> rises, whereas retention shows a two-phase thermal evolution dominated by an early warm-up reshuffling followed by a slower isothermal regime. Comparing incremental step pulse and verify algorithm (ISPVA) and one-shot programming (OSP) under identical targets and read-stress conditions further shows that both algorithms experience redistribution, but with different directionality and level dependence. These results clarify the distinct statistical signatures of field- and temperature-induced drift and identify the programming algorithm, read-voltage budget, and warm-up handling as key design knobs to improve the number of reliable levels in multi-level RRAM arrays.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"871-879"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11552800","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HyperDimensional Computing (HDC) is a brain-inspired machine learning paradigm that encodes data into high-dimensional hypervectors and performs classification through similarity comparisons. Its computational efficiency, one-shot learning capability, and robustness to noise make it attractive for resource-constrained edge applications. However, HDC systems can still exhibit uncertainty when inputs deviate from the training distribution, such as with noisy or Out-of-Distribution (OOD) data, and when hardware faults occur within the encoding or classification stages, potentially compromising reliability in safety-critical scenarios. This work introduces SafeHDC, an ultra-lightweight, concurrent runtime mechanism that detects both input-induced uncertainty and hardware-induced anomalies without model retraining or added latency. SafeHDC identifies noisy and OOD inputs as well as internal faults with negligible hardware cost (2 LUTs, 1 register). Experimental results show that SafeHDC achieves competitive detection accuracy and reaches up to 100% fault-detection coverage in many situations, enabling real-time safety enhancement for HDC accelerators with minimal overhead.
{"title":"SafeHDC: Concurrent Uncertainty and Fault Detection in Hyperdimensional Computing","authors":"Mahboobe Sadeghipour Roodsari;Vincent Meyers;Mehdi Tahoori","doi":"10.1109/TDMR.2026.3685392","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3685392","url":null,"abstract":"HyperDimensional Computing (HDC) is a brain-inspired machine learning paradigm that encodes data into high-dimensional hypervectors and performs classification through similarity comparisons. Its computational efficiency, one-shot learning capability, and robustness to noise make it attractive for resource-constrained edge applications. However, HDC systems can still exhibit uncertainty when inputs deviate from the training distribution, such as with noisy or Out-of-Distribution (OOD) data, and when hardware faults occur within the encoding or classification stages, potentially compromising reliability in safety-critical scenarios. This work introduces SafeHDC, an ultra-lightweight, concurrent runtime mechanism that detects both input-induced uncertainty and hardware-induced anomalies without model retraining or added latency. SafeHDC identifies noisy and OOD inputs as well as internal faults with negligible hardware cost (2 LUTs, 1 register). Experimental results show that SafeHDC achieves competitive detection accuracy and reaches up to 100% fault-detection coverage in many situations, enabling real-time safety enhancement for HDC accelerators with minimal overhead.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"771-779"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-26DOI: 10.1109/TDMR.2026.3707731
Elijah Seth Cishugi;Tijmen T. Smit;Bruno Forlin;Carlo Cazzaniga;Kuan-Hsun Chen;Marco Ottavi
As memory cells continue to shrink in modern semiconductor technologies, radiation-induced Single Event Effects (SEEs), such as single- and multi-bit upsets, pose growing challenges to system reliability. While traditional error detection and correction approaches, such as Error Correcting Codes (ECC), are effective for single- and double-bit errors, they incur substantial overhead and complexity when scaled to detect multiple-bit errors. This study leverages the space-efficient and low-latency properties of Bloom Filters (BF) to create a lightweight, probabilistic instruction checker. We implement this checker within a stand-alone memory subsystem as well as directly into the instruction fetch path of the NEORV32 RISC-V soft-core and validate its performance using two separate neutron beam irradiation campaigns and complementary emulation-based fault injection campaigns. Experimental results from neutron beam tests and fault injection campaigns demonstrate the checker’s effectiveness in detecting single- and multi-bit errors, with measured detection rates near theoretical targets. Additionally, the integration of the BF-based checker into the NEORV32 soft core showcases its practical applicability in a microprocessor environment, maintaining high detection coverage even under multi-bit error conditions that degrade ECC reliability.
{"title":"Instruction Error Detection With Bloom Filters: Architecture, Radiation Testing, and Fault Injection","authors":"Elijah Seth Cishugi;Tijmen T. Smit;Bruno Forlin;Carlo Cazzaniga;Kuan-Hsun Chen;Marco Ottavi","doi":"10.1109/TDMR.2026.3707731","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3707731","url":null,"abstract":"As memory cells continue to shrink in modern semiconductor technologies, radiation-induced Single Event Effects (SEEs), such as single- and multi-bit upsets, pose growing challenges to system reliability. While traditional error detection and correction approaches, such as Error Correcting Codes (ECC), are effective for single- and double-bit errors, they incur substantial overhead and complexity when scaled to detect multiple-bit errors. This study leverages the space-efficient and low-latency properties of Bloom Filters (BF) to create a lightweight, probabilistic instruction checker. We implement this checker within a stand-alone memory subsystem as well as directly into the instruction fetch path of the NEORV32 RISC-V soft-core and validate its performance using two separate neutron beam irradiation campaigns and complementary emulation-based fault injection campaigns. Experimental results from neutron beam tests and fault injection campaigns demonstrate the checker’s effectiveness in detecting single- and multi-bit errors, with measured detection rates near theoretical targets. Additionally, the integration of the BF-based checker into the NEORV32 soft core showcases its practical applicability in a microprocessor environment, maintaining high detection coverage even under multi-bit error conditions that degrade ECC reliability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"752-760"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-17DOI: 10.1109/TDMR.2026.3704605
Weizhong Chen;Huimin Tan;Wei Li;Li Wan;Haifeng Qin;Hongsheng Zhang;Zhengsheng Han
A Reverse-Conducting LIGBT integrated with three-mode Self-Adaptive n-channel MOS (SAM), named SAM-LIGBT, is proposed. SAM-LIGBT consists of a control region and a conduction region. The control region is equivalent to two diodes connected in reverse series, with its P+ regions on both sides connected to the Collector and Emitter, respectively. When the Collector or Emitter voltage rises, the potential of the N-drift and buffer regions increases accordingly. The rise in N-drift potential creates an electron accumulation effect on both sides of the conduction region. The rise in buffer potential provides the gate voltage for the SAM. 1) During forward conduction, the SAM turns on, and the electron accumulation effect enhances electron injection efficiency. Meanwhile, the P-base substrate of the SAM acts as an electron barrier, eliminating the snapback phenomenon; 2) During reverse conduction state, the SAM turns on, providing reverse conduction capability; 3) During the turn-off process, the SAM turns on to form an electron extraction channel, accelerating electron removal, thereby shortening the turn-off time $t_{mathrm {OFF}}$ and reducing the turn-off loss $E_{mathrm {OFF}}$ . Additionally, the SAM improves the device’s short-circuit safety and reverse recovery capability. In summary, the SAM-LIGBT achieves snapback-free operation and an excellent trade-off between the forward voltage drop $V_{mathrm {ON}}$ and the turn-off loss $E_{mathrm {OFF}}$ .
{"title":"A Snapback-Free RC-LIGBT Integrated With Three-Mode Self-Adaptive nMOS for Improved Performance and Reliability","authors":"Weizhong Chen;Huimin Tan;Wei Li;Li Wan;Haifeng Qin;Hongsheng Zhang;Zhengsheng Han","doi":"10.1109/TDMR.2026.3704605","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3704605","url":null,"abstract":"A Reverse-Conducting LIGBT integrated with three-mode Self-Adaptive n-channel MOS (SAM), named SAM-LIGBT, is proposed. SAM-LIGBT consists of a control region and a conduction region. The control region is equivalent to two diodes connected in reverse series, with its P+ regions on both sides connected to the Collector and Emitter, respectively. When the Collector or Emitter voltage rises, the potential of the N-drift and buffer regions increases accordingly. The rise in N-drift potential creates an electron accumulation effect on both sides of the conduction region. The rise in buffer potential provides the gate voltage for the SAM. 1) During forward conduction, the SAM turns on, and the electron accumulation effect enhances electron injection efficiency. Meanwhile, the P-base substrate of the SAM acts as an electron barrier, eliminating the snapback phenomenon; 2) During reverse conduction state, the SAM turns on, providing reverse conduction capability; 3) During the turn-off process, the SAM turns on to form an electron extraction channel, accelerating electron removal, thereby shortening the turn-off time <inline-formula> <tex-math>$t_{mathrm {OFF}}$ </tex-math></inline-formula> and reducing the turn-off loss <inline-formula> <tex-math>$E_{mathrm {OFF}}$ </tex-math></inline-formula>. Additionally, the SAM improves the device’s short-circuit safety and reverse recovery capability. In summary, the SAM-LIGBT achieves snapback-free operation and an excellent trade-off between the forward voltage drop <inline-formula> <tex-math>$V_{mathrm {ON}}$ </tex-math></inline-formula> and the turn-off loss <inline-formula> <tex-math>$E_{mathrm {OFF}}$ </tex-math></inline-formula>.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"977-983"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-07-20DOI: 10.1109/TDMR.2026.3714783
Cen Chen;Bohang Lu;Zicheng Wang;XuanYu Lin;SuNan Bi;Hao Niu;Xuerong Ye;Guofu Zhai;Abraham M. Alcaide;Jose I. Leon;Leopoldo G. Franquelo
The transfer characteristics of silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are fundamental indicators relevant to their practical applications, with hysteresis serving as a critical measure of the interface defect density within the gate oxide layer. However, measurement delays pose challenges to the accurate extraction of these transfer characteristics. This study introduces an on-the-fly (OTF) technology to characterize dynamic transfer characteristics, effectively eliminating measurement delays and complex preconditioning operations. This advancement enables a more pronounced observation of hysteresis under continuous switching stress, providing a more realistic dynamic evaluation compared to conventional static measurements. Unlike previous studies, this research directly investigates the impact of various switching application configurations on extraction results and provides a physical basis for these findings. The results suggest an optimal stress configuration for the stable and maximized extraction of significant hysteresis, characterized by a lower switching voltage, an intentionally reduced switching speed, a lower temperature, and an increased gate voltage amplitude. Rather than serving as a direct online condition monitoring tool, this research aims to establish a robust offline characterization platform. This method bridges the gap between static testing and continuous dynamic operations, providing insight into the interface trap dynamics of SiC MOSFETs.
{"title":"Configuration Dependence in the Extraction of Dynamic Transfer Characteristic Hysteresis in Switching Applications of SiC MOSFETs","authors":"Cen Chen;Bohang Lu;Zicheng Wang;XuanYu Lin;SuNan Bi;Hao Niu;Xuerong Ye;Guofu Zhai;Abraham M. Alcaide;Jose I. Leon;Leopoldo G. Franquelo","doi":"10.1109/TDMR.2026.3714783","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3714783","url":null,"abstract":"The transfer characteristics of silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are fundamental indicators relevant to their practical applications, with hysteresis serving as a critical measure of the interface defect density within the gate oxide layer. However, measurement delays pose challenges to the accurate extraction of these transfer characteristics. This study introduces an on-the-fly (OTF) technology to characterize dynamic transfer characteristics, effectively eliminating measurement delays and complex preconditioning operations. This advancement enables a more pronounced observation of hysteresis under continuous switching stress, providing a more realistic dynamic evaluation compared to conventional static measurements. Unlike previous studies, this research directly investigates the impact of various switching application configurations on extraction results and provides a physical basis for these findings. The results suggest an optimal stress configuration for the stable and maximized extraction of significant hysteresis, characterized by a lower switching voltage, an intentionally reduced switching speed, a lower temperature, and an increased gate voltage amplitude. Rather than serving as a direct online condition monitoring tool, this research aims to establish a robust offline characterization platform. This method bridges the gap between static testing and continuous dynamic operations, providing insight into the interface trap dynamics of SiC MOSFETs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"995-1003"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Guest Editorial Special Issue on the 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2025","authors":"Marcello Traiola;Angeliki Kritikakou;Riccardo Cantoro;Elena Ioana Vatajelu","doi":"10.1109/TDMR.2026.3727072","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3727072","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"719-721"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11733619","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-07-14DOI: 10.1109/TDMR.2026.3713133
B. Pavithara;P. Prithvi
This paper explores the structural design and three-dimensional TCAD-based reliability assessment of an E-shaped CombFET optimized for advanced nanoscale CMOS technology nodes. The proposed architecture employs three stacked nanosheet channels interconnected through an asymmetric fin-like interbridge, forming an E-shaped topology that enhances gate to channel coupling while maintaining structural simplicity. Device level simulations are carried out using Sentaurus TCAD at a 12 nm gate length to evaluate electrostatic integrity and material induced reliability trends. In comparison with conventional NanosheetFET, CombFET, and TreeFET architectures, the proposed E-CombFET demonstrates improved ON-state drive capability and maintaining sub-threshold swing, indicating enhanced electrostatic control without degradation in subthreshold characteristics. Temperature dependent simulations conducted from 150 K to 450 K across different spacer materials reveals a moderate decrease in ($I_{mathrm {ON}}$ ) and a corresponding increase in ($I_{mathrm {OFF}}$ ) indicating thermally resilient operation with acceptable switching characteristics. In addition to performance improvement the proposed E-CombFET demonstrates favorable analog conductance modulation characteristics indicating its potential suitability for neuromorphhic computing applications.
{"title":"Reliability-Aware Structural and Spacer Optimization of E-Shaped CombFET for Advanced CMOS Nodes","authors":"B. Pavithara;P. Prithvi","doi":"10.1109/TDMR.2026.3713133","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3713133","url":null,"abstract":"This paper explores the structural design and three-dimensional TCAD-based reliability assessment of an E-shaped CombFET optimized for advanced nanoscale CMOS technology nodes. The proposed architecture employs three stacked nanosheet channels interconnected through an asymmetric fin-like interbridge, forming an E-shaped topology that enhances gate to channel coupling while maintaining structural simplicity. Device level simulations are carried out using Sentaurus TCAD at a 12 nm gate length to evaluate electrostatic integrity and material induced reliability trends. In comparison with conventional NanosheetFET, CombFET, and TreeFET architectures, the proposed E-CombFET demonstrates improved ON-state drive capability and maintaining sub-threshold swing, indicating enhanced electrostatic control without degradation in subthreshold characteristics. Temperature dependent simulations conducted from 150 K to 450 K across different spacer materials reveals a moderate decrease in (<inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula>) and a corresponding increase in (<inline-formula> <tex-math>$I_{mathrm {OFF}}$ </tex-math></inline-formula>) indicating thermally resilient operation with acceptable switching characteristics. In addition to performance improvement the proposed E-CombFET demonstrates favorable analog conductance modulation characteristics indicating its potential suitability for neuromorphhic computing applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"897-905"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-10-12DOI: 10.1109/TDMR.2026.3727040
Michael Waltl
If no abstract provided do not include one in the JATS XML
如果没有提供摘要，则不要在JATS XML中包含摘要
{"title":"Guest Editorial Special Section on the IEEE International Integrated Reliability Workshop (IIRW) 2025","authors":"Michael Waltl","doi":"10.1109/TDMR.2026.3727040","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3727040","url":null,"abstract":"If no abstract provided do not include one in the JATS XML","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"654-655"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11733479","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conventional flash error models, relying solely on an average raw bit error rate (RBER), fail to capture critical sector-level heterogeneity, leading to inaccurate reliability assessments and significant performance underestimation. We propose the Degradation-Reliability Error Analysis Model (DREAM) to jointly model page-level physical degradation factors such as program/erase cycle (PEC) and data retention time (RT), as well as sector-level statistical variability. By combining regularized thin-plate splines (TPS), a model-driven log-normal distribution, and random sampling, DREAM provides accurate intra-page sector RBER sets. Within the modeled range, it achieves a prediction mean absolute percentage error (MAPE) of 9.3%. Furthermore, simulation results based on real-world workloads reveal that existing average-based schemes, which solely predict page-level average RBER, underestimate the average read latency by approximately 16.1%, a discrepancy effectively captured by DREAM, facilitating a more realistic assessment of solid-state drive (SSD) reliability.
{"title":"A Page-Sector Joint Degradation-Reliability Error Analysis Model for High-Density NAND Flash","authors":"Longbin Chen;Jian Huang;Ruibin Zhou;Yuhan Wang;Zhiyi Yu","doi":"10.1109/TDMR.2026.3707285","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3707285","url":null,"abstract":"Conventional flash error models, relying solely on an average raw bit error rate (RBER), fail to capture critical sector-level heterogeneity, leading to inaccurate reliability assessments and significant performance underestimation. We propose the Degradation-Reliability Error Analysis Model (DREAM) to jointly model page-level physical degradation factors such as program/erase cycle (PEC) and data retention time (RT), as well as sector-level statistical variability. By combining regularized thin-plate splines (TPS), a model-driven log-normal distribution, and random sampling, DREAM provides accurate intra-page sector RBER sets. Within the modeled range, it achieves a prediction mean absolute percentage error (MAPE) of 9.3%. Furthermore, simulation results based on real-world workloads reveal that existing average-based schemes, which solely predict page-level average RBER, underestimate the average read latency by approximately 16.1%, a discrepancy effectively captured by DREAM, facilitating a more realistic assessment of solid-state drive (SSD) reliability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"888-896"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The short-circuit (SC) capability of silicon carbide (SiC) MOSFETs is weaker than that of silicon (Si) devices. Gate failure and thermal runaway failure are two typical SC failure modes and both failure mechanisms are related to temperature. In practical application, affected by SC protection action time, devices may fail during conduction or after turn-off, and it is of vital significance to investigate the impact of SC time ($t_{mathrm {sc}}$ ) on failure modes. In this paper, a SC failure experimental platform is built. The failure modes of planar SiC MOSFETs from different manufactures under limited and unlimited $t_{mathrm {sc}}$ are investigated and divided more detailed. Results indicate that there are multiple failure modes for failures after turn-off affecting by limited $t_{mathrm {sc}}$ , while the devices from different manufactures have different SC failure modes during SC conduction period when $t_{mathrm {sc}}$ is unlimited. In addition, the characteristics of failures are more complex for planar SiC MOSFETs with negative off-state gate voltage. Moreover, the behavior of electrical quantities under different operating conditions is analyzed and the relationship between SC failure modes with different $t_{mathrm {sc}}$ is revealed with an improved Cauer thermal model. It is verified that $t_{mathrm {sc}}$ has an influence on the SC failure modes of planar SiC MOSFETs.
{"title":"Influence of Short-Circuit Time on Short-Circuit Failure Modes of Planar Silicon Carbide MOSFETs","authors":"JiaHui Meng;Peng Sun;YuMeng Cai;HaoRan Zhang;Zhen Xin;ZhiBin Zhao","doi":"10.1109/TDMR.2024.3503280","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3503280","url":null,"abstract":"The short-circuit (SC) capability of silicon carbide (SiC) MOSFETs is weaker than that of silicon (Si) devices. Gate failure and thermal runaway failure are two typical SC failure modes and both failure mechanisms are related to temperature. In practical application, affected by SC protection action time, devices may fail during conduction or after turn-off, and it is of vital significance to investigate the impact of SC time (<inline-formula> <tex-math>$t_{mathrm {sc}}$ </tex-math></inline-formula>) on failure modes. In this paper, a SC failure experimental platform is built. The failure modes of planar SiC MOSFETs from different manufactures under limited and unlimited <inline-formula> <tex-math>$t_{mathrm {sc}}$ </tex-math></inline-formula> are investigated and divided more detailed. Results indicate that there are multiple failure modes for failures after turn-off affecting by limited <inline-formula> <tex-math>$t_{mathrm {sc}}$ </tex-math></inline-formula>, while the devices from different manufactures have different SC failure modes during SC conduction period when <inline-formula> <tex-math>$t_{mathrm {sc}}$ </tex-math></inline-formula> is unlimited. In addition, the characteristics of failures are more complex for planar SiC MOSFETs with negative off-state gate voltage. Moreover, the behavior of electrical quantities under different operating conditions is analyzed and the relationship between SC failure modes with different <inline-formula> <tex-math>$t_{mathrm {sc}}$ </tex-math></inline-formula> is revealed with an improved Cauer thermal model. It is verified that <inline-formula> <tex-math>$t_{mathrm {sc}}$ </tex-math></inline-formula> has an influence on the SC failure modes of planar SiC MOSFETs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1059-1068"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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