Pub Date : 2026-09-01Epub Date: 2026-06-29DOI: 10.1109/TDMR.2026.3707975
Yicheng Ke;Wangyong Chen;Linlin Cai
This work investigates the effect of domain density ($N_{Dom}$ ) on FeFET variability, from the device level to the circuit level, using a 2-FeFET-based ternary content addressable memory (TCAM) bit-cell. Monte Carlo simulations revealed that increasing $N_{Dom}$ suppressed DTD variations in threshold voltage (Cv decreased by 80%) and memory window (Cv decreased by 79%). Furthermore, circuit-level analysis showed TCAM search failure probability exceeded 80% when $N_{Dom} lt $ $100/mu m^{2}$ , while $N_{Dom} gt $ $700/mu m^{2}$ ensured robustness by stabilizing the dominant FeFET path. Finally, the proposed cross-scale design-space exploration framework formulates three quantitative guidelines that map the interplay between domain density, device sizing, and search functionality, providing a solid physical foundation for reliable 2-FeFET-based TCAM design.
{"title":"Domain Density Dependence in 2-FeFET-Based TCAM Bit-Cell: Search Failure Analysis and Design Optimization","authors":"Yicheng Ke;Wangyong Chen;Linlin Cai","doi":"10.1109/TDMR.2026.3707975","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3707975","url":null,"abstract":"This work investigates the effect of domain density (<inline-formula> <tex-math>$N_{Dom}$ </tex-math></inline-formula>) on FeFET variability, from the device level to the circuit level, using a 2-FeFET-based ternary content addressable memory (TCAM) bit-cell. Monte Carlo simulations revealed that increasing <inline-formula> <tex-math>$N_{Dom}$ </tex-math></inline-formula> suppressed DTD variations in threshold voltage (Cv decreased by 80%) and memory window (Cv decreased by 79%). Furthermore, circuit-level analysis showed TCAM search failure probability exceeded 80% when <inline-formula> <tex-math>$N_{Dom} lt $ </tex-math></inline-formula><inline-formula> <tex-math>$100/mu m^{2}$ </tex-math></inline-formula>, while <inline-formula> <tex-math>$N_{Dom} gt $ </tex-math></inline-formula><inline-formula> <tex-math>$700/mu m^{2}$ </tex-math></inline-formula> ensured robustness by stabilizing the dominant FeFET path. Finally, the proposed cross-scale design-space exploration framework formulates three quantitative guidelines that map the interplay between domain density, device sizing, and search functionality, providing a solid physical foundation for reliable 2-FeFET-based TCAM design.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"952-958"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-03-27DOI: 10.1109/TDMR.2026.3697549
Mohd Ashraf Lone;Dibyadrasta Sahoo;Sanjeev Kumar Manhas
The polysilicon channel in conventional 3D NAND flash memory shows degraded subthreshold slope and low electrostatic control over the channel upon scaling gate pitch. 3D NAND with MoS2 channel material can potentially overcome these challenges, as it shows higher mobility with a channel thickness of a few atoms. In this work, using TCAD simulations calibrated to experimental data, the MoS2 material is incorporated as the channel in 3D NAND to investigate scaling performance. We demonstrate that the MoS2 channel NAND performs better, even at a scaled pitch of 20nm with 10nm gate length, exhibiting a good cell current value, subthreshold slope, and improved memory performance. We investigate neighboring cell interference by analyzing the effect of barrier lowering by side transistors on the focus cell at a gate length of 10nm. This shows the MoS2 channel NAND has a higher energy barrier than the polysilicon channel NAND due to better electrostatic gate control over the channel. We also demonstrate that the trapped charge during program operation is higher in MoS2 3D NAND at 10nm gate length, making it suitable for multi-bit operation. We analyze the retention property of the MoS2 channel NAND and observe almost similar charge loss at a scaled 20nm gate pitch compared to 50nm, indicating reliable operation with gate pitch scaling. Therefore, 20 nm gate-pitch MoS2 channel NAND, with a 9 V memory window, enables up to $3times $ higher storage density by allowing more cells to be stacked within the limited physical height of the 3D NAND stack.
传统3D NAND闪存中的多晶硅沟道在缩放栅极节距时显示出下降的亚阈值斜率和低静电控制。具有MoS2通道材料的3D NAND可以潜在地克服这些挑战，因为它在几个原子的通道厚度下显示出更高的迁移率。在这项工作中，使用校准实验数据的TCAD模拟，将MoS2材料作为3D NAND中的通道来研究缩放性能。我们证明了MoS2通道NAND性能更好，即使在20nm的缩放间距和10nm的栅极长度下，也表现出良好的电池电流值，亚阈值斜率和改进的存储性能。我们通过分析在栅极长度为10nm处，侧置晶体管降低势垒对聚焦电池的影响来研究相邻电池的干扰。这表明MoS2沟道NAND具有比多晶硅沟道NAND更高的能量势垒，这是由于沟道上更好的静电栅控制。我们还证明了在10nm栅极长度的MoS2 3D NAND中，程序操作期间捕获的电荷更高，使其适合于多比特操作。我们分析了MoS2通道NAND的保留特性，并观察到在20nm栅极间距缩放下与50nm栅极间距缩放下几乎相似的电荷损失，表明栅极间距缩放时运行可靠。因此，20nm栅距MoS2通道NAND，具有9v存储窗口，通过允许在3D NAND堆栈的有限物理高度内堆叠更多单元，可实现高达3倍的存储密度。
{"title":"3D NAND Scaling Performance Enhancement Using 2D MoS2 Channel","authors":"Mohd Ashraf Lone;Dibyadrasta Sahoo;Sanjeev Kumar Manhas","doi":"10.1109/TDMR.2026.3697549","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3697549","url":null,"abstract":"The polysilicon channel in conventional 3D NAND flash memory shows degraded subthreshold slope and low electrostatic control over the channel upon scaling gate pitch. 3D NAND with MoS<sub>2</sub> channel material can potentially overcome these challenges, as it shows higher mobility with a channel thickness of a few atoms. In this work, using TCAD simulations calibrated to experimental data, the MoS<sub>2</sub> material is incorporated as the channel in 3D NAND to investigate scaling performance. We demonstrate that the MoS<sub>2</sub> channel NAND performs better, even at a scaled pitch of 20nm with 10nm gate length, exhibiting a good cell current value, subthreshold slope, and improved memory performance. We investigate neighboring cell interference by analyzing the effect of barrier lowering by side transistors on the focus cell at a gate length of 10nm. This shows the MoS<sub>2</sub> channel NAND has a higher energy barrier than the polysilicon channel NAND due to better electrostatic gate control over the channel. We also demonstrate that the trapped charge during program operation is higher in MoS<sub>2</sub> 3D NAND at 10nm gate length, making it suitable for multi-bit operation. We analyze the retention property of the MoS<sub>2</sub> channel NAND and observe almost similar charge loss at a scaled 20nm gate pitch compared to 50nm, indicating reliable operation with gate pitch scaling. Therefore, 20 nm gate-pitch MoS<sub>2</sub> channel NAND, with a 9 V memory window, enables up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> higher storage density by allowing more cells to be stacked within the limited physical height of the 3D NAND stack.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"815-821"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a robust cross-layer protection mechanism that neutralizes both active and passive probing attacks in advanced 3D integrated circuits (3D-ICs). By leveraging the unique electromagnetic properties of nanocarbon interconnects, we establish that Multi-Layer Graphene Nanoribbons (MLGNRs) provide a critical intrinsic advantage for ultra-fast hardware security sensing at the 14 nm FinFET node. Frequency-domain analysis confirms MLGNR’s superiority, exhibiting a 3.5-fold higher $Delta $ S55 sensitivity (1.23 dB vs. 0.37 dB) for direct probe detection and a 6.5-fold stronger Near-End Crosstalk (NEXT) signature (11.19 dB vs. 1.84 dB) for indirect adjacent-line probing. In the time domain, comprehensive HSPICE simulations demonstrate that, unlike conventional probing detectors primarily demonstrated at mature planar nodes (e.g., 65 nm), which suffer from multi-cycle latency, the proposed MLGNR-based architecture achieves a direct security-response latency of 20 ps, significantly outperforming the MWCNT-based system’s 53 ps response. Crucially, in complex indirect sensing scenarios, MLGNR maintains a rapid 25 ps reaction time (at t = 105 ps), whereas MWCNT’s latency increases to 61 ps (at t = 141 ps) due to parasitic-induced signal dispersion. These findings, supported by an analysis of the fundamental RC damping and reliability limits of conventional metallic routing, establish MLGNR as the optimal material choice for designing 3D-ICs that require simultaneous high performance and sub-nanosecond threat neutralization.
本文介绍了一种鲁棒的跨层保护机制，可以中和先进3D集成电路（3D- ic）中的主动和被动探测攻击。通过利用纳米碳互连的独特电磁特性，我们确定多层石墨烯纳米带（mlgnr）为14nm FinFET节点的超快速硬件安全传感提供了关键的内在优势。频域分析证实了MLGNR的优势，在直接探测中显示出3.5倍的$Delta $ S55灵敏度（1.23 dB vs. 0.37 dB），在间接邻接线探测中显示出6.5倍强的近端串扰（NEXT）特征（11.19 dB vs. 1.84 dB）。在时域，综合HSPICE模拟表明，与主要在成熟平面节点（例如65 nm）上演示的传统探测探测器不同，该探测器存在多周期延迟，所提出的基于mlgnr的架构实现了20 ps的直接安全响应延迟，显著优于基于mwcnt的系统的53 ps响应。至关重要的是，在复杂的间接传感场景中，MLGNR保持了25 ps的快速反应时间（在t = 105 ps时），而MWCNT的延迟由于寄生诱导的信号分散而增加到61 ps（在t = 141 ps时）。这些发现，通过对传统金属布线的基本RC阻尼和可靠性限制的分析，确立了MLGNR作为设计3d - ic的最佳材料选择，同时需要高性能和亚纳秒级的威胁中和。
{"title":"Cross-Layer Protection Against Probing Attacks in 3-D Mixed-Signal ICs Using Nanocarbon Interconnects","authors":"Soheila Gharavi Hamedani;Mohammad Hossein Moaiyeri","doi":"10.1109/TDMR.2026.3711961","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3711961","url":null,"abstract":"This paper introduces a robust cross-layer protection mechanism that neutralizes both active and passive probing attacks in advanced 3D integrated circuits (3D-ICs). By leveraging the unique electromagnetic properties of nanocarbon interconnects, we establish that Multi-Layer Graphene Nanoribbons (MLGNRs) provide a critical intrinsic advantage for ultra-fast hardware security sensing at the 14 nm FinFET node. Frequency-domain analysis confirms MLGNR’s superiority, exhibiting a 3.5-fold higher <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>S<sub>55</sub> sensitivity (1.23 dB vs. 0.37 dB) for direct probe detection and a 6.5-fold stronger Near-End Crosstalk (NEXT) signature (11.19 dB vs. 1.84 dB) for indirect adjacent-line probing. In the time domain, comprehensive HSPICE simulations demonstrate that, unlike conventional probing detectors primarily demonstrated at mature planar nodes (e.g., 65 nm), which suffer from multi-cycle latency, the proposed MLGNR-based architecture achieves a direct security-response latency of 20 ps, significantly outperforming the MWCNT-based system’s 53 ps response. Crucially, in complex indirect sensing scenarios, MLGNR maintains a rapid 25 ps reaction time (at t = 105 ps), whereas MWCNT’s latency increases to 61 ps (at t = 141 ps) due to parasitic-induced signal dispersion. These findings, supported by an analysis of the fundamental RC damping and reliability limits of conventional metallic routing, establish MLGNR as the optimal material choice for designing 3D-ICs that require simultaneous high performance and sub-nanosecond threat neutralization.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1004-1015"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-08-03DOI: 10.1109/TDMR.2026.3719149
Jiesi Xing;Christopher J. Elash;Xiaotong Lu;Rita Fung;Enxia Zhang;Li Chen
Single event upset (SEU) cross-section and total ionizing dose (TID) effects were studied at the 12-nm bulk FinFET technology node. In this paper, SEU rates of flip-flop (FF) designs with different threshold voltage (VT) options in a GF 12-nm bulk FinFET technology are investigated with alpha particles, protons, and heavy ions. Irradiation results indicate that various VT options of the transistors do not have a significant impact on SEU rates of the FFs at this technology node, while FFs with HVT transistors exhibit slightly higher cross-sections. Interestingly, LVT and RVT cells exhibit opposite trends when exposed to different LET particles. SPICE and TCAD simulations have been carried out to further analyze the experimental results. In addition, the total dose effects on ring oscillators (RO) designed with inverters, two-input NAND and NOR gates are also investigated with gamma sources. PDK-based SPICE simulations and qualitative TCAD simulations are used to support the interpretation of the measured VT-dependent SEU trends. In addition, total-ionizing-dose effects on ring oscillators designed with inverters, two-input NAND gates, and two-input NOR gates are investigated using Co-60 gamma irradiation. The results show negligible RO frequency degradation and only a small chip-current increase up to 300 krad, indicating strong circuit-level TID tolerance for the implemented two-fin standard-cell RO structures.
{"title":"Analysis of Threshold Voltage Options on Single-Event Error Rates and TID Effects in 12-nm FinFET D Flip-Flops and Ring Oscillators","authors":"Jiesi Xing;Christopher J. Elash;Xiaotong Lu;Rita Fung;Enxia Zhang;Li Chen","doi":"10.1109/TDMR.2026.3719149","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3719149","url":null,"abstract":"Single event upset (SEU) cross-section and total ionizing dose (TID) effects were studied at the 12-nm bulk FinFET technology node. In this paper, SEU rates of flip-flop (FF) designs with different threshold voltage (V<sub>T</sub>) options in a GF 12-nm bulk FinFET technology are investigated with alpha particles, protons, and heavy ions. Irradiation results indicate that various V<sub>T</sub> options of the transistors do not have a significant impact on SEU rates of the FFs at this technology node, while FFs with HVT transistors exhibit slightly higher cross-sections. Interestingly, LVT and RVT cells exhibit opposite trends when exposed to different LET particles. SPICE and TCAD simulations have been carried out to further analyze the experimental results. In addition, the total dose effects on ring oscillators (RO) designed with inverters, two-input NAND and NOR gates are also investigated with gamma sources. PDK-based SPICE simulations and qualitative TCAD simulations are used to support the interpretation of the measured V<sub>T</sub>-dependent SEU trends. In addition, total-ionizing-dose effects on ring oscillators designed with inverters, two-input NAND gates, and two-input NOR gates are investigated using Co-60 gamma irradiation. The results show negligible RO frequency degradation and only a small chip-current increase up to 300 krad, indicating strong circuit-level TID tolerance for the implemented two-fin standard-cell RO structures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1016-1024"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents the design and reliability evaluation of an underlap-engineered electrically reconfigurable tunnel field-effect transistor (ULE-ER-TFET) intended for ultra-low-power and high-frequency nanoelectronic applications. The proposed architecture integrates a drain-side gate-underlap with selective HfO2 dielectric engineering near the source–channel junction to simultaneously suppress ambipolar conduction and enhance tunneling efficiency. Comparative investigation with a conventional electrically reconfigurable TFET demonstrates substantial improvement in electrostatic integrity and switching behavior. The proposed ULE-ER-TFET achieves an ON-state current of $3.14 times 10^{-5}$ A/$mu $ m, an $I_{mathrm {ON}}/I_{mathrm {OFF}}$ ratio of $7.05 times 10^{12}$ , a threshold voltage of 0.452 V, and a point subthreshold swing of 13.78 mV/dec. Reliability analysis under positive and negative interface trap charges of $pm 1 times 10^{12}$ cm−2 reveals significantly reduced degradation in DC and analog/RF performance metrics compared with the conventional structure. The variation in ON-current and $I_{mathrm {ON}}/I_{mathrm {OFF}}$ ratio remains within nearly ±2%, confirming strong tolerance against trap-induced fluctuations. Furthermore, temperature-dependent assessment from 250 K to 450 K indicates stable ON-state conduction and controlled leakage characteristics under elevated thermal conditions. The proposed device also exhibits improved transconductance, cutoff frequency, gain-bandwidth product, and carrier transit characteristics with minimal sensitivity to interface traps and temperature variations. These results establish the ULE-ER-TFET as a promising candidate for future reliable low-power integrated circuits and RF systems.
{"title":"Design and Reliability Assessment of a Reconfigurable Tunneling Device for Ultra Low-Power Applications","authors":"Bandi Venkata Chandan;Kaushal Kumar Nigam;Adil Tanveer","doi":"10.1109/TDMR.2026.3708312","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3708312","url":null,"abstract":"This work presents the design and reliability evaluation of an underlap-engineered electrically reconfigurable tunnel field-effect transistor (ULE-ER-TFET) intended for ultra-low-power and high-frequency nanoelectronic applications. The proposed architecture integrates a drain-side gate-underlap with selective HfO<sub>2</sub> dielectric engineering near the source–channel junction to simultaneously suppress ambipolar conduction and enhance tunneling efficiency. Comparative investigation with a conventional electrically reconfigurable TFET demonstrates substantial improvement in electrostatic integrity and switching behavior. The proposed ULE-ER-TFET achieves an ON-state current of <inline-formula> <tex-math>$3.14 times 10^{-5}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, an <inline-formula> <tex-math>$I_{mathrm {ON}}/I_{mathrm {OFF}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$7.05 times 10^{12}$ </tex-math></inline-formula>, a threshold voltage of 0.452 V, and a point subthreshold swing of 13.78 mV/dec. Reliability analysis under positive and negative interface trap charges of <inline-formula> <tex-math>$pm 1 times 10^{12}$ </tex-math></inline-formula> cm<sup>−2</sup> reveals significantly reduced degradation in DC and analog/RF performance metrics compared with the conventional structure. The variation in ON-current and <inline-formula> <tex-math>$I_{mathrm {ON}}/I_{mathrm {OFF}}$ </tex-math></inline-formula> ratio remains within nearly ±2%, confirming strong tolerance against trap-induced fluctuations. Furthermore, temperature-dependent assessment from 250 K to 450 K indicates stable ON-state conduction and controlled leakage characteristics under elevated thermal conditions. The proposed device also exhibits improved transconductance, cutoff frequency, gain-bandwidth product, and carrier transit characteristics with minimal sensitivity to interface traps and temperature variations. These results establish the ULE-ER-TFET as a promising candidate for future reliable low-power integrated circuits and RF systems.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"839-848"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-08-13DOI: 10.1109/TDMR.2026.3723461
Antony David;Ankush Bag;Rahul Kumar
In recent times, there has been an immense amount of interest in the utilization of gallium oxide (<italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula>) in power electronics because of the excellent figure of merit (FOM) values it exhibits, mostly as a consequence of its wide bandgap of almost 5 <italic>eV</i>. Many different <italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula>-based field-effect transistors (FETs) have been realized, and a number of devices have also been proposed in the literature. Among these devices, high electron mobility transistors (HEMTs) are particularly advantageous in realizing the high-power RF capabilities of <italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula>, as they typically exhibit higher values of sheet carrier density (<inline-formula> <tex-math>$n_{s}$ </tex-math></inline-formula>) and effective mobility (<inline-formula> <tex-math>$mu _{eff}$ </tex-math></inline-formula>). Of the proposed structures, the <italic>AlN/</i><inline-formula> <tex-math>$beta $ </tex-math></inline-formula><italic>-Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula> polar HEMT is one of the most promising, with simulations indicating <inline-formula> <tex-math>$n_{s}$ </tex-math></inline-formula> of the order <inline-formula> <tex-math>$10^{13}$ </tex-math></inline-formula> <italic>cm<sup>−2</sup></i> and excellent RF parameter values. In this work, we have performed a proof-of-concept simulation of an <italic>AlN/</i><inline-formula> <tex-math>$beta -$ </tex-math></inline-formula><italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula> polar HEMT, having gate length (<inline-formula> <tex-math>$L_{G}$ </tex-math></inline-formula>) of 50 <italic>nm</i> to maximize RF performance, with the aim of benchmarking this device’s performance and exploring its design space. We note poor subthreshold characteristics and aim to improve subthreshold slope (<italic>SS</i>), ON-OFF current ratio (<inline-formula> <tex-math>$I_{ON}/I_{OFF}$ </tex-math></inline-formula>) and drain-induced barrier lowering (<italic>DIBL</i>) coefficient without significantly compromising the RF performance. To this end, we implement an <italic>(Al</i><inline-formula> <tex-math>${}_{x}$ </tex-math></inline-formula><italic>Ga</i><inline-formula> <tex-math>${}_{1-x})_{2}O_{3}$ </tex-math></inline-formula> back barrier layer to improve carrier confinement and mitigate OFF-state leakage current. <italic>SS</i> and <italic>DIBL</i> values of 122 <italic>mV/dec</i> and 87 <italic>mV/V</i> were obtained for an optimized structure having the back barrier, with an ON-OFF ratio (<inline-formula> <tex-math>$I_{ON}/I_{OFF}$ </tex-math></inline-formula>) of the order <inline-formula> <tex-math>$10^{6}- 10^{7}$ </tex-math></inline-formula>. While the implementation of the back barrier initially produced improvement in the values of cutoff
近年来，人们对氧化镓（Ga ${}_{2}O_{3}$）在电力电子领域的应用产生了极大的兴趣，因为它具有优异的性能值（FOM），这主要是由于它具有近5 eV的宽带隙。许多不同的基于Ga ${}_{2}O_{3}$的场效应晶体管（fet）已经实现，并且在文献中也提出了许多器件。在这些器件中，高电子迁移率晶体管（hemt）在实现Ga ${}_{2}O_{3}$的高功率射频能力方面尤其具有优势，因为它们通常具有更高的片载流子密度（$n_{s}$）和有效迁移率（$mu _{eff}$）。在所提出的结构中，AlN/ $beta $ -Ga ${}_{2}O_{3}$极性HEMT是最有前途的结构之一，模拟表明$n_{s}$的阶为$10^{13}$ cm−2，并且具有良好的RF参数值。在这项工作中，我们对AlN/ $beta -$ Ga ${}_{2}O_{3}$极性HEMT进行了概念验证模拟，其栅极长度（$L_{G}$）为50 nm，以最大限度地提高射频性能，目的是对该器件的性能进行基准测试并探索其设计空间。我们注意到较差的亚阈值特性，并旨在改善亚阈值斜率（SS），通断电流比（$I_{ON}/I_{OFF}$）和漏极诱导势垒降低（DIBL）系数，而不会显著影响射频性能。为此，我们实现了（Al ${}_{x}$ Ga ${}_{1-x})_{2}O_{3}$）后阻挡层，以改善载流子约束和减轻off状态泄漏电流。优化后的结构具有后屏障，开关比（$I_{ON}/I_{OFF}$）为$10^{6}- 10^{7}$级，SS值为122 mV/dec， DIBL值为87 mV/V。虽然后阻挡的实现最初提高了截止频率（$f_{t}$）和最大振荡频率（$f_{max}$）的值，但具有最佳亚阈值性能的优化结构的$f_{t}$和$f_{max}$值分别较低，分别为66.3 GHz和74.8 GHz，尽管这些值仍然优于实验实现的基于Ga ${}_{2}O_{3}$的平面fet的最高值。这些结果证明了开发AlN/ $beta -$ Ga ${}_{2}O_{3}$极性hemt作为可靠的高性能射频器件的兴趣，而改进的亚阈值特性也增加了这些器件在生物传感器中的适用性。
{"title":"Mitigation of Short-Channel Effects in Ultra-Scaled AlN/β−Ga2O3 High Electron Mobility Transistors","authors":"Antony David;Ankush Bag;Rahul Kumar","doi":"10.1109/TDMR.2026.3723461","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3723461","url":null,"abstract":"In recent times, there has been an immense amount of interest in the utilization of gallium oxide (<italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula>) in power electronics because of the excellent figure of merit (FOM) values it exhibits, mostly as a consequence of its wide bandgap of almost 5 <italic>eV</i>. Many different <italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula>-based field-effect transistors (FETs) have been realized, and a number of devices have also been proposed in the literature. Among these devices, high electron mobility transistors (HEMTs) are particularly advantageous in realizing the high-power RF capabilities of <italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula>, as they typically exhibit higher values of sheet carrier density (<inline-formula> <tex-math>$n_{s}$ </tex-math></inline-formula>) and effective mobility (<inline-formula> <tex-math>$mu _{eff}$ </tex-math></inline-formula>). Of the proposed structures, the <italic>AlN/</i><inline-formula> <tex-math>$beta $ </tex-math></inline-formula><italic>-Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula> polar HEMT is one of the most promising, with simulations indicating <inline-formula> <tex-math>$n_{s}$ </tex-math></inline-formula> of the order <inline-formula> <tex-math>$10^{13}$ </tex-math></inline-formula> <italic>cm<sup>−2</sup></i> and excellent RF parameter values. In this work, we have performed a proof-of-concept simulation of an <italic>AlN/</i><inline-formula> <tex-math>$beta -$ </tex-math></inline-formula><italic>Ga</i><inline-formula> <tex-math>${}_{2}O_{3}$ </tex-math></inline-formula> polar HEMT, having gate length (<inline-formula> <tex-math>$L_{G}$ </tex-math></inline-formula>) of 50 <italic>nm</i> to maximize RF performance, with the aim of benchmarking this device’s performance and exploring its design space. We note poor subthreshold characteristics and aim to improve subthreshold slope (<italic>SS</i>), ON-OFF current ratio (<inline-formula> <tex-math>$I_{ON}/I_{OFF}$ </tex-math></inline-formula>) and drain-induced barrier lowering (<italic>DIBL</i>) coefficient without significantly compromising the RF performance. To this end, we implement an <italic>(Al</i><inline-formula> <tex-math>${}_{x}$ </tex-math></inline-formula><italic>Ga</i><inline-formula> <tex-math>${}_{1-x})_{2}O_{3}$ </tex-math></inline-formula> back barrier layer to improve carrier confinement and mitigate OFF-state leakage current. <italic>SS</i> and <italic>DIBL</i> values of 122 <italic>mV/dec</i> and 87 <italic>mV/V</i> were obtained for an optimized structure having the back barrier, with an ON-OFF ratio (<inline-formula> <tex-math>$I_{ON}/I_{OFF}$ </tex-math></inline-formula>) of the order <inline-formula> <tex-math>$10^{6}- 10^{7}$ </tex-math></inline-formula>. While the implementation of the back barrier initially produced improvement in the values of cutoff","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"1051-1058"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The incidence of alpha ($alpha $ ) particles on a device induces single-event transients (SET), leading to serious reliability concerns related to device degradation and failure. Exposure to high-energy $alpha $ -radiation can therefore alter device performance, particularly in highly confined device architectures (e.g., Nanosheet FETs), where the channels are extremely sensitive to charge deposition. In this work, we present a comprehensive investigation of $alpha $ -particle-induced reliability assessment of Nanosheet FET (NSFET) using well-calibrated TCAD models. Upon striking, high-energy $alpha $ particles generate electron-hole pairs (EHPs), which alter the device’s resistivity/conductivity. The magnitude of the induced transients increases with linear energy transfer (LET), while the conductivity degradation is mainly attributed to the hole population generated during EHP formation. In our TCAD experiment, we varied the strike energy from 1 to 5 MeV, the strike time from 10 ps to $2.5~mu $ s, and the strike angle from 0° to 60°. Further, the strike locations were varied to assess resistivity modulation in all possible scenarios. In the worst-case scenario, the maximum current of $1.86~mu $ A is observed at a strike interval of 10 ps in the drain extension. Moreover, we develop a resistivity model to capture the $alpha $ -radiation-induced resistivity modulation using the transmission line method (TLM). The model predictions closely match the simulation data, confirming the model’s validity. Thus, the proposed design guidelines and model provide an efficient means of assessing the effects of alpha radiation on the resilience of NSFETs.
{"title":"Reliability-Assisted Electro-Physical Modeling of Radiation-Induced Resistance Fluctuation in Nanosheet FET","authors":"Khushi Jain;Sandeep Kumar;Sunil Rathore;Shashank Banchhor;Navjeet Bagga","doi":"10.1109/TDMR.2026.3713056","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3713056","url":null,"abstract":"The incidence of alpha (<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>) particles on a device induces single-event transients (SET), leading to serious reliability concerns related to device degradation and failure. Exposure to high-energy <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-radiation can therefore alter device performance, particularly in highly confined device architectures (e.g., Nanosheet FETs), where the channels are extremely sensitive to charge deposition. In this work, we present a comprehensive investigation of <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-particle-induced reliability assessment of Nanosheet FET (NSFET) using well-calibrated TCAD models. Upon striking, high-energy <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula> particles generate electron-hole pairs (EHPs), which alter the device’s resistivity/conductivity. The magnitude of the induced transients increases with linear energy transfer (LET), while the conductivity degradation is mainly attributed to the hole population generated during EHP formation. In our TCAD experiment, we varied the strike energy from 1 to 5 MeV, the strike time from 10 ps to <inline-formula> <tex-math>$2.5~mu $ </tex-math></inline-formula>s, and the strike angle from 0° to 60°. Further, the strike locations were varied to assess resistivity modulation in all possible scenarios. In the worst-case scenario, the maximum current of <inline-formula> <tex-math>$1.86~mu $ </tex-math></inline-formula>A is observed at a strike interval of 10 ps in the drain extension. Moreover, we develop a resistivity model to capture the <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-radiation-induced resistivity modulation using the transmission line method (TLM). The model predictions closely match the simulation data, confirming the model’s validity. Thus, the proposed design guidelines and model provide an efficient means of assessing the effects of alpha radiation on the resilience of NSFETs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"832-838"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-18DOI: 10.1109/TDMR.2026.3704933
Giuseppe Esposito;Enrico Magliano;Nicola Scarano;Tamer Ahmed Eltaras;Juan David Guerrero Balaguera;Luca Mannella;Josie E. Rodriguez Condia;Annachiara Ruospo;Stefano Di Carlo;Marco Levorato;Alessandro Savino;Matteo Sonza Reorda
Split Computing (SC) has emerged as an effective strategy for deploying Deep Neural Networks (DNNs) on edge and Internet of Things (IoT) platforms. By partitioning inference between constrained edge devices and powerful cloud servers. However, the intermediate feature representations exchanged between the Head and Tail models can be corrupted either by deliberate adversarial perturbations, obtained by crafting the input to the Head, or by unintended hardware faults affecting the computations in the Head. Both phenomena manifest as distortions in the feature maps, but they have distinct causes and require different responses. Therefore, detecting and classifying such anomalies is crucial for dependable and secure SC-based inference. This work formulates feature-map monitoring in SC as a three-class classification problem. A lightweight classifier is trained to distinguish among clean, fault-induced, and attack-induced feature maps at the split boundary. It thereby determines whether corruption is present and identifies its most likely source, enabling the detection and classification of threats. We conduct a detailed analysis of how hardware faults and adversarially crafted inputs in the Head affect the distribution of entries in the intermediate feature map. Performing a design-space exploration across multiple SC configurations. Experiments on SC ResNet-50 show that the SC configuration, which involves intermediate 3-channel feature maps, achieves an F1-score of 97.84% on the clean/adversarial/faulty classification task, with a 31.07% computational overhead relative to baseline SC inference. These results indicate that three-class feature-map classification is a practical and effective front-end for cause-aware analysis in SC deployments.
{"title":"AI-Based Detection and Classification of Adversarial and Fault-Induced Threats in Split Computing","authors":"Giuseppe Esposito;Enrico Magliano;Nicola Scarano;Tamer Ahmed Eltaras;Juan David Guerrero Balaguera;Luca Mannella;Josie E. Rodriguez Condia;Annachiara Ruospo;Stefano Di Carlo;Marco Levorato;Alessandro Savino;Matteo Sonza Reorda","doi":"10.1109/TDMR.2026.3704933","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3704933","url":null,"abstract":"Split Computing (SC) has emerged as an effective strategy for deploying Deep Neural Networks (DNNs) on edge and Internet of Things (IoT) platforms. By partitioning inference between constrained edge devices and powerful cloud servers. However, the intermediate feature representations exchanged between the Head and Tail models can be corrupted either by <italic>deliberate</i> adversarial perturbations, obtained by crafting the input to the Head, or by <italic>unintended</i> hardware faults affecting the computations in the Head. Both phenomena manifest as distortions in the feature maps, but they have distinct causes and require different responses. Therefore, detecting and classifying such anomalies is crucial for dependable and secure SC-based inference. This work formulates feature-map monitoring in SC as a <italic>three-class classification</i> problem. A lightweight classifier is trained to distinguish among <italic>clean</i>, <italic>fault-induced</i>, and <italic>attack-induced</i> feature maps at the split boundary. It thereby determines whether corruption is present and identifies its most likely source, enabling the detection and classification of threats. We conduct a detailed analysis of how hardware faults and adversarially crafted inputs in the Head affect the distribution of entries in the intermediate feature map. Performing a design-space exploration across multiple SC configurations. Experiments on SC ResNet-50 show that the SC configuration, which involves intermediate 3-channel feature maps, achieves an F1-score of 97.84% on the clean/adversarial/faulty classification task, with a 31.07% computational overhead relative to baseline SC inference. These results indicate that three-class feature-map classification is a practical and effective front-end for cause-aware analysis in SC deployments.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"780-793"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11570223","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-07-17DOI: 10.1109/TDMR.2026.3714196
Yuncong Li;Zhizhe Wang;Shichen Su;Menglin Yan;Yongle Zhong;Yuansheng Li;Liang He;Jun Luo
In this work, the parameters degradation and failure mechanisms of 1200V double-trench SiC MOSFETs under both single and repetitive surge current stresses has been systematically investigated. Experiments have been conducted at gate-source voltages (V${}_{mathrm {GS}}$ ) of 0 V, –5 V, and –10 V. The critical single-pulse surge current has been first determined using incremental single-surge stress until catastrophic failure. Repetitive surge tests have been then conducted at fixed current amplitudes corresponding to 90% and 60% of this critical value to evaluate cumulative, non-catastrophic degradation. Results demonstrate that the VGS significantly influences the surge capability of the device. As VGS becomes more negative, the threshold voltage shift increases significantly in the negative direction. Under single surge stress, the device at V${}_{mathrm {GS}} =0$ V exhibits a surge tolerance approximately 45.45% lower than that at V${}_{mathrm {GS}} =~-5$ V and −10 V due to stronger channel-assisted leakage conduction under the hybrid conduction condition. Under repetitive stress, the fewest surge cycles are observed for the device at V${}_{mathrm {GS}} =0$ V, the same as single stress. The increase in surge cycles with VGS rising from −10 V to −5 V is attributed to the increase of the degree for channel opening, allowing more surge current flow through channel. It is revealed that device failures under single surge stress are primarily caused by metal migration and active region breakdown, leading to three-terminal short circuit. Variations in failure mechanisms are observed under different repetitive surge conditions. Localized interlayer dielectric (ILD) and metallization damage near the termination region is associated with degradation of the drain–source blocking capability at the 90% stress level, while the combined effect of gate oxide fracture and ILD damage contributes to leakage paths at the 60% stress level. These findings provide valuable insights for the reliability optimization and application of double-trench SiC MOSFETs in high-power systems.
{"title":"Investigation of Parameters Degradation and Failure Mechanisms for 1200-V Double-Trench SiC MOSFETs Under Single and Repetitive Surge Current Stress","authors":"Yuncong Li;Zhizhe Wang;Shichen Su;Menglin Yan;Yongle Zhong;Yuansheng Li;Liang He;Jun Luo","doi":"10.1109/TDMR.2026.3714196","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3714196","url":null,"abstract":"In this work, the parameters degradation and failure mechanisms of 1200V double-trench SiC MOSFETs under both single and repetitive surge current stresses has been systematically investigated. Experiments have been conducted at gate-source voltages (V<inline-formula> <tex-math>${}_{mathrm {GS}}$ </tex-math></inline-formula>) of 0 V, –5 V, and –10 V. The critical single-pulse surge current has been first determined using incremental single-surge stress until catastrophic failure. Repetitive surge tests have been then conducted at fixed current amplitudes corresponding to 90% and 60% of this critical value to evaluate cumulative, non-catastrophic degradation. Results demonstrate that the V<sub>GS</sub> significantly influences the surge capability of the device. As V<sub>GS</sub> becomes more negative, the threshold voltage shift increases significantly in the negative direction. Under single surge stress, the device at V<inline-formula> <tex-math>${}_{mathrm {GS}} =0$ </tex-math></inline-formula> V exhibits a surge tolerance approximately 45.45% lower than that at V<inline-formula> <tex-math>${}_{mathrm {GS}} =~-5$ </tex-math></inline-formula> V and −10 V due to stronger channel-assisted leakage conduction under the hybrid conduction condition. Under repetitive stress, the fewest surge cycles are observed for the device at V<inline-formula> <tex-math>${}_{mathrm {GS}} =0$ </tex-math></inline-formula> V, the same as single stress. The increase in surge cycles with V<sub>GS</sub> rising from −10 V to −5 V is attributed to the increase of the degree for channel opening, allowing more surge current flow through channel. It is revealed that device failures under single surge stress are primarily caused by metal migration and active region breakdown, leading to three-terminal short circuit. Variations in failure mechanisms are observed under different repetitive surge conditions. Localized interlayer dielectric (ILD) and metallization damage near the termination region is associated with degradation of the drain–source blocking capability at the 90% stress level, while the combined effect of gate oxide fracture and ILD damage contributes to leakage paths at the 60% stress level. These findings provide valuable insights for the reliability optimization and application of double-trench SiC MOSFETs in high-power systems.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"967-976"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-29DOI: 10.1109/TDMR.2026.3708182
B. Veryser;F. Stampfl;J. M. Gonzalez-Medina;C. Godfrin;B. Raes;K. De Greve;R. Loo;Y. Shimura;L. Panarella;A. Grill;M. Houssa;S. E. Tyaginov
Si/SiGe heterostructures are a promising platform for electron spin based quantum computers. In this work, we show that the dielectric trapping of these devices can be studied with a phenomenological approach based on employment of effective charges at channel interfaces. We consider a device as consisting of two independent channels: one in the Si quantum well and another one in the Si capping layer. For each channel we use compact models to extract the respective characteristics including the threshold voltage, gate oxide capacitance, and channel mobility. By employing these parameters in our device simulator, we can model the hysteretic capacitance-voltage and current-voltage characteristics at cryogenic temperatures. Within this methodology, we extract a mobility value of both the Si quantum well and the interface channel and correlate them with defect density and barrier thickness. Next, we evaluate the interface state energy distribution, which shows a strong peak around 0.2 eV below the conduction band minimum and a peak value of 4 × 1013 cm−2eV−1. Our interface state energy distribution profiles are in good agreement with those reported in the literature, which supports our hypothesis that the hysteresis is driven by interface traps.
{"title":"Understanding and Modeling the Impact of Defects on Electrical Characteristics of Si/SiGe Heterostructures at Cryogenic temperatures","authors":"B. Veryser;F. Stampfl;J. M. Gonzalez-Medina;C. Godfrin;B. Raes;K. De Greve;R. Loo;Y. Shimura;L. Panarella;A. Grill;M. Houssa;S. E. Tyaginov","doi":"10.1109/TDMR.2026.3708182","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3708182","url":null,"abstract":"Si/SiGe heterostructures are a promising platform for electron spin based quantum computers. In this work, we show that the dielectric trapping of these devices can be studied with a phenomenological approach based on employment of effective charges at channel interfaces. We consider a device as consisting of two independent channels: one in the Si quantum well and another one in the Si capping layer. For each channel we use compact models to extract the respective characteristics including the threshold voltage, gate oxide capacitance, and channel mobility. By employing these parameters in our device simulator, we can model the hysteretic capacitance-voltage and current-voltage characteristics at cryogenic temperatures. Within this methodology, we extract a mobility value of both the Si quantum well and the interface channel and correlate them with defect density and barrier thickness. Next, we evaluate the interface state energy distribution, which shows a strong peak around 0.2 eV below the conduction band minimum and a peak value of 4 × 10<sup>13</sup> cm<sup>−2</sup>eV<sup>−1</sup>. Our interface state energy distribution profiles are in good agreement with those reported in the literature, which supports our hypothesis that the hysteresis is driven by interface traps.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"689-696"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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