This article presents a method to enhance the error correction capability of binary block error-correcting codes used in resistive memories. It relies on a more effective utilization of bits that are more susceptible to erroneous sensing. Once identified upon receiving an error decoding alert, these weak bits are flipped, and the decoding process is resumed with better chances of success. This works with an error-only decoder unable to handle any kind of soft information by itself. It is shown that the uncorrectable bit error rate can be reduced by up to an additional order of magnitude if the weak-bit information is leveraged not only in the presence of detectable uncorrectable errors but also in the case of certain conventionally undetectable errors. The same applies to the uncorrectable and undetectable bit error rate. These improvements can be achieved without any storage overhead and with limited latency and logic costs.
{"title":"Improving Error Correction With Weak-bit Information in Resistive Memories","authors":"Valentin Gherman;Giuseppe Piccolboni;Zeev Freidin;Matan Guttman;Amir Regev;Gabriel Molas;Ishai Naveh;Bastien Giraud;Antoine Hebert;Ilan Sever","doi":"10.1109/TDMR.2026.3683720","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3683720","url":null,"abstract":"This article presents a method to enhance the error correction capability of binary block error-correcting codes used in resistive memories. It relies on a more effective utilization of bits that are more susceptible to erroneous sensing. Once identified upon receiving an error decoding alert, these <italic>weak bits</i> are flipped, and the decoding process is resumed with better chances of success. This works with an error-only decoder unable to handle any kind of <italic>soft</i> information by itself. It is shown that the uncorrectable bit error rate can be reduced by up to an additional order of magnitude if the weak-bit information is leveraged not only in the presence of detectable uncorrectable errors but also in the case of certain <italic>conventionally</i> undetectable errors. The same applies to the uncorrectable and undetectable bit error rate. These improvements can be achieved without any storage overhead and with limited latency and logic costs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"743-751"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hydrogen passivation and incorporation in active-layer strongly affect the electrical performance of devices; however, the behavior of residual hydrogen during bottom-gate insulator (BGI) fabrication remains unclear. In this study, the electrical properties and reliability performance of dual-gate InGaZnO (IGZO) thin-film transistors (TFTs) synthesized using different BGI fabrication processes were thoroughly examined. Variations in the chemical species ratio and deposition power during chemical vapor deposition greatly affected the gate insulator composition, particularly at the interface between the active layer and BGI. The electrical behaviors of the top-gate and bottom-gate device configurations were analyzed using the transmission line method and persistent photoconductivity measurements, which revealed differences in device performance that were attributed to changes in the gate insulator composition. Hydrogen diffusion within the gate insulator caused the passivation of defects and a reduction in electron trapping sites. This process also altered the composition of the active layer, as confirmed by the electrical performance and material characterization results. X-ray photoelectron spectroscopy was used to further compare the hydrogen concentrations at the interface. Secondary-ion mass spectrometry depth profiling revealed differences in the hydrogen content, which correlated with the random-telegraph signal (RTS) noise measurements. Subsequently, the relationship between the RTS noise and silanol groups at the interface was elucidated, providing more detailed insight into the role of noise measurements in IGZO TFT applications. Finally, a physical model was proposed to explain the degradation trends. This study shows that the initial electrical properties and reliabilities are influenced by the hydrogen-induced passivation effect during different BGI-fabrication processes.
{"title":"Influence of Gate Insulator Modulation on the Electrical and Material Properties of Dual-Gate InGaZnO Thin-Film Transistors","authors":"Ya-Ting Chien;Yu-An Chen;Bo-Shen Huang;Po-Yu Yen;Tzu-Hsuan Juan;Ting-Chang Chang;Tsung-Ming Tsai;Yang-Shun Fan;Chen-Shuo Huang;Chih-Hung Tsai","doi":"10.1109/TDMR.2026.3712375","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3712375","url":null,"abstract":"Hydrogen passivation and incorporation in active-layer strongly affect the electrical performance of devices; however, the behavior of residual hydrogen during bottom-gate insulator (BGI) fabrication remains unclear. In this study, the electrical properties and reliability performance of dual-gate InGaZnO (IGZO) thin-film transistors (TFTs) synthesized using different BGI fabrication processes were thoroughly examined. Variations in the chemical species ratio and deposition power during chemical vapor deposition greatly affected the gate insulator composition, particularly at the interface between the active layer and BGI. The electrical behaviors of the top-gate and bottom-gate device configurations were analyzed using the transmission line method and persistent photoconductivity measurements, which revealed differences in device performance that were attributed to changes in the gate insulator composition. Hydrogen diffusion within the gate insulator caused the passivation of defects and a reduction in electron trapping sites. This process also altered the composition of the active layer, as confirmed by the electrical performance and material characterization results. X-ray photoelectron spectroscopy was used to further compare the hydrogen concentrations at the interface. Secondary-ion mass spectrometry depth profiling revealed differences in the hydrogen content, which correlated with the random-telegraph signal (RTS) noise measurements. Subsequently, the relationship between the RTS noise and silanol groups at the interface was elucidated, providing more detailed insight into the role of noise measurements in IGZO TFT applications. Finally, a physical model was proposed to explain the degradation trends. This study shows that the initial electrical properties and reliabilities are influenced by the hydrogen-induced passivation effect during different BGI-fabrication processes.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"880-887"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Testing advanced memories is critical for ensuring SoC quality, especially as smaller transistors increase manufacturing defects occurrence, making traditional SRAM functional testing insufficient. To address this issue, a novel structural testing approach based on the Cell-Aware test methodology has been proposed. Structural test patterns are generated by an Automatic Test Pattern Generator (ATPG) using analog CA models, which are derived from exhaustive analog simulations of SRAM primary blocks. However, generating these CA models through analog simulations is both time-consuming and technology-dependent. To overcome this limitation, the TrUnDeL methodology was developed to accelerate CA model generation by combining switch-level graph-based analysis with analog simulations. In this work, we further adapt TrUnDeL to generate CA models solely through switch-level graph-based simulations, completely eliminating the need for analog simulations. The resulting TrUnDeL CA models are then used by the ATPG to create structural test patterns. Through a validation flow, we demonstrate that these patterns, generated without any analog simulations, achieve nearly the same fault coverage as those produced using exhaustive analog simulations in an SRAM case study. Furthermore, the CA model generation time is drastically reduced from one hour to just fifteen seconds for the same case.
{"title":"Graph-Based Efficient Generation of Cell-Aware Models for Structural SRAM Testing","authors":"Gianmarco Mongelli;Dorian Ronga;Eric Faehn;Patrick Girard;Arnaud Virazel","doi":"10.1109/TDMR.2026.3696162","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3696162","url":null,"abstract":"Testing advanced memories is critical for ensuring SoC quality, especially as smaller transistors increase manufacturing defects occurrence, making traditional SRAM functional testing insufficient. To address this issue, a novel structural testing approach based on the Cell-Aware test methodology has been proposed. Structural test patterns are generated by an Automatic Test Pattern Generator (ATPG) using analog CA models, which are derived from exhaustive analog simulations of SRAM primary blocks. However, generating these CA models through analog simulations is both time-consuming and technology-dependent. To overcome this limitation, the TrUnDeL methodology was developed to accelerate CA model generation by combining switch-level graph-based analysis with analog simulations. In this work, we further adapt TrUnDeL to generate CA models solely through switch-level graph-based simulations, completely eliminating the need for analog simulations. The resulting TrUnDeL CA models are then used by the ATPG to create structural test patterns. Through a validation flow, we demonstrate that these patterns, generated without any analog simulations, achieve nearly the same fault coverage as those produced using exhaustive analog simulations in an SRAM case study. Furthermore, the CA model generation time is drastically reduced from one hour to just fifteen seconds for the same case.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"722-732"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-08DOI: 10.1109/TDMR.2026.3700961
Paolo La Torraca;Khushabu Santosh Agrawal;Adam Austin Gruszecki;Joy Roy;Robert Milo Wallace;Paul Hurley;Chadwin Delin Young;Karim Cherkaoui
Electrically active defects in $beta $ -Ga2O3/HfO2/Cr MOS stacks, both non-annealed and forming gas (FG)-annealed, are investigated using a combination of electrical characterization and physics-based simulations. The defects’ space–energy distributions are profiled by using capacitance–voltage (CV) and conductance–voltage (GV) measurements. The comparison of the extracted energy levels with density functional theory (DFT) results in the identification of oxygen vacancies (VO) and intrinsic trapping sites in the HfO2 layer, both of which are potential VOs precursor sites. Breakdown simulations predict that FG-annealed gate stacks, although exhibiting a larger initial density of precursor sites, achieve longer operational lifetimes. This result is explained by the carrier-injection (CI) model of the dielectric breakdown.
{"title":"Defect Profiling and Dielectric Breakdown Projections of the β-Ga2O3/HfO2 MOS System","authors":"Paolo La Torraca;Khushabu Santosh Agrawal;Adam Austin Gruszecki;Joy Roy;Robert Milo Wallace;Paul Hurley;Chadwin Delin Young;Karim Cherkaoui","doi":"10.1109/TDMR.2026.3700961","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3700961","url":null,"abstract":"Electrically active defects in <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/Cr MOS stacks, both non-annealed and forming gas (FG)-annealed, are investigated using a combination of electrical characterization and physics-based simulations. The defects’ space–energy distributions are profiled by using capacitance–voltage (CV) and conductance–voltage (GV) measurements. The comparison of the extracted energy levels with density functional theory (DFT) results in the identification of oxygen vacancies (V<sub>O</sub>) and intrinsic trapping sites in the HfO<sub>2</sub> layer, both of which are potential V<sub>O</sub>s precursor sites. Breakdown simulations predict that FG-annealed gate stacks, although exhibiting a larger initial density of precursor sites, achieve longer operational lifetimes. This result is explained by the carrier-injection (CI) model of the dielectric breakdown.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"663-670"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11554083","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We systematically explore the design space of ferroelectric hafnium–zirconium oxide (H0.5Z0.5O or HZO) heterostructures for reliable high-temperature operation. HZO films are deposited using thermal and plasma-enhanced atomic layer deposition (Th-ALD and PE-ALD) on tungsten (W) and titanium nitride (TiN) bottom electrodes (BE), while maintaining identical top electrodes. We demonstrate that PE-ALD HZO capacitors integrated with W BE exhibit wake-up-free switching up to $125~^{circ } $ C, along with significantly improved endurance compared to Th-ALD HZO/W devices across a wide temperature range (85–$125~^{circ } $ C). By decoupling the contributions of the plasma-deposited HZO film and the oxidized bottom interface inherently formed during PE-ALD, we identify the oxidized W interfacial layer (WOx) as the primary factor governing endurance enhancement and wake-up suppression at elevated temperatures, while the PE-ALD HZO film provides secondary benefits in reducing wake-up. In contrast, PE-ALD HZO capacitors fabricated on TiN BE show no substantial improvement in wake-up behavior or endurance relative to Th-ALD HZO/TiN devices, despite the formation of an unintentional TiOxNy interfacial layer, and instead exhibit degraded polarization. This difference arises from the significantly weaker endurance enhancement and no wake-up suppression provided by oxidized TiN compared to oxidized W under comparable oxidation conditions. Overall, PE-ALD HZO films enable superior ferroelectric performance at elevated temperatures only when deposited on W BE, while Th-ALD HZO films remain a viable option for high-temperature operation on TiN BE. These findings clarify the interplay between deposition technique, electrode chemistry, and interfacial oxidation, and provide design guidelines for integrating ferroelectric memories into monolithic 3D systems under stringent thermal constraints.
{"title":"Engineering Wake-Up-Free Ferroelectric Capacitors With Enhanced High-Temperature Reliability","authors":"Nashrah Afroze;Salma Soliman;Yu-Hsin Kuo;Sanghyun Kang;Mengkun Tian;Priyankka Ravikumar;Andrea Padovani;Asif Khan","doi":"10.1109/TDMR.2026.3679333","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3679333","url":null,"abstract":"We systematically explore the design space of ferroelectric hafnium–zirconium oxide (H<sub>0.5</sub>Z<sub>0.5</sub>O or HZO) heterostructures for reliable high-temperature operation. HZO films are deposited using thermal and plasma-enhanced atomic layer deposition (Th-ALD and PE-ALD) on tungsten (W) and titanium nitride (TiN) bottom electrodes (BE), while maintaining identical top electrodes. We demonstrate that PE-ALD HZO capacitors integrated with W BE exhibit wake-up-free switching up to <inline-formula> <tex-math>$125~^{circ } $ </tex-math></inline-formula>C, along with significantly improved endurance compared to Th-ALD HZO/W devices across a wide temperature range (85–<inline-formula> <tex-math>$125~^{circ } $ </tex-math></inline-formula>C). By decoupling the contributions of the plasma-deposited HZO film and the oxidized bottom interface inherently formed during PE-ALD, we identify the oxidized W interfacial layer (WO<sub>x</sub>) as the primary factor governing endurance enhancement and wake-up suppression at elevated temperatures, while the PE-ALD HZO film provides secondary benefits in reducing wake-up. In contrast, PE-ALD HZO capacitors fabricated on TiN BE show no substantial improvement in wake-up behavior or endurance relative to Th-ALD HZO/TiN devices, despite the formation of an unintentional TiO<sub>x</sub>N<sub>y</sub> interfacial layer, and instead exhibit degraded polarization. This difference arises from the significantly weaker endurance enhancement and no wake-up suppression provided by oxidized TiN compared to oxidized W under comparable oxidation conditions. Overall, PE-ALD HZO films enable superior ferroelectric performance at elevated temperatures only when deposited on W BE, while Th-ALD HZO films remain a viable option for high-temperature operation on TiN BE. These findings clarify the interplay between deposition technique, electrode chemistry, and interfacial oxidation, and provide design guidelines for integrating ferroelectric memories into monolithic 3D systems under stringent thermal constraints.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"656-662"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-22DOI: 10.1109/TDMR.2026.3706183
Prity Sinha;Pramod Kumar Tiwari
We investigate the performance of an AlSb monolayer quantum dot (QD)-based single-electron transistor using density functional theory (DFT) to analyze its electronic and transport properties. The adsorption of toxic gases NH3, HCN, and H2S on AlSb at surface and edge sites is analyzed. Electronic structure analysis shows that new states are introduced into the band structure, while the density of state analyses reveal notable changes in the charge distribution upon adsorption. These modifications reduce the energy gap from 1.347 eV to as low as 0.178 eV, enhancing conductance. The sensing response of the AlSb monolayer in the SET environment toward these configurations is studied from the calculated total energy plot against gate voltage for distinct charge states, charge stability diagram, corresponding line scan, and normalized differential conductance are further analyzed to provide distinct charge transport signatures for each gas, facilitating a fingerprint for selective gas detection. Moreover, the device behavior in the presence of humidity and oxygen is also investigated and found to exhibit stable sensing capability. These insights highlight the viability of AlSb-based devices for sensing and switching applications and pave the way for further exploration of two-dimensional Group III–V semiconductor materials in advanced sensor technologies.
{"title":"Investigation of AlSb Monolayer and Its Application in Single-Electron Transistor for Low-Power Switching and Toxic Gas Sensing","authors":"Prity Sinha;Pramod Kumar Tiwari","doi":"10.1109/TDMR.2026.3706183","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3706183","url":null,"abstract":"We investigate the performance of an AlSb monolayer quantum dot (QD)-based single-electron transistor using density functional theory (DFT) to analyze its electronic and transport properties. The adsorption of toxic gases NH<sub>3</sub>, HCN, and H<sub>2</sub>S on AlSb at surface and edge sites is analyzed. Electronic structure analysis shows that new states are introduced into the band structure, while the density of state analyses reveal notable changes in the charge distribution upon adsorption. These modifications reduce the energy gap from 1.347 eV to as low as 0.178 eV, enhancing conductance. The sensing response of the AlSb monolayer in the SET environment toward these configurations is studied from the calculated total energy plot against gate voltage for distinct charge states, charge stability diagram, corresponding line scan, and normalized differential conductance are further analyzed to provide distinct charge transport signatures for each gas, facilitating a fingerprint for selective gas detection. Moreover, the device behavior in the presence of humidity and oxygen is also investigated and found to exhibit stable sensing capability. These insights highlight the viability of AlSb-based devices for sensing and switching applications and pave the way for further exploration of two-dimensional Group III–V semiconductor materials in advanced sensor technologies.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"942-951"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents experimental $I_{d}$ -$V_{gs}$ measurements and an analysis of the electrical characteristics of a MOS (Metal-Oxide-Semiconductor) transistor featuring a novel gate geometry referred to as the hourglass shape. This new transistor was designed to increase total ionizing radiation (TID) tolerance without modifying the manufacturing process. Experiments were conducted using a test chip with individual transistors, under temperature sweeps down to 3.6 K. Key performance metrics—including threshold voltage, subthreshold swing, and zero temperature coefficient (ZTC)—were compared against those of a conventional rectangular transistor used as a reference and a diamond transistor with similar geometry, and fabricated on the same chip. The experimental results show that the hourglass-shaped transistor presents a 27.17% reduction in normalized power consumption compared to the rectangular transistor, while the reduction is 3.61% compared to the diamond-shaped transistor. Additionally, the hourglass transistor presents a normalized increment of 115% and 10.4% in current difference with respect to the rectangular and diamond transistor, respectively across the evaluated temperature range. This study highlights the improved current efficiency of the hourglass design while maintaining lower power consumption under cryogenic conditions. The enhanced thermal stability, the stability of threshold voltage ($V_{th}$ ) and subthreshold swing (SS) shifts and energy efficiency of the proposed device across a wide temperature range are also shown.
{"title":"Electrical Behavior at Cryogenic Temperature of the Radiation-Tolerant Hourglass MOS Transistor","authors":"Carlos Alfredo Pelcastre Ortega;Mónico Linares Aranda;Daniel Ferrusca Rodríguez;Ismael Martínez Ramos;Ignacio Juárez Ramírez","doi":"10.1109/TDMR.2026.3701856","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3701856","url":null,"abstract":"This article presents experimental <inline-formula> <tex-math>$I_{d}$ </tex-math></inline-formula>-<inline-formula> <tex-math>$V_{gs}$ </tex-math></inline-formula> measurements and an analysis of the electrical characteristics of a MOS (Metal-Oxide-Semiconductor) transistor featuring a novel gate geometry referred to as the hourglass shape. This new transistor was designed to increase total ionizing radiation (TID) tolerance without modifying the manufacturing process. Experiments were conducted using a test chip with individual transistors, under temperature sweeps down to 3.6 K. Key performance metrics—including threshold voltage, subthreshold swing, and zero temperature coefficient (ZTC)—were compared against those of a conventional rectangular transistor used as a reference and a diamond transistor with similar geometry, and fabricated on the same chip. The experimental results show that the hourglass-shaped transistor presents a 27.17% reduction in normalized power consumption compared to the rectangular transistor, while the reduction is 3.61% compared to the diamond-shaped transistor. Additionally, the hourglass transistor presents a normalized increment of 115% and 10.4% in current difference with respect to the rectangular and diamond transistor, respectively across the evaluated temperature range. This study highlights the improved current efficiency of the hourglass design while maintaining lower power consumption under cryogenic conditions. The enhanced thermal stability, the stability of threshold voltage (<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>) and subthreshold swing (SS) shifts and energy efficiency of the proposed device across a wide temperature range are also shown.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"807-814"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-03-22DOI: 10.1109/TDMR.2026.3696237
Stuart E. Wodzro;Shimeng Yu
In this work, we employ 3D technology computer-aided design (TCAD) mixed-mode simulations to investigate single-event effects (SEE) in FeRAM across three distinct access-transistor geometries, prioritizing heavy-ion impingement on the access transistor. We evaluate write, hold, and read operations to elucidate the device response under varying bias configurations. The simulations are coupled with a regenerative voltage-latch sense amplifier implemented using 32 nm PTM low-power (LP) transistor models to realize the logical manifestation of the single-event effects. Under heavy-ion irradiation, the internal polarization dynamics exhibit a state-dependent response. For the Data 1 state, heavy-ion-induced charge deposition produces an electric field that degrades polarization, whereas in the Data 0 state, the induced field is constructive. This asymmetry arises from state-dependent electrostatics at the storage node. The degradation in the Data 1 state is further amplified by residual charge due to the parasitic bipolar effect present in bulk transistors. Additionally, the sense amplifier topology, whether single-ended or double-ended/differential, strongly influences the available sensing margin and thus the read robustness under radiation events.
{"title":"Modeling and Evaluation of Single Event Effects on Hafnia-Based FeRAM","authors":"Stuart E. Wodzro;Shimeng Yu","doi":"10.1109/TDMR.2026.3696237","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3696237","url":null,"abstract":"In this work, we employ 3D technology computer-aided design (TCAD) mixed-mode simulations to investigate single-event effects (SEE) in FeRAM across three distinct access-transistor geometries, prioritizing heavy-ion impingement on the access transistor. We evaluate write, hold, and read operations to elucidate the device response under varying bias configurations. The simulations are coupled with a regenerative voltage-latch sense amplifier implemented using 32 nm PTM low-power (LP) transistor models to realize the logical manifestation of the single-event effects. Under heavy-ion irradiation, the internal polarization dynamics exhibit a state-dependent response. For the Data 1 state, heavy-ion-induced charge deposition produces an electric field that degrades polarization, whereas in the Data 0 state, the induced field is constructive. This asymmetry arises from state-dependent electrostatics at the storage node. The degradation in the Data 1 state is further amplified by residual charge due to the parasitic bipolar effect present in bulk transistors. Additionally, the sense amplifier topology, whether single-ended or double-ended/differential, strongly influences the available sensing margin and thus the read robustness under radiation events.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"849-857"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-04-13DOI: 10.1109/TDMR.2026.3683485
Benjamin H. Stafford;Andreas Martin
Plasma-induced charging damage (PID) introduces additional trapping sites in gate dielectrics and can distort negative bias temperature instability (NBTI) characterization when measured with conventional hot-chuck routines. We present a fast heater-based NBTI methodology that integrates local polysilicon heaters with rapid readout to minimize the delay between stress and threshold-voltage $V_{mathrm {t}}$ measurement and to quench devices to near room temperature within the early-millisecond window. Applied to pMOSFETs with SiO2 and high-$k$ gate stacks bearing stacked-antenna structures, the fast routine captures larger threshold-voltage shifts $Delta V_{mathrm {t}}$ than the conventional routine while preserving the antenna ratio (AR) trend in SiO2. In SiO2, $Delta V_{mathrm {t}}$ increases with AR under both routines, with the fast routine producing a uniform ~8-10 mV offset at matched times; diode-protected controls show no $Delta V_{mathrm {t}}$ increase with antenna size, confirming suppression of PID. In high-$k$ devices, the apparent antenna effect is strongly routine-dependent: the conventional routine at 125°C exhibits a mild reverse antenna effect (antenna $Delta V_{mathrm {t}} lt $ reference), whereas the fast routine reveals larger immediate post-stress $Delta V_{mathrm {t}}$ in antenna devices. Pre-stress $V_{mathrm {t}}$ measurements vs temperature $T$ and early recovery data (~1-6 ms) indicate co-existing trap populations—fast, shallow positive-charge traps and slower, deep negative-charge traps—whose interplay explains the routine-dependent behavior and resolves the reverse antenna effect without post-hoc data correction. These results demonstrate that fast heater-based NBTI more faithfully probes the instantaneous post-stress state and improves reliability assessment in PID-susceptible technologies.
{"title":"Fast Heater-Based NBTI Resolves the Reverse Antenna Effect in PID-Degraded High-k and SiO2 pMOSFETs","authors":"Benjamin H. Stafford;Andreas Martin","doi":"10.1109/TDMR.2026.3683485","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3683485","url":null,"abstract":"Plasma-induced charging damage (PID) introduces additional trapping sites in gate dielectrics and can distort negative bias temperature instability (NBTI) characterization when measured with conventional hot-chuck routines. We present a fast heater-based NBTI methodology that integrates local polysilicon heaters with rapid readout to minimize the delay between stress and threshold-voltage <inline-formula> <tex-math>$V_{mathrm {t}}$ </tex-math></inline-formula> measurement and to quench devices to near room temperature within the early-millisecond window. Applied to pMOSFETs with SiO<sub>2</sub> and high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> gate stacks bearing stacked-antenna structures, the fast routine captures larger threshold-voltage shifts <inline-formula> <tex-math>$Delta V_{mathrm {t}}$ </tex-math></inline-formula> than the conventional routine while preserving the antenna ratio (AR) trend in SiO<sub>2</sub>. In SiO<sub>2</sub>, <inline-formula> <tex-math>$Delta V_{mathrm {t}}$ </tex-math></inline-formula> increases with AR under both routines, with the fast routine producing a uniform ~8-10 mV offset at matched times; diode-protected controls show no <inline-formula> <tex-math>$Delta V_{mathrm {t}}$ </tex-math></inline-formula> increase with antenna size, confirming suppression of PID. In high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> devices, the apparent antenna effect is strongly routine-dependent: the conventional routine at 125°C exhibits a mild reverse antenna effect (antenna <inline-formula> <tex-math>$Delta V_{mathrm {t}} lt $ </tex-math></inline-formula> reference), whereas the fast routine reveals larger immediate post-stress <inline-formula> <tex-math>$Delta V_{mathrm {t}}$ </tex-math></inline-formula> in antenna devices. Pre-stress <inline-formula> <tex-math>$V_{mathrm {t}}$ </tex-math></inline-formula> measurements vs temperature <inline-formula> <tex-math>$T$ </tex-math></inline-formula> and early recovery data (~1-6 ms) indicate co-existing trap populations—fast, shallow positive-charge traps and slower, deep negative-charge traps—whose interplay explains the routine-dependent behavior and resolves the reverse antenna effect without post-hoc data correction. These results demonstrate that fast heater-based NBTI more faithfully probes the instantaneous post-stress state and improves reliability assessment in PID-susceptible technologies.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"671-679"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-15DOI: 10.1109/TDMR.2026.3703987
G. Durand;F. E. Bergamaschi;M. Cassé;X. Federspiel;P. Galy;E. Vincent;I. Ionica
This paper presents hot-carrier injection measurements and model on 28nm FD-SOI transistors down to 4.2K. While the empirical models (e.g. exponential of inverse temperature) give a reasonable fit data obtained for temperatures higher than 220K, the cryogenic behavior could only be captured by more sophisticated approaches (i.e. the Lucky electron model). The impact of temperature on the creation of defects has been studied considering self-heating and degradation’s localization.
{"title":"28 nm FD-SOI Transistor Hot-Carrier Injection at Cryogenic Temperature","authors":"G. Durand;F. E. Bergamaschi;M. Cassé;X. Federspiel;P. Galy;E. Vincent;I. Ionica","doi":"10.1109/TDMR.2026.3703987","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3703987","url":null,"abstract":"This paper presents hot-carrier injection measurements and model on 28nm FD-SOI transistors down to 4.2K. While the empirical models (e.g. exponential of inverse temperature) give a reasonable fit data obtained for temperatures higher than 220K, the cryogenic behavior could only be captured by more sophisticated approaches (i.e. the Lucky electron model). The impact of temperature on the creation of defects has been studied considering self-heating and degradation’s localization.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"706-711"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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