Pub Date : 2026-06-01Epub Date: 2026-03-15DOI: 10.1109/TDMR.2026.3693765
Lu Cao;Yidan Tang;Wenlong Liu;Chaoming Liu;Zhen Dong;Yun Bai;Xiaoli Tian;Xuan Li;Jilong Hao;Yiping Xiao;Mingxue Huo;Xinyu Liu
This study investigates the underlying mechanisms of electrical performance degradation in 4H-SiC junction barrier Schottky (JBS) diodes under 1 MeV neutron irradiation at varying fluence levels through both experimental measurements and Technology Computer-Aided Design (TCAD) simulations. Defects introduced by irradiation were characterized using Deep Level Transient Spectroscopy (DLTS) and Photoluminescence (PL). The experimental results show that neutron irradiation leads to an increase in forward series resistance and reverse leakage current, with the degradation becoming more pronounced as the neutron fluence increases from $1times 10 ^{13}$ n/cm2 to $1times 10 ^{14}$ n/cm2. Notably, the degradation of reverse breakdown voltage is ascribed to a reduction in the Schottky barrier height caused by the increased defect concentration after irradiation. Simulations were employed to quantitatively elucidate the correlation between the degradation of electrical characteristics and key parameters including the Schottky barrier height, as well as the concentration and type of radiation-induced traps. The results of simulation, DLTS, and PL collectively indicate that the defects introduced by irradiation are the primary cause of the degradation in electrical performance. The concentration of Z${}_{1/2}$ defects increased by about 7 times by DLTS when the neutron irradiation dose was increased from $1times 10 ^{13}$ n/cm2 to $1times 10 ^{14}$ n/cm2. Moreover, deep-level acceptor traps induce more severe electrical degradation compared to shallow-level traps. This work establishes a solid theoretical foundation for investigating the impact of neutron irradiation on SiC power device reliability, offering guidance for future experiments and resource allocation.
{"title":"Analysis of Electrical Performance Degradation of 4H-SiC Junction Barrier Schottky Diodes Induced by Neutron Irradiation","authors":"Lu Cao;Yidan Tang;Wenlong Liu;Chaoming Liu;Zhen Dong;Yun Bai;Xiaoli Tian;Xuan Li;Jilong Hao;Yiping Xiao;Mingxue Huo;Xinyu Liu","doi":"10.1109/TDMR.2026.3693765","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3693765","url":null,"abstract":"This study investigates the underlying mechanisms of electrical performance degradation in 4H-SiC junction barrier Schottky (JBS) diodes under 1 MeV neutron irradiation at varying fluence levels through both experimental measurements and Technology Computer-Aided Design (TCAD) simulations. Defects introduced by irradiation were characterized using Deep Level Transient Spectroscopy (DLTS) and Photoluminescence (PL). The experimental results show that neutron irradiation leads to an increase in forward series resistance and reverse leakage current, with the degradation becoming more pronounced as the neutron fluence increases from <inline-formula> <tex-math>$1times 10 ^{13}$ </tex-math></inline-formula> n/cm<sup>2</sup> to <inline-formula> <tex-math>$1times 10 ^{14}$ </tex-math></inline-formula> n/cm<sup>2</sup>. Notably, the degradation of reverse breakdown voltage is ascribed to a reduction in the Schottky barrier height caused by the increased defect concentration after irradiation. Simulations were employed to quantitatively elucidate the correlation between the degradation of electrical characteristics and key parameters including the Schottky barrier height, as well as the concentration and type of radiation-induced traps. The results of simulation, DLTS, and PL collectively indicate that the defects introduced by irradiation are the primary cause of the degradation in electrical performance. The concentration of Z<inline-formula> <tex-math>${}_{1/2}$ </tex-math></inline-formula> defects increased by about 7 times by DLTS when the neutron irradiation dose was increased from <inline-formula> <tex-math>$1times 10 ^{13}$ </tex-math></inline-formula> n/cm<sup>2</sup> to <inline-formula> <tex-math>$1times 10 ^{14}$ </tex-math></inline-formula> n/cm<sup>2</sup>. Moreover, deep-level acceptor traps induce more severe electrical degradation compared to shallow-level traps. This work establishes a solid theoretical foundation for investigating the impact of neutron irradiation on SiC power device reliability, offering guidance for future experiments and resource allocation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"567-576"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-04-02DOI: 10.1109/TDMR.2026.3680306
Zhengfeng Huang;Shicheng Yang;Jianhao Wu;Xiaolei Wang;Yingchun Lu;Jun Pan;Fan Cheng;Xiaoqing Wen;Aibin Yan
As nanometer-scale CMOS technology continues to advance, the susceptibility of memory cells to soft errors has significantly increased. Single-event multiple-node upsets (MNUs) have become a critical factor affecting integrated circuit reliability. This paper first proposes a self-recoverable double-node-upset (DNU) hardened latch (DSAR) based on the Soft-Error Aware Read-Decoupled (SAR) latch. Building upon this, a Quad-SAR latch capable of tolerating Quintuple-node upset (QtNU) is designed through dual DSAR redundancy and a two-stage C-element (CE) voting mechanism, achieving an optimized balance in area, power consumption, and delay. Furthermore, to address the high-impedance-state (HIS) sensitivity issue of C-elements, a Quint-SAR latch is achieved in this paper through the implementation of Quintuple-modular redundancy (QMR) combined with an Analog Voter (AV). This structure not only effectively tolerates QtNUs, but its incorporated Analog Voter features HIS insensitivity and offers significant low-overhead advantages compared to traditional voters. Extensive fault injection, PVT fluctuation, and negative bias temperature instability (NBTI) aging effect simulations verify the reliability of the proposed designs. HSPICE simulation results show that both the Quad-SAR and Quint-SAR latches possess QtNU tolerance capability and achieve a good balance in hardware overhead. Quad-SAR is suitable for low-power and low-delay requirements in non-HIS-sensitive scenarios, while Quint-SAR, with its HIS immunity, becomes the preferred solution for high-robustness scenarios. Compared to QNU-hardened and QtNU-hardened latches, their area-power-delay product (APDP) exhibits a decrease of 49.41% and 17.16%, respectively, and their setup time exhibits a decrease of 35.10% and 49.71%, respectively.
{"title":"Design of Quintuple-Node-Upset Hardened Latches Based on C-Element Voting and an Analog Voter","authors":"Zhengfeng Huang;Shicheng Yang;Jianhao Wu;Xiaolei Wang;Yingchun Lu;Jun Pan;Fan Cheng;Xiaoqing Wen;Aibin Yan","doi":"10.1109/TDMR.2026.3680306","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3680306","url":null,"abstract":"As nanometer-scale CMOS technology continues to advance, the susceptibility of memory cells to soft errors has significantly increased. Single-event multiple-node upsets (MNUs) have become a critical factor affecting integrated circuit reliability. This paper first proposes a self-recoverable double-node-upset (DNU) hardened latch (DSAR) based on the Soft-Error Aware Read-Decoupled (SAR) latch. Building upon this, a Quad-SAR latch capable of tolerating Quintuple-node upset (QtNU) is designed through dual DSAR redundancy and a two-stage C-element (CE) voting mechanism, achieving an optimized balance in area, power consumption, and delay. Furthermore, to address the high-impedance-state (HIS) sensitivity issue of C-elements, a Quint-SAR latch is achieved in this paper through the implementation of Quintuple-modular redundancy (QMR) combined with an Analog Voter (AV). This structure not only effectively tolerates QtNUs, but its incorporated Analog Voter features HIS insensitivity and offers significant low-overhead advantages compared to traditional voters. Extensive fault injection, PVT fluctuation, and negative bias temperature instability (NBTI) aging effect simulations verify the reliability of the proposed designs. HSPICE simulation results show that both the Quad-SAR and Quint-SAR latches possess QtNU tolerance capability and achieve a good balance in hardware overhead. Quad-SAR is suitable for low-power and low-delay requirements in non-HIS-sensitive scenarios, while Quint-SAR, with its HIS immunity, becomes the preferred solution for high-robustness scenarios. Compared to QNU-hardened and QtNU-hardened latches, their area-power-delay product (APDP) exhibits a decrease of 49.41% and 17.16%, respectively, and their setup time exhibits a decrease of 35.10% and 49.71%, respectively.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"604-615"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-04-13DOI: 10.1109/TDMR.2026.3683329
Shivansh Awasthi;Vikas Kumar;Ankur Gupta
In this work, the current collapse (CC) behavior and reliability improvement of a double-channel graded-barrier high electron mobility transistor (DCGB HEMT) employing an InAlGaN-based quaternary top barrier are investigated using numerical simulations. The proposed DCGB architecture enhances gate electrostatic control and carrier confinement while suppressing buffer-trap induced dispersion. Compared with conventional single-channel (SC) HEMTs, the DCGB HEMT exhibits an improved drain current (I${}_{mathrm {D}}$ ) of approximately 0.3 A/mm. Current collapse is significantly reduced, as quantified by an improved post-stress recovery ratio (PSR${}^{2}$ ) of ~0.98 compared with ~0.80 in SC devices, corresponding to a reduction in current collapse of over 20%. This improvement is attributed to the formation of a volumetric three-dimensional electron gas (3DEG), which effectively screens the channel from Fe-related buffer trap charging. Transient drain-lag analysis further reveals faster recovery dynamics, with reduced trapping time constants extracted from exponential fitting of the transient response. These results provide design insight for dispersion-resilient GaN HEMTs targeting high-power RF, 6G power amplifier (PA), and space applications.
{"title":"Mitigation of Buffer Trap Induced Current Collapse in Quaternary Double Channel Graded-Barrier InAlGaN/GaN HEMTs","authors":"Shivansh Awasthi;Vikas Kumar;Ankur Gupta","doi":"10.1109/TDMR.2026.3683329","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3683329","url":null,"abstract":"In this work, the current collapse (CC) behavior and reliability improvement of a double-channel graded-barrier high electron mobility transistor (DCGB HEMT) employing an InAlGaN-based quaternary top barrier are investigated using numerical simulations. The proposed DCGB architecture enhances gate electrostatic control and carrier confinement while suppressing buffer-trap induced dispersion. Compared with conventional single-channel (SC) HEMTs, the DCGB HEMT exhibits an improved drain current (I<inline-formula> <tex-math>${}_{mathrm {D}}$ </tex-math></inline-formula>) of approximately 0.3 A/mm. Current collapse is significantly reduced, as quantified by an improved post-stress recovery ratio (PSR<inline-formula> <tex-math>${}^{2}$ </tex-math></inline-formula>) of ~0.98 compared with ~0.80 in SC devices, corresponding to a reduction in current collapse of over 20%. This improvement is attributed to the formation of a volumetric three-dimensional electron gas (3DEG), which effectively screens the channel from Fe-related buffer trap charging. Transient drain-lag analysis further reveals faster recovery dynamics, with reduced trapping time constants extracted from exponential fitting of the transient response. These results provide design insight for dispersion-resilient GaN HEMTs targeting high-power RF, 6G power amplifier (PA), and space applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"577-584"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148518005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-05DOI: 10.1109/TDMR.2026.3689763
Steven L. Kosier;Arijit Sengupta;Sajal Islam;Dennis R. Ball;John M. Hutson;Andrew L. Sternberg;Arthur F. Witulski;Ronald D. Schrimpf;Kenneth F. Galloway;Michael L. Alles;Jason M. Osheroff
Ideal one-dimensional expressions for Single Event Burnout (SEB) Voltage and Single Event Leakage Current (SELC) Voltage in vertical SiC power devices are derived. The derivation employs the critical energy storage and release model to show that the specific on-resistance ($R_{sp}$ ) varies with the SEB and SELC voltages to the $5^{mathrm {th}}$ power. Experimental data from MOSFETs and JBS diodes with voltage ratings of 1.2 kV to 10 kV are used to validate and illustrate the ideal limit. A physical understanding of the need for voltage derating is provided.
{"title":"Ideal Specific On-Resistance Versus Single-Event Burnout and Leakage Voltage Thresholds in Vertical SiC Power Devices","authors":"Steven L. Kosier;Arijit Sengupta;Sajal Islam;Dennis R. Ball;John M. Hutson;Andrew L. Sternberg;Arthur F. Witulski;Ronald D. Schrimpf;Kenneth F. Galloway;Michael L. Alles;Jason M. Osheroff","doi":"10.1109/TDMR.2026.3689763","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3689763","url":null,"abstract":"Ideal one-dimensional expressions for Single Event Burnout (SEB) Voltage and Single Event Leakage Current (SELC) Voltage in vertical SiC power devices are derived. The derivation employs the critical energy storage and release model to show that the specific on-resistance (<inline-formula> <tex-math>$R_{sp}$ </tex-math></inline-formula>) varies with the SEB and SELC voltages to the <inline-formula> <tex-math>$5^{mathrm {th}}$ </tex-math></inline-formula> power. Experimental data from MOSFETs and JBS diodes with voltage ratings of 1.2 kV to 10 kV are used to validate and illustrate the ideal limit. A physical understanding of the need for voltage derating is provided.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"648-651"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11506416","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-12DOI: 10.1109/TDMR.2026.3691775
Amir Shahzad;Na Ren;Liang Qiao;Xinke Liu
This paper discusses a comprehensive reliability evaluation of a 1200-V 4H-SiC planar MOSFET fabricated in-house for research purposes, subjected to Unclamped Inductive Switching (UIS) stress under a wide temperature range from $25~^{circ }$ C to $175~^{circ }$ C. Avalanche current, breakdown voltage, and avalanche energy were recorded in a systematic way to measure temperature-dependent ruggedness. The examination of post-stress failure by ultrasonic scanning, decapsulation, OBIRCH/EMMI, and FIB-SEM showed that a series of degradation processes occur, starting with early charge trapping and slight shifts of leakage, then through the formation of localized hot-spots, weakening of the gate-oxide, and the erosion of metallization. Current crowding around the source region linked by a single bond wire was the cause of catastrophic failures, which caused a short between gate and source and between drain and source once thermal runaway and parasitic BJT activation had taken place. It was demonstrated that temperature is a strong accelerator of degradation, decreasing the avalanche capability and increasing structural damage. The SEM cross-section shows that the hotspot that develops at the corner of the p+ region where the highest accumulation of electric field takes place, causes p-well degradation during early failure. These results provide new insight into the thermal-electrical overstress limits of SiC MOSFETs and highlight the critical influence of packaging-dependent current distribution on avalanche reliability.
本文讨论了一种用于研究目的的1200 v 4H-SiC平面MOSFET的综合可靠性评估，该器件在25~ $ {circ}$ C至175~ $ {circ}$ C的宽温度范围内承受非箝位电感开关（UIS）应力。雪崩电流、击穿电压和雪崩能量被系统地记录下来，以测量温度相关的坚固性。通过超声扫描、解封装、OBIRCH/EMMI和FIB-SEM对应力后破坏进行了检测，结果表明，材料发生了一系列降解过程，从早期的电荷捕获和泄漏的轻微转移开始，然后通过局部热点的形成、栅极氧化物的减弱和金属化的侵蚀。由单键线连接的源区周围的电流拥挤是灾难性故障的原因，一旦发生热失控和寄生BJT激活，就会导致栅极和源之间以及漏极和源之间的短路。结果表明，温度是一种强大的降解加速器，降低了雪崩能力，增加了结构损伤。SEM截面图显示，在p+区域的角部，电场积累最大的地方出现了热点，导致p井在早期破坏时退化。这些结果为SiC mosfet的热电超应力极限提供了新的见解，并强调了封装相关电流分布对雪崩可靠性的关键影响。
{"title":"Experimental Study on Failure Mechanism of 4H-SiC MOSFETs Under Unclamped Inductive Switching (UIS) Stress Conditions","authors":"Amir Shahzad;Na Ren;Liang Qiao;Xinke Liu","doi":"10.1109/TDMR.2026.3691775","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3691775","url":null,"abstract":"This paper discusses a comprehensive reliability evaluation of a 1200-V 4H-SiC planar MOSFET fabricated in-house for research purposes, subjected to Unclamped Inductive Switching (UIS) stress under a wide temperature range from <inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$175~^{circ }$ </tex-math></inline-formula>C. Avalanche current, breakdown voltage, and avalanche energy were recorded in a systematic way to measure temperature-dependent ruggedness. The examination of post-stress failure by ultrasonic scanning, decapsulation, OBIRCH/EMMI, and FIB-SEM showed that a series of degradation processes occur, starting with early charge trapping and slight shifts of leakage, then through the formation of localized hot-spots, weakening of the gate-oxide, and the erosion of metallization. Current crowding around the source region linked by a single bond wire was the cause of catastrophic failures, which caused a short between gate and source and between drain and source once thermal runaway and parasitic BJT activation had taken place. It was demonstrated that temperature is a strong accelerator of degradation, decreasing the avalanche capability and increasing structural damage. The SEM cross-section shows that the hotspot that develops at the corner of the p+ region where the highest accumulation of electric field takes place, causes p-well degradation during early failure. These results provide new insight into the thermal-electrical overstress limits of SiC MOSFETs and highlight the critical influence of packaging-dependent current distribution on avalanche reliability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"585-593"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To overcome the critical performance-manufacturability-cost trade-off in Internet of Things (IoT) and edge devices, this paper presents a split-gate embedded Flash (eFlash) memory in a 55-nm technology node. The memory utilizes a spacer-defined floating gate (FG) to co-optimize high performance, high manufacturability, and low cost. The proposed cell achieves a low read voltage of 1.5 V, program/erase operations at ±7 V, and a fast program time of $1~mu $ s, enabling high energy efficiency at both the cell and system levels. The self-aligned FG structure inherently eliminates etch-induced variations, demonstrating enhanced process robustness that is confirmed by a high yield in fully functional array testing. This work provides a highly competitive solution for balancing performance, manufacturability, and cost in advanced-node embedded Flash memories.
{"title":"A Process-Robust Split-Gate eFlash Memory With Spacer-Defined Floating Gate in 55-nm Node","authors":"Wanyi Ling;Kun Ren;Dianyu Qi;Yongyu Wu;Guangji Li;Miao Zhou;Qingshuang Xu;Xuan Li;Dawei Gao","doi":"10.1109/TDMR.2026.3672989","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3672989","url":null,"abstract":"To overcome the critical performance-manufacturability-cost trade-off in Internet of Things (IoT) and edge devices, this paper presents a split-gate embedded Flash (eFlash) memory in a 55-nm technology node. The memory utilizes a spacer-defined floating gate (FG) to co-optimize high performance, high manufacturability, and low cost. The proposed cell achieves a low read voltage of 1.5 V, program/erase operations at ±7 V, and a fast program time of <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>s, enabling high energy efficiency at both the cell and system levels. The self-aligned FG structure inherently eliminates etch-induced variations, demonstrating enhanced process robustness that is confirmed by a high yield in fully functional array testing. This work provides a highly competitive solution for balancing performance, manufacturability, and cost in advanced-node embedded Flash memories.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"524-530"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-12DOI: 10.1109/TDMR.2026.3673352
Jae-Yun Lee;Gergely Tarsoly;Sung-Jin Kim
Amorphous indium gallium zinc oxide (a-IGZO) is a popular research target for electronic device applications due to its versatility, high electron concentration, and high charge carrier mobility. To achieve optimal physical properties of sputtering-deposited a-IGZO films and ideal device performance characteristics, post-deposition processes such as thermal annealing are often used. In this work, we employ a 30-minute soft-chilling pre-annealing treatment to improve the performance of the device by increasing the temperature range the film is exposed to without raising the annealing temperature. Performance evaluations were performed on devices without soft chilling pre-annealing, devices treated for 30 minutes and 60 minutes, within 24 hours of fabrication, and after 12 months and 18 months of low-humidity storage. To show the applicability in digital circuits, load type NOT, NOR and NAND logic gates were fabricated and tested. The device response was shown to be stable and unchanged for 18 months storage period, evidencing high long-term stability without encapsulation. This work proves that soft chilling is a viable route for the improvement of amorphous metal oxide thin film-based devices.
{"title":"Soft-Chilled Amorphous Indium Gallium Zinc Oxide Semiconductors Enable High-Performance Digital Circuits With Excellent Long-Term Stability","authors":"Jae-Yun Lee;Gergely Tarsoly;Sung-Jin Kim","doi":"10.1109/TDMR.2026.3673352","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3673352","url":null,"abstract":"Amorphous indium gallium zinc oxide (a-IGZO) is a popular research target for electronic device applications due to its versatility, high electron concentration, and high charge carrier mobility. To achieve optimal physical properties of sputtering-deposited a-IGZO films and ideal device performance characteristics, post-deposition processes such as thermal annealing are often used. In this work, we employ a 30-minute soft-chilling pre-annealing treatment to improve the performance of the device by increasing the temperature range the film is exposed to without raising the annealing temperature. Performance evaluations were performed on devices without soft chilling pre-annealing, devices treated for 30 minutes and 60 minutes, within 24 hours of fabrication, and after 12 months and 18 months of low-humidity storage. To show the applicability in digital circuits, load type NOT, NOR and NAND logic gates were fabricated and tested. The device response was shown to be stable and unchanged for 18 months storage period, evidencing high long-term stability without encapsulation. This work proves that soft chilling is a viable route for the improvement of amorphous metal oxide thin film-based devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"485-491"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-17DOI: 10.1109/TDMR.2026.3674791
Konstantinos M. Gektidis;Ioannis Kaissas;Thomas Tsovilis
This work presents an interdisciplinary experimental study on the impact of gamma radiation on the performance and reliability of surge protective components, focusing on both switching-type and limiting-type technologies. Gas discharge tubes, metal-oxide varistors, and transient voltage suppressor diodes were experimentally evaluated before and after prolonged exposure (~740 to ~2370 hours) to gamma radiation from Cesium-137 and Barium-133 sources, having activities of ~5.7 MBq and ~4.1 MBq, respectively. The novelty of the study lies in the evaluation of 1) switching-type components performance under standardized 8/$20~mu $ s impulse current waveforms and 2) limiting-type components voltage-current characteristic over the 30–1000 Hz range up to ~1 A. The investigation considers both varying dose rates and prolonged exposure durations applied to the devices under test. The resulting data were systematically examined to assess radiation-induced variations in electrical characteristics, providing insight into the radiation resilience of surge protective components and supporting their deployment in radiation-prone environments, including aerospace, nuclear, medical, and defense applications.
{"title":"Gamma Irradiation Effects on Surge Protective Components: A Comprehensive Experimental Evaluation of Transient and V–I Characteristics","authors":"Konstantinos M. Gektidis;Ioannis Kaissas;Thomas Tsovilis","doi":"10.1109/TDMR.2026.3674791","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3674791","url":null,"abstract":"This work presents an interdisciplinary experimental study on the impact of gamma radiation on the performance and reliability of surge protective components, focusing on both switching-type and limiting-type technologies. Gas discharge tubes, metal-oxide varistors, and transient voltage suppressor diodes were experimentally evaluated before and after prolonged exposure (~740 to ~2370 hours) to gamma radiation from Cesium-137 and Barium-133 sources, having activities of ~5.7 MBq and ~4.1 MBq, respectively. The novelty of the study lies in the evaluation of 1) switching-type components performance under standardized 8/<inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>s impulse current waveforms and 2) limiting-type components voltage-current characteristic over the 30–1000 Hz range up to ~1 A. The investigation considers both varying dose rates and prolonged exposure durations applied to the devices under test. The resulting data were systematically examined to assess radiation-induced variations in electrical characteristics, providing insight into the radiation resilience of surge protective components and supporting their deployment in radiation-prone environments, including aerospace, nuclear, medical, and defense applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"556-566"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11436019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The demand for copper-based composite materials is increasing in various sectors such as electronics, automobiles, electrochemical systems, etc. In the recent past, 2D materials such as graphene, TMDs, etc., have emerged, and incorporating into a metallic copper matrix for manifold capabilities. In the present work, the exfoliated graphene is reinforced (1-3 wt.%) with a copper matrix and prepared composite electrodes for investigating corrosion resistance, electrochemical sensing. Initially, various characterization such as XRD, Raman spectra, FESEM, HRTEM were employed for evaluating the phases, defects, morphologies, interfaces, etc. The corrosion resistance was examined in a harsh 3.5 wt.% NaCl electrolyte solution. It is observed that corrosion rates (CR) of copper-graphene composite (Cu-3.0G: CR $= 0.21~pm ~0.05$ mpy) are significantly reduced, multiple folds than that of pure copper (CR $= 3.08~pm ~0.18$ mpy). The graphene-embedded copper composite showed impressive electrochemical performances, e.g. cyclic voltammetry, impedance in Na2SO4 electrolyte/solvents. The composite electrode is able to differentiate the NaCl, Na2SO4 electrolytes based on the electrochemical interaction between the electrode surface and electrolytes. The insights are attributed to the infusion of graphene flakes, hydrophobic (WCA: $75.3~pm ~1.5^{circ }$ C) nature of the electrode surface, perhaps grow the passivation layer over the composite surface. Thus, graphene-reinforced copper composite electrodes can strongly be recommended for extreme corrosion resistance, electrochemical sensing, etc., for exploring harsh, underwater challenges.
{"title":"Corrosion-Resistant Cu/Graphene Nanocomposite-Based Electrodes for Advanced Electrochemical Measurements","authors":"Aminul Islam;Ankur Gupta;J. Jency Rubia;Yogesh Tripathi;Pratiksha Sarma;Abhishek Kumar Grain;Supriya Khatoniar;Arindam Majhi;Julaiba Tahsina Mazumdar;Anup Kumar Keshri;Santosha Kumar Dwivedy;Ravindra Kumar Jha","doi":"10.1109/TDMR.2026.3666875","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3666875","url":null,"abstract":"The demand for copper-based composite materials is increasing in various sectors such as electronics, automobiles, electrochemical systems, etc. In the recent past, 2D materials such as graphene, TMDs, etc., have emerged, and incorporating into a metallic copper matrix for manifold capabilities. In the present work, the exfoliated graphene is reinforced (1-3 wt.%) with a copper matrix and prepared composite electrodes for investigating corrosion resistance, electrochemical sensing. Initially, various characterization such as XRD, Raman spectra, FESEM, HRTEM were employed for evaluating the phases, defects, morphologies, interfaces, etc. The corrosion resistance was examined in a harsh 3.5 wt.% NaCl electrolyte solution. It is observed that corrosion rates (CR) of copper-graphene composite (Cu-3.0G: CR <inline-formula> <tex-math>$= 0.21~pm ~0.05$ </tex-math></inline-formula> mpy) are significantly reduced, multiple folds than that of pure copper (CR <inline-formula> <tex-math>$= 3.08~pm ~0.18$ </tex-math></inline-formula> mpy). The graphene-embedded copper composite showed impressive electrochemical performances, e.g. cyclic voltammetry, impedance in Na<sub>2</sub>SO<sub>4</sub> electrolyte/solvents. The composite electrode is able to differentiate the NaCl, Na<sub>2</sub>SO<sub>4</sub> electrolytes based on the electrochemical interaction between the electrode surface and electrolytes. The insights are attributed to the infusion of graphene flakes, hydrophobic (WCA: <inline-formula> <tex-math>$75.3~pm ~1.5^{circ }$ </tex-math></inline-formula>C) nature of the electrode surface, perhaps grow the passivation layer over the composite surface. Thus, graphene-reinforced copper composite electrodes can strongly be recommended for extreme corrosion resistance, electrochemical sensing, etc., for exploring harsh, underwater challenges.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"516-523"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-06-11DOI: 10.1109/TDMR.2026.3696479
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2026.3696479","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3696479","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11559147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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