Threading screw dislocations (TSDs) in heteroepitaxial GaN introduce quasi-one-dimensional (1D) conductive filaments that penetrate the full device depth, constituting a primary source of reverse leakage current in vertical heterogeneous power devices. Conventional TCAD simulation approaches, which model defects as zero-dimensional point charges, cannot capture the stochastic lateral distribution of TSDs or their coupling to three-dimensional (3D) electric field distributions. This work proposes a cross-scale numerical framework that couples a 1D trap carrier transport with a 3D bulk drift-diffusion model through carrier exchange terms. Critical physical parameters are derived from the first-principle calculation of the single six-atom ring TSD core and calibrated against experimental data of GaN vertical diodes, achieving quantitative agreement across a temperature range of 210–470 K within a bias voltage range of 0–300 V. The calibrated framework is applied to a GaN oxide-gated vertical trench MOSFET, where the TSD lateral position is varied across 56 devices. Under the conservative worst-case assumption of a single-6-atom ring TSD core, the analysis reveals that stochastic dislocation placement produces an upper-bound TAT threshold voltage spread of 31 V for a $0.6~mu $ m trench depth, and 71 V for a $0.9~mu $ m trench. This twofold increase is driven by the lateral electric field non-uniformity near the trench corner, and motivates a reorientation of vertical GaN device design principles, where lateral field uniformity should be treated as a primary constraint alongside breakdown voltage.
{"title":"Cross-Scale Modeling of Threading Screw Dislocation Leakage in Heterogeneous GaN Vertical Devices","authors":"Nian-En Zhang;Shuo Zhang;Zhifa Zhang;Qi Shen;Hao Xie;Guoguang Lu;Cheng Zhuo;Wen-Yan Yin","doi":"10.1109/TDMR.2026.3718878","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3718878","url":null,"abstract":"Threading screw dislocations (TSDs) in heteroepitaxial GaN introduce quasi-one-dimensional (1D) conductive filaments that penetrate the full device depth, constituting a primary source of reverse leakage current in vertical heterogeneous power devices. Conventional TCAD simulation approaches, which model defects as zero-dimensional point charges, cannot capture the stochastic lateral distribution of TSDs or their coupling to three-dimensional (3D) electric field distributions. This work proposes a cross-scale numerical framework that couples a 1D trap carrier transport with a 3D bulk drift-diffusion model through carrier exchange terms. Critical physical parameters are derived from the first-principle calculation of the single six-atom ring TSD core and calibrated against experimental data of GaN vertical diodes, achieving quantitative agreement across a temperature range of 210–470 K within a bias voltage range of 0–300 V. The calibrated framework is applied to a GaN oxide-gated vertical trench MOSFET, where the TSD lateral position is varied across 56 devices. Under the conservative worst-case assumption of a single-6-atom ring TSD core, the analysis reveals that stochastic dislocation placement produces an upper-bound TAT threshold voltage spread of 31 V for a <inline-formula> <tex-math>$0.6~mu $ </tex-math></inline-formula>m trench depth, and 71 V for a <inline-formula> <tex-math>$0.9~mu $ </tex-math></inline-formula>m trench. This twofold increase is driven by the lateral electric field non-uniformity near the trench corner, and motivates a reorientation of vertical GaN device design principles, where lateral field uniformity should be treated as a primary constraint alongside breakdown voltage.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"984-994"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-10-12DOI: 10.1109/TDMR.2026.3739660
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2026.3739660","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3739660","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11733520","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-07-29DOI: 10.1109/TDMR.2026.3718376
Andressa Mara Menezes Alexandre;Paulo Soares Filho;Helio Fiori de Castro;Tárcio André dos Santos Barros
This work presents a new methodology for predicting capacitor reliability, explicitly incorporating operational and constructional uncertainties. The proposed method introduces four main advances: statistical modeling of capacitance, Equivalent Series Resistance (ESR), and thermal resistance as probability distributions instead of fixed average values; replacement of traditional Lookup Table (LUT) with Kriging-based interpolation, ensuring higher accuracy and generalization capability; representation of the voltage stress factor as a uniform random variable, covering the uncertainty range that is often neglected; and the adoption of the gamma distribution for lifetime fitting, replacing the traditional Weibull-based model. The proposed methodology was evaluated through a computational analysis of a bank of eight electrolytic capacitors, while the interpolation stage was additionally validated using experimental measurements. The results showed that the new methodology provides more conservative predictions. The failure time associated with the $B_{10}$ analysis was estimated at approximately 7 years for a single capacitor and 5.2 years for the capacitor bank, while the traditional method indicated 11.8 years and 8.2 years, respectively. This difference represents a reduction of about 36.6% in the estimated lifetime when compared to the established procedure in the literature. Furthermore, the experimental validation of the interpolation stage showed that the Kriging metamodel exhibited greater agreement with the measured capacitor losses than the linear interpolation of the LUT, reducing the maximum error from 0.0604 W to 0.0006 W, corresponding to a reduction of approximately 99.0%. Such results demonstrate that the proposed approach is more consistent with the physical and statistical nature of cumulative aging mechanisms, providing more conservative estimates for practical applications in photovoltaic inverters and other power electronic converters.
{"title":"Uncertainty-Aware Probabilistic Reliability Algorithm for Capacitors Using Kriging-Based Electrothermal Modeling","authors":"Andressa Mara Menezes Alexandre;Paulo Soares Filho;Helio Fiori de Castro;Tárcio André dos Santos Barros","doi":"10.1109/TDMR.2026.3718376","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3718376","url":null,"abstract":"This work presents a new methodology for predicting capacitor reliability, explicitly incorporating operational and constructional uncertainties. The proposed method introduces four main advances: statistical modeling of capacitance, Equivalent Series Resistance (ESR), and thermal resistance as probability distributions instead of fixed average values; replacement of traditional Lookup Table (LUT) with Kriging-based interpolation, ensuring higher accuracy and generalization capability; representation of the voltage stress factor as a uniform random variable, covering the uncertainty range that is often neglected; and the adoption of the gamma distribution for lifetime fitting, replacing the traditional Weibull-based model. The proposed methodology was evaluated through a computational analysis of a bank of eight electrolytic capacitors, while the interpolation stage was additionally validated using experimental measurements. The results showed that the new methodology provides more conservative predictions. The failure time associated with the <inline-formula> <tex-math>$B_{10}$ </tex-math></inline-formula> analysis was estimated at approximately 7 years for a single capacitor and 5.2 years for the capacitor bank, while the traditional method indicated 11.8 years and 8.2 years, respectively. This difference represents a reduction of about 36.6% in the estimated lifetime when compared to the established procedure in the literature. Furthermore, the experimental validation of the interpolation stage showed that the Kriging metamodel exhibited greater agreement with the measured capacitor losses than the linear interpolation of the LUT, reducing the maximum error from 0.0604 W to 0.0006 W, corresponding to a reduction of approximately 99.0%. Such results demonstrate that the proposed approach is more consistent with the physical and statistical nature of cumulative aging mechanisms, providing more conservative estimates for practical applications in photovoltaic inverters and other power electronic converters.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"858-870"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11627945","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-02-26DOI: 10.1109/TDMR.2026.3668707
Maria Trakosa;Odysseas Chatzopoulos;Dimitris Gizopoulos
As semiconductor fabrication scales to smaller technology nodes, process variation presents significant challenges, affecting power consumption, thermal behavior, and voltage stability in silicon compute devices. Conservative voltage guardbands are traditionally used to ensure reliable operation under worst-case process, voltage, and temperature (PVT) variations, but they lead to excessive power consumption. Reducing the supply voltage is a promising technique for improving energy efficiency without sacrificing computational correctness and performance. While extensive research has been conducted on reducing the voltage levels in CPUs and NVIDIA GPUs, the AMD GPU side remains relatively unexplored. Process variation, inherent in semiconductor manufacturing, results in differences in power efficiency, thermal characteristics, and voltage stability even among identical GPUs from the same production batch. In this paper, we present an extensive study on voltage scaling beyond nominal conditions for three modern AMD NAVI GPUs (i.e., RX 7600 XT, 7700 XT, and 7800 XT) executing both conventional benchmarks and PyTorch-based machine learning workloads. We evaluate and present power savings and execution stability by combining undervolting characterization with neutron irradiation physical experiments, contributing to a deeper understanding of undervolting and resilience of AMD GPUs.
{"title":"NAVIgator Under Fire: Characterizing Voltage Limits and Soft Error Resilience of AMD NAVI GPUs","authors":"Maria Trakosa;Odysseas Chatzopoulos;Dimitris Gizopoulos","doi":"10.1109/TDMR.2026.3668707","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3668707","url":null,"abstract":"As semiconductor fabrication scales to smaller technology nodes, process variation presents significant challenges, affecting power consumption, thermal behavior, and voltage stability in silicon compute devices. Conservative voltage guardbands are traditionally used to ensure reliable operation under worst-case process, voltage, and temperature (PVT) variations, but they lead to excessive power consumption. Reducing the supply voltage is a promising technique for improving energy efficiency without sacrificing computational correctness and performance. While extensive research has been conducted on reducing the voltage levels in CPUs and NVIDIA GPUs, the AMD GPU side remains relatively unexplored. Process variation, inherent in semiconductor manufacturing, results in differences in power efficiency, thermal characteristics, and voltage stability even among identical GPUs from the same production batch. In this paper, we present an extensive study on voltage scaling beyond nominal conditions for three modern AMD NAVI GPUs (i.e., RX 7600 XT, 7700 XT, and 7800 XT) executing both conventional benchmarks and PyTorch-based machine learning workloads. We evaluate and present power savings and execution stability by combining undervolting characterization with neutron irradiation physical experiments, contributing to a deeper understanding of undervolting and resilience of AMD GPUs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"761-770"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149175959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-03-02DOI: 10.1109/TDMR.2026.3669812
Andreas Martin;Benjamin H. Stafford
A case of plasma processing induced charging damage (PID), precisely well charging on a product is reported which was not detected by antenna design rules during layout control with a standard antenna rule checking procedure. The affected MOS device is placed in an n-well over p-substrate and comprising of a high-k dielectric layer. Three critical properties of the degraded MOS device are, the placement of the MOS in a simple n-well (contrary to previous reports), the absence of a signal path to a second MOS device in a different well and the influence of the large dielectric area of the degraded MOS device. The product malfunction is finally a superposition of non-ideal high-k dielectric processing reducing reliability and suboptimal design. High-temperature operating life (HTOL) stress results of product testing are presented. Various design solutions for effective protection are described avoiding the degradation from PID. It is demonstrated based on experimental data that a comprehensively established fast wafer level reliability (fWLR) monitoring methodology can detect such a product reliability loss before shipping products to a customer. The dependence of a well antenna ratio (AR${}_{mathrm {W}}$ ) on the dielectric area of the degraded MOS device is discussed in detail and a first order solution for a design rule check proposed. PID well charging is currently a hot topic and this work adds further aspects to the methodology of PID reliability testing and productive antenna design rule checks.
{"title":"PID Well-Charging Observed for Large MOS Transistors Embedded in Suboptimal Product Design and Triggered by Inhomogeneous High-k Dielectric Reliability","authors":"Andreas Martin;Benjamin H. Stafford","doi":"10.1109/TDMR.2026.3669812","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3669812","url":null,"abstract":"A case of plasma processing induced charging damage (PID), precisely well charging on a product is reported which was not detected by antenna design rules during layout control with a standard antenna rule checking procedure. The affected MOS device is placed in an n-well over p-substrate and comprising of a high-k dielectric layer. Three critical properties of the degraded MOS device are, the placement of the MOS in a simple n-well (contrary to previous reports), the absence of a signal path to a second MOS device in a different well and the influence of the large dielectric area of the degraded MOS device. The product malfunction is finally a superposition of non-ideal high-k dielectric processing reducing reliability and suboptimal design. High-temperature operating life (HTOL) stress results of product testing are presented. Various design solutions for effective protection are described avoiding the degradation from PID. It is demonstrated based on experimental data that a comprehensively established fast wafer level reliability (fWLR) monitoring methodology can detect such a product reliability loss before shipping products to a customer. The dependence of a well antenna ratio (AR<inline-formula> <tex-math>${}_{mathrm {W}}$ </tex-math></inline-formula>) on the dielectric area of the degraded MOS device is discussed in detail and a first order solution for a design rule check proposed. PID well charging is currently a hot topic and this work adds further aspects to the methodology of PID reliability testing and productive antenna design rule checks.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"680-688"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-10DOI: 10.1109/TDMR.2026.3702337
C. Dimri;R. Asanovski;S. Santermans;S. Balamurali;A. Potočnik;A. Beckers;B. Kaczer;A. Grill;K. De Greve
The 22nm fully-depleted silicon-on-insulator (FDSOI) technology is considered near-ideal for creating low-power cryogenic control electronics, a key milestone in the pursuit of large-scale fault-tolerant quantum computers. However, it is essential to assess the device reliability under conditions of interest, as various gate stack reliability phenomena such as bias temperature instability (BTI) and hot carrier degradation (HCD) have been reported active at 4K. This study comprehensively analyzes the shift in device parameters induced by BTI stress and recovery from room temperature down to 4K. A new method of assessing the impact of cryogenic BTI on ultra-low-power applications is presented, showcasing how nMOS devices of the 22nm technology prove to be ready for long-term cryo-operation, whereas pMOS devices do not.
{"title":"Impact of Cryogenic Bias Temperature Instabilities on Low-Voltage Operation of 22-nm Fully-Depleted Silicon-on-Insulator MOSFETs","authors":"C. Dimri;R. Asanovski;S. Santermans;S. Balamurali;A. Potočnik;A. Beckers;B. Kaczer;A. Grill;K. De Greve","doi":"10.1109/TDMR.2026.3702337","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3702337","url":null,"abstract":"The 22nm fully-depleted silicon-on-insulator (FDSOI) technology is considered near-ideal for creating low-power cryogenic control electronics, a key milestone in the pursuit of large-scale fault-tolerant quantum computers. However, it is essential to assess the device reliability under conditions of interest, as various gate stack reliability phenomena such as bias temperature instability (BTI) and hot carrier degradation (HCD) have been reported active at 4K. This study comprehensively analyzes the shift in device parameters induced by BTI stress and recovery from room temperature down to 4K. A new method of assessing the impact of cryogenic BTI on ultra-low-power applications is presented, showcasing how nMOS devices of the 22nm technology prove to be ready for long-term cryo-operation, whereas pMOS devices do not.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"697-705"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-03-29DOI: 10.1109/TDMR.2026.3698068
Ting Yang;Jie Zeng;Qidong Xie;Kyong Jin Hwang;Tupei Chen
This work investigates the impact of epitaxial layer (Epi) thickness on the holding voltage ($V_{mathrm {h}}$ ) scalability of bidirectional silicon-controlled rectifiers (BiSCRs) in 130 nm BCD technology. Experimental results show that increasing the base lengths ($L_{mathrm {nb}}$ /$L_{mathrm {pb}}$ ) of parasitic BJTs leads to a linear increase in $V_{mathrm {h}}$ under a thicker epitaxial process ($1.5times $ ), while having a negligible impact in a thinner epitaxial process ($1times $ ). Technology computer-aided design (TCAD) simulations attribute this disparity to Epi dependent current gain variations in the parasitic NPN and PNP BJTs: thinner Epi strengthens NPN gain, dominating conduction current and suppressing $V_{mathrm {h}}$ control via lateral base-length adjustments, while thicker Epi weakens NPN gain, enabling effective $V_{mathrm {h}}$ tuning. These findings demonstrate that Epi thickness critically determines the efficacy of geometric design strategies for BiSCR latch-up immunity, guiding optimized ESD protection in holding-voltage sensitive applications.
{"title":"Influence of Epitaxial Layer Thickness on the Holding Voltage Scalability of Bi-Directional SCR Devices","authors":"Ting Yang;Jie Zeng;Qidong Xie;Kyong Jin Hwang;Tupei Chen","doi":"10.1109/TDMR.2026.3698068","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3698068","url":null,"abstract":"This work investigates the impact of epitaxial layer (Epi) thickness on the holding voltage (<inline-formula> <tex-math>$V_{mathrm {h}}$ </tex-math></inline-formula>) scalability of bidirectional silicon-controlled rectifiers (BiSCRs) in 130 nm BCD technology. Experimental results show that increasing the base lengths (<inline-formula> <tex-math>$L_{mathrm {nb}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$L_{mathrm {pb}}$ </tex-math></inline-formula>) of parasitic BJTs leads to a linear increase in <inline-formula> <tex-math>$V_{mathrm {h}}$ </tex-math></inline-formula> under a thicker epitaxial process (<inline-formula> <tex-math>$1.5times $ </tex-math></inline-formula>), while having a negligible impact in a thinner epitaxial process (<inline-formula> <tex-math>$1times $ </tex-math></inline-formula>). Technology computer-aided design (TCAD) simulations attribute this disparity to Epi dependent current gain variations in the parasitic NPN and PNP BJTs: thinner Epi strengthens NPN gain, dominating conduction current and suppressing <inline-formula> <tex-math>$V_{mathrm {h}}$ </tex-math></inline-formula> control via lateral base-length adjustments, while thicker Epi weakens NPN gain, enabling effective <inline-formula> <tex-math>$V_{mathrm {h}}$ </tex-math></inline-formula> tuning. These findings demonstrate that Epi thickness critically determines the efficacy of geometric design strategies for BiSCR latch-up immunity, guiding optimized ESD protection in holding-voltage sensitive applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"794-799"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-08-06DOI: 10.1109/TDMR.2026.3721283
Pritika Singh;Harshita Rai;Tejendra Dixit;Shyam S. Pandey;Vipul Singh
Organic field-effect transistors (OFETs) based on conjugated polymers are promising for flexible, low-cost electronics; however, their performance is often limited by interfacial trap states and disordered molecular packing. In this work, the combined influence of fabrication method (spin coating and UFTM), dielectric interface engineering (OTS and CYTOP), and molecular orientation on the charge transport characteristics of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2)-based thin film transistors is systematically investigated. The UFTM process produces highly aligned polymer films, yielding pronounced optical anisotropy with a dichroic ratio of $sim ~6.5$ at an optimized annealing temperature of $120~^{circ }$ C. The optimized UFTM CYTOP $(|)$ device exhibits a maximum field-effect mobility of $sim 2.8times 10^{-3}$ cm2 V−1 s−1, an on/off current ratio of $sim ~4times 10^{6}$ , improved threshold voltage, reduced subthreshold swing, excellent device-to-device reproducibility, while retaining $sim ~80$ % of its initial mobility after 60 days under ambient conditions. These findings demonstrate a simple, low-cost, and scalable fabrication strategy for improving the electrical performance and operational reliability of F8T2-based OFETs.
{"title":"Synergistic Thin-Film Alignment and Surface Passivation for Anisotropic Charge Transport and Long-Term Stability in OFETs","authors":"Pritika Singh;Harshita Rai;Tejendra Dixit;Shyam S. Pandey;Vipul Singh","doi":"10.1109/TDMR.2026.3721283","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3721283","url":null,"abstract":"Organic field-effect transistors (OFETs) based on conjugated polymers are promising for flexible, low-cost electronics; however, their performance is often limited by interfacial trap states and disordered molecular packing. In this work, the combined influence of fabrication method (spin coating and UFTM), dielectric interface engineering (OTS and CYTOP), and molecular orientation on the charge transport characteristics of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2)-based thin film transistors is systematically investigated. The UFTM process produces highly aligned polymer films, yielding pronounced optical anisotropy with a dichroic ratio of <inline-formula> <tex-math>$sim ~6.5$ </tex-math></inline-formula> at an optimized annealing temperature of <inline-formula> <tex-math>$120~^{circ }$ </tex-math></inline-formula>C. The optimized UFTM CYTOP <inline-formula> <tex-math>$(|)$ </tex-math></inline-formula> device exhibits a maximum field-effect mobility of <inline-formula> <tex-math>$sim 2.8times 10^{-3}$ </tex-math></inline-formula> cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>, an on/off current ratio of <inline-formula> <tex-math>$sim ~4times 10^{6}$ </tex-math></inline-formula>, improved threshold voltage, reduced subthreshold swing, excellent device-to-device reproducibility, while retaining <inline-formula> <tex-math>$sim ~80$ </tex-math></inline-formula>% of its initial mobility after 60 days under ambient conditions. These findings demonstrate a simple, low-cost, and scalable fabrication strategy for improving the electrical performance and operational reliability of F8T2-based OFETs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"935-941"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-03DOI: 10.1109/TDMR.2026.3699742
Rino Micheloni;Nicholas Battistini;Gabriele Miorandi;Luca Crippa;Alessia Marelli;Savino Di Giosa;Cristian Zambelli
3D NAND Flash technology is central to modern Solid State Drives (SSDs), where reliability and performance are critical across all levels of architecture. While Error Correction Codes (ECC) and read retry mechanisms are standard for mitigating reliability issues, they are often constrained by strict endurance and data retention limits. This study explores an alternative methodology to extend SSD longevity by integrating a Threshold Voltage (VT)-shift Flash Signal Processing (FSP) technique with advanced ECC strategies. Experimental results from a custom SSD implementation demonstrate a $1.8times $ increase in Program/Erase (P/E) cycles and a total lifetime extension of $1.9times $ over contemporary state-of-the-art solutions and link the results to the different Write Amplification Factor. The total cost of ownership (TCO) will also be considered.
3D NAND闪存技术是现代固态硬盘（ssd）的核心，其可靠性和性能在所有级别的架构中都至关重要。虽然纠错码（Error Correction Codes， ECC）和读取重试机制是缓解可靠性问题的标准，但它们通常受到严格的持久性和数据保留限制的约束。本研究探索了一种通过将阈值电压（VT）移位闪光信号处理（FSP）技术与先进的ECC策略相结合来延长SSD寿命的替代方法。自定义SSD实现的实验结果表明，与当代最先进的解决方案相比，程序/擦除（P/E）周期增加了1.8倍，总寿命延长了1.9倍，并将结果与不同的写入放大系数联系起来。总拥有成本（TCO）也将被考虑在内。
{"title":"System-Level Lifetime Extension in 3-D NAND SSDs via VT-Shift-Aware Flash Signal Processing and Advanced ECC","authors":"Rino Micheloni;Nicholas Battistini;Gabriele Miorandi;Luca Crippa;Alessia Marelli;Savino Di Giosa;Cristian Zambelli","doi":"10.1109/TDMR.2026.3699742","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3699742","url":null,"abstract":"3D NAND Flash technology is central to modern Solid State Drives (SSDs), where reliability and performance are critical across all levels of architecture. While Error Correction Codes (ECC) and read retry mechanisms are standard for mitigating reliability issues, they are often constrained by strict endurance and data retention limits. This study explores an alternative methodology to extend SSD longevity by integrating a Threshold Voltage (VT)-shift Flash Signal Processing (FSP) technique with advanced ECC strategies. Experimental results from a custom SSD implementation demonstrate a <inline-formula> <tex-math>$1.8times $ </tex-math></inline-formula> increase in Program/Erase (P/E) cycles and a total lifetime extension of <inline-formula> <tex-math>$1.9times $ </tex-math></inline-formula> over contemporary state-of-the-art solutions and link the results to the different Write Amplification Factor. The total cost of ownership (TCO) will also be considered.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 3","pages":"712-718"},"PeriodicalIF":2.7,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149176283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-09-01Epub Date: 2026-06-26DOI: 10.1109/TDMR.2026.3707557
Jiale Wang;Yun Bai;Shuai Lai;Jilong Hao;Xuan Li;Yidan Tang;Xiaoli Tian;Xinyu Liu
This paper presents the design and characterization of a current-source-loaded common-source amplifier (CST), a five-transistor operational transconductance amplifier (5OTA), and a two-stage differential operational amplifier (AMP) composed of these two circuits. All circuits were fabricated using a 4H-SiC CMOS process and demonstrated operation across a wide temperature range from 25°C to 500°C. The gain of these amplifiers exhibits distinct trends as temperature increases. Without dynamic adjustment of the bias voltage ($V_{mathrm {bias}}$ ) and the DC input voltage ($V_{mathrm {IN}}$ ) with rising temperature, the gain of the CST degrades rapidly. In contrast, the 5OTA shows a stable gain increase from 25°C to 400°C even without dynamic adjustment of $V_{mathrm {bias}}$ and $V_{mathrm {IN}}$ , owing to its tail current source. However, its DC output level initially increases and then decreases with temperature. This shift affects the gain of subsequent amplifier stages, explaining why the gain of the AMP begins to decrease when the temperature exceeds 300°C. These results demonstrate the potential of 4H-SiC CMOS circuits for harsh-environment applications and highlight the significant impact of circuit topology on amplifier performance stability over a wide temperature range.
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