Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731670
W. Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, T. Lee, M. Chang
Efficient edge computing, with sufficiently large on-chip memory capacity, is essential in the internet-of-everything era. Nonvolatile computing-in-memory (nvCIM) reduces the data transfer overhead by bringing computation closer, in proximity, to the memory [1]–[4]. While the multi-level cell (MLC) has higher storage density than the single-level cell (SLC). A few MLC or analog nvCIM designs had been proposed, but they either target simpler neural-net models [5] or are implemented using a less area-efficient differential cell [6]. Furthermore, representing the entire weight vector using one storage type does not exploit the drastic accuracy difference between the upper and the lower bits.
{"title":"A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices","authors":"W. Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, T. Lee, M. Chang","doi":"10.1109/ISSCC42614.2022.9731670","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731670","url":null,"abstract":"Efficient edge computing, with sufficiently large on-chip memory capacity, is essential in the internet-of-everything era. Nonvolatile computing-in-memory (nvCIM) reduces the data transfer overhead by bringing computation closer, in proximity, to the memory [1]–[4]. While the multi-level cell (MLC) has higher storage density than the single-level cell (SLC). A few MLC or analog nvCIM designs had been proposed, but they either target simpler neural-net models [5] or are implemented using a less area-efficient differential cell [6]. Furthermore, representing the entire weight vector using one storage type does not exploit the drastic accuracy difference between the upper and the lower bits.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"83 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73906798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731761
{"title":"Session 11 Overview: Compute-in-Memory and SRAM","authors":"","doi":"10.1109/isscc42614.2022.9731761","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731761","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"161 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76451842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731779
{"title":"Session 4 Overview: mm-Wave and Sub-THz ICs for Communication and Sensing","authors":"","doi":"10.1109/isscc42614.2022.9731779","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731779","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"24 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79163265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731539
{"title":"Session 28 Overview: DRAM and Interface","authors":"","doi":"10.1109/isscc42614.2022.9731539","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731539","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"99 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79307327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731612
R. Prabhakar, Sumti Jairath, Jinuk Luke Shin
The availability of large amounts of data and advances in modern machine-learning algorithms are pushing the limits of computing systems and redefining the way software is written. This new software paradigm, termed “Software 2.0”, is a departure from deterministic computing - centered around exact specifications and expert-created algorithms to accomplish a task - to probabilistic computing, centered around methods that learn to accomplish the same task using several examples. Software 2.0 contains a graph of operations that is rich in data locality and has abundant data, task, and hierarchical pipeline parallelism. Consequently, Software 2.0 can be accelerated by building custom dataflow pipelines. However, conventional GPU systems provide limited flexibility to build such dataflow pipelines. As a result, they suffer from poor device utilization and require a high-bandwidth off-chip memory system, which results in lower memory capacity. Memory capacity limitations impose serious challenges for increasingly larger models and data sets common in the fields of Natural Language Processing (NLP), high-resolution computer vision, and large recommender systems. SambaNova Systems Cardinal SN10 is a Reconfigurable Dataflow Unit (RDU) that enables accelerating Software 2.0 with the flexibility to build custom dataflow pipelines as well as large memory capacity to run big models efficiently [1].
大量数据的可用性和现代机器学习算法的进步正在推动计算系统的极限，并重新定义软件的编写方式。这种新的软件范式被称为“软件2.0”，它从确定性计算(以精确的规范和专家创建的算法为中心来完成任务)转向概率计算(以学习使用几个示例来完成相同任务的方法为中心)。软件2.0包含一个操作图，它具有丰富的数据局部性，并具有丰富的数据、任务和分层管道并行性。因此，可以通过构建定制的数据流管道来加速软件2.0。然而，传统的GPU系统提供有限的灵活性来构建这样的数据流管道。因此，它们的设备利用率很低，并且需要高带宽的片外存储系统，这导致内存容量较低。在自然语言处理(NLP)、高分辨率计算机视觉和大型推荐系统等领域中，内存容量的限制给越来越大的模型和数据集带来了严峻的挑战。SambaNova Systems Cardinal SN10是一款可重构数据流单元(RDU)，它可以加速Software 2.0，灵活地构建自定义数据流管道，以及大容量内存，从而有效地运行大型模型。
{"title":"SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0","authors":"R. Prabhakar, Sumti Jairath, Jinuk Luke Shin","doi":"10.1109/ISSCC42614.2022.9731612","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731612","url":null,"abstract":"The availability of large amounts of data and advances in modern machine-learning algorithms are pushing the limits of computing systems and redefining the way software is written. This new software paradigm, termed “Software 2.0”, is a departure from deterministic computing - centered around exact specifications and expert-created algorithms to accomplish a task - to probabilistic computing, centered around methods that learn to accomplish the same task using several examples. Software 2.0 contains a graph of operations that is rich in data locality and has abundant data, task, and hierarchical pipeline parallelism. Consequently, Software 2.0 can be accelerated by building custom dataflow pipelines. However, conventional GPU systems provide limited flexibility to build such dataflow pipelines. As a result, they suffer from poor device utilization and require a high-bandwidth off-chip memory system, which results in lower memory capacity. Memory capacity limitations impose serious challenges for increasingly larger models and data sets common in the fields of Natural Language Processing (NLP), high-resolution computer vision, and large recommender systems. SambaNova Systems Cardinal SN10 is a Reconfigurable Dataflow Unit (RDU) that enables accelerating Software 2.0 with the flexibility to build custom dataflow pipelines as well as large memory capacity to run big models efficiently [1].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"40 1","pages":"350-352"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79481477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biometric authentication is a proven and practical way to identify personal information efficiently. In payment card applications, using biometrics is of primary interest because it makes the cardholder verification method (CVM) simpler with a higher level of security. Instead of personal identification numbers (PINs) or signatures, individual and unique physical information is applied in the payment procedure. Among several biometric alternatives, the use of fingerprint recognition is becoming the most popular method in plastic smart card applications, because of user convenience and compatibility with the current payment infrastructure without modifications or additional devices [1].
{"title":"A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication","authors":"Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Jae Hyun Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung-Ung Kwak","doi":"10.1109/ISSCC42614.2022.9731106","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731106","url":null,"abstract":"Biometric authentication is a proven and practical way to identify personal information efficiently. In payment card applications, using biometrics is of primary interest because it makes the cardholder verification method (CVM) simpler with a higher level of security. Instead of personal identification numbers (PINs) or signatures, individual and unique physical information is applied in the payment procedure. Among several biometric alternatives, the use of fingerprint recognition is becoming the most popular method in plastic smart card applications, because of user convenience and compatibility with the current payment infrastructure without modifications or additional devices [1].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"77 1","pages":"504-506"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85999856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731585
G. Lim, Gyeong-Gu Kang, Hyunggun Ma, M. Jeong, Hyunsik Kim
As the spatial resolution of mobile OLED displays increases, more than a thousand column channels must be integrated into a source-driver IC (SD-IC). Furthermore, the data resolution of the DAC occupying the majority area of the column channel must become higher for color-depth improvement. The top-left of Fig. 5.9.1 shows a typical SD-IC architecture composed of R-DAC-based column channels sharing a global resistor-string. The switch-array size of the conventional R-DAC increases proportionally to a power of 2 with DAC resolution. Moreover, since the full-scale range ${left(FSR,=,V_{H},-,V_{L}right)}$ of the R-string is directly correlated with the dynamic range in an OLED display, the R-DAC, including level-shifters (L/S), must be implemented with high-voltage MOSFETs (HV-MOS). Accordingly, even modern CMOS technology nodes are still unable to shrink the SD-IC size considerably. Thus far, many efforts to improve the DAC area efficiency employing a voltage-interpolative sub-DAC have been reported [1 – 3], as shown in the top-middle of Fig. 5.9.1. However, the use of a 2-output HV R-dAc, which occupies 2× larger area, is mandatory for voltage interpolation. Mismatch between sub-DACs is also inevitable, and thus the inter-channel uniformity, one of the key performance metrics in a SD-IC, deteriorates significantly. This paper presents an ultra-compact-sized 10b SD-IC achieving an area of 2688μm2/nel even without adopting voltage-interpolation. As shown in the top-right of Fig. 5.9.1, two key innovations of this work include: 1) a mismatch-insensitive switched-capacitor-based LV-to-HV-amplify DAC, which enables an 8b R-DAC to be realized with only low-voltage MOSFETs (LV-MOS) while obtaining the HV output, and 2) a deviation-free 2b LSB stack-up (LSU) technique enabling finer resolution consuming little area. Considering a 1.5V thin-gate MOS is 24×smaller than a 5V thick-gate MOS for the same ${R_{text{ON}}}$ in 130nm CMOS, this work can achieve dramatic shrinkage of the chip size due to the all-LV-MOS-based R-DAC in conjunction with the elimination of L/S. In addition, both our innovations are highly robust to process variations and thus contribute to overcoming inter-channel mismatch, which is a drawback of prior voltage-interpolative schemes.
{"title":"A 10b Source-Driver IC with LSB-Stacked LV-to-HV-Amplify DAC Achieving 2688μm2/channel and 4.8mV DVO for Mobile OLED Displays","authors":"G. Lim, Gyeong-Gu Kang, Hyunggun Ma, M. Jeong, Hyunsik Kim","doi":"10.1109/ISSCC42614.2022.9731585","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731585","url":null,"abstract":"As the spatial resolution of mobile OLED displays increases, more than a thousand column channels must be integrated into a source-driver IC (SD-IC). Furthermore, the data resolution of the DAC occupying the majority area of the column channel must become higher for color-depth improvement. The top-left of Fig. 5.9.1 shows a typical SD-IC architecture composed of R-DAC-based column channels sharing a global resistor-string. The switch-array size of the conventional R-DAC increases proportionally to a power of 2 with DAC resolution. Moreover, since the full-scale range ${left(FSR,=,V_{H},-,V_{L}right)}$ of the R-string is directly correlated with the dynamic range in an OLED display, the R-DAC, including level-shifters (L/S), must be implemented with high-voltage MOSFETs (HV-MOS). Accordingly, even modern CMOS technology nodes are still unable to shrink the SD-IC size considerably. Thus far, many efforts to improve the DAC area efficiency employing a voltage-interpolative sub-DAC have been reported [1 – 3], as shown in the top-middle of Fig. 5.9.1. However, the use of a 2-output HV R-dAc, which occupies 2× larger area, is mandatory for voltage interpolation. Mismatch between sub-DACs is also inevitable, and thus the inter-channel uniformity, one of the key performance metrics in a SD-IC, deteriorates significantly. This paper presents an ultra-compact-sized 10b SD-IC achieving an area of 2688μm2/nel even without adopting voltage-interpolation. As shown in the top-right of Fig. 5.9.1, two key innovations of this work include: 1) a mismatch-insensitive switched-capacitor-based LV-to-HV-amplify DAC, which enables an 8b R-DAC to be realized with only low-voltage MOSFETs (LV-MOS) while obtaining the HV output, and 2) a deviation-free 2b LSB stack-up (LSU) technique enabling finer resolution consuming little area. Considering a 1.5V thin-gate MOS is 24×smaller than a 5V thick-gate MOS for the same ${R_{text{ON}}}$ in 130nm CMOS, this work can achieve dramatic shrinkage of the chip size due to the all-LV-MOS-based R-DAC in conjunction with the elimination of L/S. In addition, both our innovations are highly robust to process variations and thus contribute to overcoming inter-channel mismatch, which is a drawback of prior voltage-interpolative schemes.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"4 1","pages":"110-112"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77096796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731738
Alessandro Franceschin, Domenico Riccardi, A. Mazzanti
The phase noise of oscillators limits the modulation Error Vector Magnitude (EVM) in wireless communications and the SNR in high-speed data converters. The issue is particularly critical in the wireless infrastructure for 5G and beyond, where base stations and backhaul transceivers need extremely low phase noise to support wide bandwidth and spectrally efficient modulation schemes at high carrier frequency. Given the supply voltage, the phase noise in LC oscillators is reduced by scaling down the inductance and increasing power consumption. However, the Q degradation with too-small inductors sets a lower bound on phase noise [1], [2]. To overcome this limit, oscillators evolved from a single-core to multicore topologies, where N oscillators are coupled to scale down phase noise by 10log(N). This concept was exploited with two cores [1] and then extended to four [2]–[4] and eight cores [5], giving ideally the phase-noise reduction of 3, 6, and 9dB, respectively. Nevertheless, mismatches between oscillators impair phase noise and penalize the figure of merit (FoM) [3]. Moreover, with the number of cores that grows exponentially, the extension of the approach for further phase-noise reduction is not practical.
{"title":"Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM","authors":"Alessandro Franceschin, Domenico Riccardi, A. Mazzanti","doi":"10.1109/ISSCC42614.2022.9731738","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731738","url":null,"abstract":"The phase noise of oscillators limits the modulation Error Vector Magnitude (EVM) in wireless communications and the SNR in high-speed data converters. The issue is particularly critical in the wireless infrastructure for 5G and beyond, where base stations and backhaul transceivers need extremely low phase noise to support wide bandwidth and spectrally efficient modulation schemes at high carrier frequency. Given the supply voltage, the phase noise in LC oscillators is reduced by scaling down the inductance and increasing power consumption. However, the Q degradation with too-small inductors sets a lower bound on phase noise [1], [2]. To overcome this limit, oscillators evolved from a single-core to multicore topologies, where N oscillators are coupled to scale down phase noise by 10log(N). This concept was exploited with two cores [1] and then extended to four [2]–[4] and eight cores [5], giving ideally the phase-noise reduction of 3, 6, and 9dB, respectively. Nevertheless, mismatches between oscillators impair phase noise and penalize the figure of merit (FoM) [3]. Moreover, with the number of cores that grows exponentially, the extension of the approach for further phase-noise reduction is not practical.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80831960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731781
Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seung-Jun Bae, Won-Woong Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, T. B. Cho
The conventional cellular mobile device needs a tens-of-MHz main crystal oscillator (XO) and 32.768kHz real-time clock (RTC) XO for RF ultra-low-jitter PLLs and sleep operation, respectively. To minimize BoM cost and PCB area by reducing the number of crystals, the low-power main XO with a fractional divider (DIV.) in [1] is reported for the RTC. However, the high-power-consuming start-up operation for high-Q-factor main XO is inevitable. The on-chip RC oscillator (RCO) can be an alternative to the RTC XO due to its compact area and excellent stability over process, voltage, and temperature (PVT) variation. To improve the temperature sensitivity of the RCO, the two-point trimming using the resistors having the opposite temperature coefficient (TC) is employed in [2], but the accuracy is limited to 20ppm/ºC due to the $1^{text{st}}$ -order compensation. The RCOs using high-resolution temperature-sensor units (TSUs) in [3], [4] can improve the TC up to <10ppm/ºC. However, the TSU requires a large area and an external FPGA to address complex digital signals. In addition, the previous approaches of [2]–[4] can be applied only to the limited processes providing a negative TC resistor. The main XO should accomplish ultra-low jitter for the RF PLLs (i.e $< 100{text{fs}}_{text{rms}})$, but it causes long start-up time due to a large swing of the XO. Consequently, the system stand-by power is increased. Although a precisely timed energy injection in [5] can effectively reduce the start-up time, it is only applicable when the clock swing is small (0.32V). The 2-step injection technique [6] can improve the start-up time of the XO close to the theoretical limit even with large swing, but the short-circuit current of the buffer for a reference clock of the PLL restricts the start-up energy reduction (3.4×).
{"title":"A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration","authors":"Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seung-Jun Bae, Won-Woong Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, T. B. Cho","doi":"10.1109/ISSCC42614.2022.9731781","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731781","url":null,"abstract":"The conventional cellular mobile device needs a tens-of-MHz main crystal oscillator (XO) and 32.768kHz real-time clock (RTC) XO for RF ultra-low-jitter PLLs and sleep operation, respectively. To minimize BoM cost and PCB area by reducing the number of crystals, the low-power main XO with a fractional divider (DIV.) in [1] is reported for the RTC. However, the high-power-consuming start-up operation for high-Q-factor main XO is inevitable. The on-chip RC oscillator (RCO) can be an alternative to the RTC XO due to its compact area and excellent stability over process, voltage, and temperature (PVT) variation. To improve the temperature sensitivity of the RCO, the two-point trimming using the resistors having the opposite temperature coefficient (TC) is employed in [2], but the accuracy is limited to 20ppm/ºC due to the $1^{text{st}}$ -order compensation. The RCOs using high-resolution temperature-sensor units (TSUs) in [3], [4] can improve the TC up to <10ppm/ºC. However, the TSU requires a large area and an external FPGA to address complex digital signals. In addition, the previous approaches of [2]–[4] can be applied only to the limited processes providing a negative TC resistor. The main XO should accomplish ultra-low jitter for the RF PLLs (i.e $< 100{text{fs}}_{text{rms}})$, but it causes long start-up time due to a large swing of the XO. Consequently, the system stand-by power is increased. Although a precisely timed energy injection in [5] can effectively reduce the start-up time, it is only applicable when the clock swing is small (0.32V). The 2-step injection technique [6] can improve the start-up time of the XO close to the theoretical limit even with large swing, but the short-circuit current of the buffer for a reference clock of the PLL restricts the start-up energy reduction (3.4×).","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"2 1","pages":"58-60"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81675080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731669
Tingxu Hu, Mo Huang, Yan Lu, R. Martins
Automotive and industrial applications require a high-efficiency DC-DC converter to directly convert power from the 12V intermediate bus to a low-voltage point-of-load (PoL). The double step-down (DSD) buck converter [1]–[4] (shown in Fig. 18.3.1) is suitable for such applications, where a flying capacitor $C_{mathrm{F}}$ sustains a half-input-voltage $(V_{text{IN}}/2)$ stress. Therefore, all the power switches only experience $V_{text{IN}}/2$ stress except $M_{mathrm{A}2}$, allowing for exploiting the benefits of low-voltage devices. Two pulse-width modulation (PWM) signals $phi_{1}$ and $phi_{2}$ with an equal duty cycle $D$ drive the DSD. A $text{PoL}$ supply should have a small output capacitor $C_{0}$ if a fast dynamic voltage scaling (DVS) is needed. However, a small $C_{0}$ in the conventional DSD may cause a large output undershoot $V_{text{US}}$ during a transient event. This comes from the low inductor current slew rate $I_{mathrm{L}_{-}text{SR}}=(V_{text{IN}}/2-2V_{0})/L$, due to the amplitude of the inductor switching nodes $V_{text{XA}1}$ and $V_{text{XB}1}$ being reduced to $V_{text{IN}}/2$ by $C_{mathrm{F}}$, and the non-overlapping $phi_{1}$ and $phi_{2}$ in a conventional $Dleq 0.5$ control. Furthermore, the $D$ should cover a wide range to respond to an integral transient error in the control loop compensator. With $Dleq 0.5$, the DSD converter may fail to cancel the error in time, and the accumulation and release of the error result in overshoot/ringing. This would be more severe at a higher output voltage $V_{0}$ because the steady-state $D$ is closer to 0.5. A possible solution can be to have a DSD converter that works with $D>0.5$. Nevertheless, this leads to an over-sterss on $M_{mathrm{A}1}$, and imbalance in inductor currents $I_{text{LA}}$ and $I_{text{LB}}$, which should be eliminated [3].
{"title":"A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD","authors":"Tingxu Hu, Mo Huang, Yan Lu, R. Martins","doi":"10.1109/ISSCC42614.2022.9731669","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731669","url":null,"abstract":"Automotive and industrial applications require a high-efficiency DC-DC converter to directly convert power from the 12V intermediate bus to a low-voltage point-of-load (PoL). The double step-down (DSD) buck converter [1]–[4] (shown in Fig. 18.3.1) is suitable for such applications, where a flying capacitor <tex>$C_{mathrm{F}}$</tex> sustains a half-input-voltage <tex>$(V_{text{IN}}/2)$</tex> stress. Therefore, all the power switches only experience <tex>$V_{text{IN}}/2$</tex> stress except <tex>$M_{mathrm{A}2}$</tex>, allowing for exploiting the benefits of low-voltage devices. Two pulse-width modulation (PWM) signals <tex>$phi_{1}$</tex> and <tex>$phi_{2}$</tex> with an equal duty cycle <tex>$D$</tex> drive the DSD. A <tex>$text{PoL}$</tex> supply should have a small output capacitor <tex>$C_{0}$</tex> if a fast dynamic voltage scaling (DVS) is needed. However, a small <tex>$C_{0}$</tex> in the conventional DSD may cause a large output undershoot <tex>$V_{text{US}}$</tex> during a transient event. This comes from the low inductor current slew rate <tex>$I_{mathrm{L}_{-}text{SR}}=(V_{text{IN}}/2-2V_{0})/L$</tex>, due to the amplitude of the inductor switching nodes <tex>$V_{text{XA}1}$</tex> and <tex>$V_{text{XB}1}$</tex> being reduced to <tex>$V_{text{IN}}/2$</tex> by <tex>$C_{mathrm{F}}$</tex>, and the non-overlapping <tex>$phi_{1}$</tex> and <tex>$phi_{2}$</tex> in a conventional <tex>$Dleq 0.5$</tex> control. Furthermore, the <tex>$D$</tex> should cover a wide range to respond to an integral transient error in the control loop compensator. With <tex>$Dleq 0.5$</tex>, the DSD converter may fail to cancel the error in time, and the accumulation and release of the error result in overshoot/ringing. This would be more severe at a higher output voltage <tex>$V_{0}$</tex> because the steady-state <tex>$D$</tex> is closer to 0.5. A possible solution can be to have a DSD converter that works with <tex>$D>0.5$</tex>. Nevertheless, this leads to an over-sterss on <tex>$M_{mathrm{A}1}$</tex>, and imbalance in inductor currents <tex>$I_{text{LA}}$</tex> and <tex>$I_{text{LB}}$</tex>, which should be eliminated [3].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82096136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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