Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731792
Xiaosen Liu, H. Krishnamurthy, Renzhi Liu, K. Ravichandran, Zakir Ahmed, Nachiket V. Desai, N. Butzen, J. Tschanz, V. De
Complex SoCs in nanoscale CMOS integrate a variety of digital compute/memory and analog/mixed-signal circuits such as SerDes transceivers, RF/wireless front-end, PLLs, sensors, etc. On-chip low-dropout regulators (LDOs) isolate the input $mathrm{V}_{text{in}}$ noise from switching DC-DC converters powering the digital blocks (Fig. 30.4.1) and provide high power-supply rejection (PSR) to the noise-sensitive analog/mixed-signal circuits by modulating the small-signal output resistance $(mathrm{R}_{0}$) of the power FET in the saturation region. Therefore, the minimum dropout (DO) voltage must be larger than the necessary gate overdrive (OV). While larger DO enables higher Ro and better PSR, it degrades the LDO power conversion efficiency (PCE). Using larger power FETs can reduce OV and DO for a target $mathrm{l}_{max}$ but at the cost of more die area. Therefore, LDO designs that provide the required high PSR while maximizing PCE and area efficiency are essential for high-performance SoCs [1].
{"title":"A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer","authors":"Xiaosen Liu, H. Krishnamurthy, Renzhi Liu, K. Ravichandran, Zakir Ahmed, Nachiket V. Desai, N. Butzen, J. Tschanz, V. De","doi":"10.1109/ISSCC42614.2022.9731792","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731792","url":null,"abstract":"Complex SoCs in nanoscale CMOS integrate a variety of digital compute/memory and analog/mixed-signal circuits such as SerDes transceivers, RF/wireless front-end, PLLs, sensors, etc. On-chip low-dropout regulators (LDOs) isolate the input $mathrm{V}_{text{in}}$ noise from switching DC-DC converters powering the digital blocks (Fig. 30.4.1) and provide high power-supply rejection (PSR) to the noise-sensitive analog/mixed-signal circuits by modulating the small-signal output resistance $(mathrm{R}_{0}$) of the power FET in the saturation region. Therefore, the minimum dropout (DO) voltage must be larger than the necessary gate overdrive (OV). While larger DO enables higher Ro and better PSR, it degrades the LDO power conversion efficiency (PCE). Using larger power FETs can reduce OV and DO for a target $mathrm{l}_{max}$ but at the cost of more die area. Therefore, LDO designs that provide the required high PSR while maximizing PCE and area efficiency are essential for high-performance SoCs [1].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"137 1","pages":"478-480"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86283913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731744
Shihkai Kuo, Manideep Dunna, Dinesh Bharadia, P. Mercier
Many envisioned IoT applications are not realizable today due to the mW-level power burden of wireless communication circuits for the most popular consumer standards: WiFi and BLE. To help enable new IoT applications, WiFi backscatter communication techniques have been shown to enable a ∼1, 000× reduction in power consumption over conventional transceivers while maintaining WiFi standard compatibility [1]–[3]. However, pragmatic deployment is currently hindered by their limited range, and lack of IC implementations for BLE [4]–[5]. For example, [3] and [1] only operate with inter- access point (AP) distances of 16m and 21m, respectively, which is not quite sufficient for robust operation in dense office environments, or large smart warehouses or airports with larger (and therefore lower cost) inter-AP deployment distances. Since backscatter modulation is passive with no RF power amplification, additional range can only be achieved by reducing insertion loss or adding antenna gain. For example, the work in [2] replaced 500 absorbing terminations with reactive terminations to reduce insertion loss over [1] and improve range to 26m, though a bulky and lossy Wilkinson power splitter/combiner was still required. The work in [2] also introduced a way to utilize multiple antennas to achieve MIMO-like antenna gain, though only in a static retro-reflective manner with no beam steering capabilities. This latter approach requires two co-located APs, which have self-interference challenges, and are thus not readily available in existing mesh networks. In addition to range challenges, there are no current backscatter ICs that can operate with BLE.
{"title":"A WiFi and Bluetooth Backscattering Combo Chip Featuring Beam Steering via a Fully-Reflective Phased-Controlled Multi-Antenna Termination Technique Enabling Operation Over 56 Meters","authors":"Shihkai Kuo, Manideep Dunna, Dinesh Bharadia, P. Mercier","doi":"10.1109/ISSCC42614.2022.9731744","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731744","url":null,"abstract":"Many envisioned IoT applications are not realizable today due to the mW-level power burden of wireless communication circuits for the most popular consumer standards: WiFi and BLE. To help enable new IoT applications, WiFi backscatter communication techniques have been shown to enable a ∼1, 000× reduction in power consumption over conventional transceivers while maintaining WiFi standard compatibility [1]–[3]. However, pragmatic deployment is currently hindered by their limited range, and lack of IC implementations for BLE [4]–[5]. For example, [3] and [1] only operate with inter- access point (AP) distances of 16m and 21m, respectively, which is not quite sufficient for robust operation in dense office environments, or large smart warehouses or airports with larger (and therefore lower cost) inter-AP deployment distances. Since backscatter modulation is passive with no RF power amplification, additional range can only be achieved by reducing insertion loss or adding antenna gain. For example, the work in [2] replaced 500 absorbing terminations with reactive terminations to reduce insertion loss over [1] and improve range to 26m, though a bulky and lossy Wilkinson power splitter/combiner was still required. The work in [2] also introduced a way to utilize multiple antennas to achieve MIMO-like antenna gain, though only in a static retro-reflective manner with no beam steering capabilities. This latter approach requires two co-located APs, which have self-interference challenges, and are thus not readily available in existing mesh networks. In addition to range challenges, there are no current backscatter ICs that can operate with BLE.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"44 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86778163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Soil monitoring provides comprehensive information on the ecosystem and soil functions, but it involves intensive field sampling and costly laboratory analysis. Advanced wireless sensor networks ease the sampling process and labor efforts [1]. However, the proliferation of wireless environmental monitoring applications is problematic in maintaining the power required for proper operation. Also, battery poses issues for minimizing sensor nodes and limiting environmental pollution. Ambient energy harvesting offers an alternative power supply to operate the sensor interface and wireless transceiver [2]–[5]. However, batteryless wireless sensor nodes typically suffer from low RF-powering sensitivity (~ -20dBm) [2], [5] and a short communication distance [4], making them unsuitable for wide-range environmental monitoring.
{"title":"A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting","authors":"Chuan-Yi Wu, Chi-Wei Liu, Jing-Siang Chen, Cong-Sheng Huang, Ting-Heng Lu, Ling-Chia Chen, I. Ou, Sook-Kuan Lee, Yen-Chi Chen, Po-Hung Chen, Chi-Te Liu, Ying-Chih Liao, Y. Liao","doi":"10.1109/ISSCC42614.2022.9731723","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731723","url":null,"abstract":"Soil monitoring provides comprehensive information on the ecosystem and soil functions, but it involves intensive field sampling and costly laboratory analysis. Advanced wireless sensor networks ease the sampling process and labor efforts [1]. However, the proliferation of wireless environmental monitoring applications is problematic in maintaining the power required for proper operation. Also, battery poses issues for minimizing sensor nodes and limiting environmental pollution. Ambient energy harvesting offers an alternative power supply to operate the sensor interface and wireless transceiver [2]–[5]. However, batteryless wireless sensor nodes typically suffer from low RF-powering sensitivity (~ -20dBm) [2], [5] and a short communication distance [4], making them unsuitable for wide-range environmental monitoring.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84234971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731789
Qilong Liu, L. Breems, Chenming Zhang, Shagun Bajoria, M. Bolatkale, R. Rutten, G. Radulov
In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1]–[3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to layout parasitics due to the high sampling rates, and most important of all, are power hungry, consuming several hundreds of mW. In this paper, we propose a filtering rnulti-stage noise-shaping (MASH) ΔΣ ADC architecture that overcomes the abovementioned drawbacks. Passive delay compensating filters [4] are used to realize broadband and deep suppression of the input signal component at the internal filter nodes of the ADC. As a result, no interstage DACs are needed, which are commonly required to generate the quantization error replicas in a MASH ΔΣ ADC, saving substantial power and greatly reducing the parasitic load of the high-speed critical nodes. Moreover, because of the absence of signal content at the internal filter nodes, the backend stages of the MASH architecture have relaxed linearity requirements and can be implemented with simple low-power Gm-C filters. Precise excess loop delay and excess phase compensation are accomplished with a partly resistive and capacitive stabilization DAC, enabling very-high-speed operation of the ΔΣ loops. The realized MASH ADC is sampled at 5GHz and achieves 68dB/65dB DR/peak SNDR over a 360MHz bandwidth, -78dBc THD at -1dBFS for a 115MHz input signal, and consumes 158mW. Implemented in a mature 40nm CMOS technology, the ADC occupies only 0.21 mm2 core area, achieves 2× lower power, 5dB higher Schreier FOM and 2× lower Walden FOM compared to state-of-the-art broadband CT ADCs in advanced 16nm-28nm nodes [1]–[3].
{"title":"A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS","authors":"Qilong Liu, L. Breems, Chenming Zhang, Shagun Bajoria, M. Bolatkale, R. Rutten, G. Radulov","doi":"10.1109/ISSCC42614.2022.9731789","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731789","url":null,"abstract":"In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1]–[3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to layout parasitics due to the high sampling rates, and most important of all, are power hungry, consuming several hundreds of mW. In this paper, we propose a filtering rnulti-stage noise-shaping (MASH) ΔΣ ADC architecture that overcomes the abovementioned drawbacks. Passive delay compensating filters [4] are used to realize broadband and deep suppression of the input signal component at the internal filter nodes of the ADC. As a result, no interstage DACs are needed, which are commonly required to generate the quantization error replicas in a MASH ΔΣ ADC, saving substantial power and greatly reducing the parasitic load of the high-speed critical nodes. Moreover, because of the absence of signal content at the internal filter nodes, the backend stages of the MASH architecture have relaxed linearity requirements and can be implemented with simple low-power Gm-C filters. Precise excess loop delay and excess phase compensation are accomplished with a partly resistive and capacitive stabilization DAC, enabling very-high-speed operation of the ΔΣ loops. The realized MASH ADC is sampled at 5GHz and achieves 68dB/65dB DR/peak SNDR over a 360MHz bandwidth, -78dBc THD at -1dBFS for a 115MHz input signal, and consumes 158mW. Implemented in a mature 40nm CMOS technology, the ADC occupies only 0.21 mm2 core area, achieves 2× lower power, 5dB higher Schreier FOM and 2× lower Walden FOM compared to state-of-the-art broadband CT ADCs in advanced 16nm-28nm nodes [1]–[3].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"66 1","pages":"414-416"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81068519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731678
T. Burd, Wilson Li, James Pistole, S. Venkataraman, M. McCabe, Timothy Johnson, J. Vinh, Thomas Yiu, M. Wasio, H. Wong, Daryl Lieu, Jonathan White, B. Munger, Joshua Lindner, Javin Olson, S. Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar
“Zen 3” is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation “Zen 2” core [1], as well as the same platform infrastructure, the primary “Zen 3” design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency. The core complex unit (CCX) consists of 8 “Zen 3” cores, each with a 0.5MB private L2 cache, and a 32MB shared L3 cache. Increasing this from 4 cores and 16MB L3 in the prior generation provides additional performance uplift, in addition to the IPC and frequency improvements. The “Zen 3” CCX shown in Fig. 2.7.1 contains 4.08B transistors in 68mm2, and is used across a broad array of client, server, and embedded market segments.
{"title":"Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core","authors":"T. Burd, Wilson Li, James Pistole, S. Venkataraman, M. McCabe, Timothy Johnson, J. Vinh, Thomas Yiu, M. Wasio, H. Wong, Daryl Lieu, Jonathan White, B. Munger, Joshua Lindner, Javin Olson, S. Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar","doi":"10.1109/ISSCC42614.2022.9731678","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731678","url":null,"abstract":"“Zen 3” is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation “Zen 2” core [1], as well as the same platform infrastructure, the primary “Zen 3” design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency. The core complex unit (CCX) consists of 8 “Zen 3” cores, each with a 0.5MB private L2 cache, and a 32MB shared L3 cache. Increasing this from 4 cores and 16MB L3 in the prior generation provides additional performance uplift, in addition to the IPC and frequency improvements. The “Zen 3” CCX shown in Fig. 2.7.1 contains 4.08B transistors in 68mm2, and is used across a broad array of client, server, and embedded market segments.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"150 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79449759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731625
Juzheng Liu, Mohsen Hassanpourghadi, M. Chen
High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-domain time-interleaved (TI) SAR ADC [1]–[2] is a popular choice for its superior power efficiency. However, its single-channel sample rate is generally limited to <1GS/s, necessitating a large number of TI channels in high-sample-rate scenarios. It inevitably increases implementation overhead, including capacitive loading to the input driver and total area consumption. Recently, time-domain ADCs [3]–[5] have shown promising sampling speed, but are mostly based on thermometer coded time-to-digital converters (TDC). Unfortunately, the circuit complexity for such Flash TDC grows exponentially with the target bit resolution. Existing SAR TDCs [6] demonstrate a lower complexity but are generally limited in sample rate (MS/s). In this work, we propose a two-step time-domain ADC that uses a first-stage Flash TDC with the residue time quantized by the second-stage SAR TDC, targeting the >GS/s regime. To further improve the throughput of SAR TDC conversion, we propose a delay-tracking pipelining technique that allows the SAR TDC to quantize two residue time samples, simultaneously. At the circuit level, we use a selective delay tuning (SDT) cell to provide the time reference required for SAR conversion without using an excessive number of delay stages. A proof-of-concept ADC prototype in 14nm CMOS technology with 2x time interleaving achieves 10GS/s with 37.2dB SNDR at Nyquist frequency. It measures an energy efficiency of 24.8fJ/conv-step and occupies an active area of 2850um2, which are the highest reported energy efficiency and smallest area consumption among the state-of-the-art ADCs with> 10GS/s [7].
高速(>GS/s)中分辨率adc对宽带通信ic的需求很大。同时，先进技术节点的成本不断增加，有利于面积高效的ADC架构。传统的电压域时间交错(TI) SAR ADC[1] -[2]因其卓越的功率效率而成为一种流行的选择。然而，它的单通道采样率通常限制在GS/s范围内。为了进一步提高SAR TDC转换的吞吐量，我们提出了一种延迟跟踪流水线技术，该技术允许SAR TDC同时量化两个剩余时间样本。在电路级，我们使用选择性延迟调谐(SDT)单元来提供SAR转换所需的时间参考，而不使用过多的延迟级。概念验证ADC原型采用14nm CMOS技术，采用2倍时间交错，在Nyquist频率下实现10GS/s和37.2dB SNDR。它的能量效率为24.8fJ/ v-step，占用2850um2的有效面积，这是目前最先进的> 10GS/s的adc中报道的最高的能量效率和最小的面积消耗[7]。
{"title":"A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology","authors":"Juzheng Liu, Mohsen Hassanpourghadi, M. Chen","doi":"10.1109/ISSCC42614.2022.9731625","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731625","url":null,"abstract":"High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-domain time-interleaved (TI) SAR ADC [1]–[2] is a popular choice for its superior power efficiency. However, its single-channel sample rate is generally limited to <1GS/s, necessitating a large number of TI channels in high-sample-rate scenarios. It inevitably increases implementation overhead, including capacitive loading to the input driver and total area consumption. Recently, time-domain ADCs [3]–[5] have shown promising sampling speed, but are mostly based on thermometer coded time-to-digital converters (TDC). Unfortunately, the circuit complexity for such Flash TDC grows exponentially with the target bit resolution. Existing SAR TDCs [6] demonstrate a lower complexity but are generally limited in sample rate (MS/s). In this work, we propose a two-step time-domain ADC that uses a first-stage Flash TDC with the residue time quantized by the second-stage SAR TDC, targeting the >GS/s regime. To further improve the throughput of SAR TDC conversion, we propose a delay-tracking pipelining technique that allows the SAR TDC to quantize two residue time samples, simultaneously. At the circuit level, we use a selective delay tuning (SDT) cell to provide the time reference required for SAR conversion without using an excessive number of delay stages. A proof-of-concept ADC prototype in 14nm CMOS technology with 2x time interleaving achieves 10GS/s with 37.2dB SNDR at Nyquist frequency. It measures an energy efficiency of 24.8fJ/conv-step and occupies an active area of 2850um2, which are the highest reported energy efficiency and smallest area consumption among the state-of-the-art ADCs with> 10GS/s [7].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"73 1","pages":"160-162"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90521068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731713
Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi
To generate low-jitter, high-frequency signals with ring oscillators (ROs), injection-locked clock multipliers (ILCMs) are the most suitable architecture due to advantages such wide bandwidth and fewer noise sources. However, they have two inherent issues. The first is that their jitter performance is sensitive to PVT variations. To address this problem, recent RO-ILCMs have been equipped with a multi-purpose, real-time digital calibrator that can remove both the frequency error of the RO and the phase error of the calibrator [1]–[2]. The second is that their operational stability and jitter performance degrade rapidly as the multiplication factor, N, increases. This issue, which has yet to be well addressed, is rooted in the fundamental limitation of the typical injection-locking method, i.e., injecting narrow pulses into the RO (top left of Fig. 13.2.1). When the free-running frequency of the RO deviates from the target frequency, $Nf_{text{REF}}$, where $f_{text{REF}}$ is the frequency of the reference clock $(mathcal{S}_{text{REF}})$, the core current of the RO $(I_{text{osc}})$ and the $text{injecting}$ current $(I_{text{INJ}})$ should be out of phase to satisfy the oscillation condition by creating the necessary phase shift. Thus, the effective magnitude of $I_{text{INJ}}$ at $N f_{text {REF, }} text {i.e}., I_{text{INJ,eff }}$, relative to $l_{text{osc}}$ determines the maximum phase angle, $phi_{text{MAX}}$, and, thus, the maximum lock range, $omega_{mathrm{L},text{MAX}}$ [3]. However, for a large $N, I_{text{INJ,eff} }$ becomes extremely small, sharply reducing $phi_{text{MAX}}$ and $omega_{mathrm{L},text{MAX}}$. Although the RO-ILCMs in [4]–[5] achieved a total $N$ of over 40 by using a reference doubler or quadrupler, their two-stage operation offers limited improvement of the jitter $text{FoM}$. MDLL-based implementations are better suited for larger N, but the time required for edge switching limits the maximum output frequency, $f_{text{OUT}}$, and the value of N.
{"title":"A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator","authors":"Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi","doi":"10.1109/ISSCC42614.2022.9731713","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731713","url":null,"abstract":"To generate low-jitter, high-frequency signals with ring oscillators (ROs), injection-locked clock multipliers (ILCMs) are the most suitable architecture due to advantages such wide bandwidth and fewer noise sources. However, they have two inherent issues. The first is that their jitter performance is sensitive to PVT variations. To address this problem, recent RO-ILCMs have been equipped with a multi-purpose, real-time digital calibrator that can remove both the frequency error of the RO and the phase error of the calibrator [1]–[2]. The second is that their operational stability and jitter performance degrade rapidly as the multiplication factor, N, increases. This issue, which has yet to be well addressed, is rooted in the fundamental limitation of the typical injection-locking method, i.e., injecting narrow pulses into the RO (top left of Fig. 13.2.1). When the free-running frequency of the RO deviates from the target frequency, $Nf_{text{REF}}$, where $f_{text{REF}}$ is the frequency of the reference clock $(mathcal{S}_{text{REF}})$, the core current of the RO $(I_{text{osc}})$ and the $text{injecting}$ current $(I_{text{INJ}})$ should be out of phase to satisfy the oscillation condition by creating the necessary phase shift. Thus, the effective magnitude of $I_{text{INJ}}$ at $N f_{text {REF, }} text {i.e}., I_{text{INJ,eff }}$, relative to $l_{text{osc}}$ determines the maximum phase angle, $phi_{text{MAX}}$, and, thus, the maximum lock range, $omega_{mathrm{L},text{MAX}}$ [3]. However, for a large $N, I_{text{INJ,eff} }$ becomes extremely small, sharply reducing $phi_{text{MAX}}$ and $omega_{mathrm{L},text{MAX}}$. Although the RO-ILCMs in [4]–[5] achieved a total $N$ of over 40 by using a reference doubler or quadrupler, their two-stage operation offers limited improvement of the jitter $text{FoM}$. MDLL-based implementations are better suited for larger N, but the time required for edge switching limits the maximum output frequency, $f_{text{OUT}}$, and the value of N.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90585256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many PLLs, including those used for mm-wave 5G communications, require deep-sub-picosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a recent trend in addressing this problem [2]–[4]. They are composed of two stages: the 1st stage (PLL #1) receives an external frequency reference FREF to generate a filtered reference of several GHz feeding into the 2nd stage (PLL #2) that features a lower division ratio and a wide bandwidth for better overall jitter performance. Although the cascaded PLL can chose from various combinations of oscillators, e.g., LC-tank and ring-oscillator (RO), the PLL #2 using an RO can benefit from a small size, easy integration, wide frequency-tuning range (FTR), and multiphase clock outputs (e.g., for directly supporting multibeam antenna arrays). Normally, the RO-PLL cannot achieve the same jitter performance as an LC-PLL, but here a low value of $N$ in the wide-bandwidth integer-N configuration of PLL #2 makes this distinction less relevant.
{"title":"A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur","authors":"Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Yaopei Chang, Chih-Hsien Chang, R. Staszewski","doi":"10.1109/ISSCC42614.2022.9731676","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731676","url":null,"abstract":"Many PLLs, including those used for mm-wave 5G communications, require deep-sub-picosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a recent trend in addressing this problem [2]–[4]. They are composed of two stages: the 1st stage (PLL #1) receives an external frequency reference FREF to generate a filtered reference of several GHz feeding into the 2nd stage (PLL #2) that features a lower division ratio and a wide bandwidth for better overall jitter performance. Although the cascaded PLL can chose from various combinations of oscillators, e.g., LC-tank and ring-oscillator (RO), the PLL #2 using an RO can benefit from a small size, easy integration, wide frequency-tuning range (FTR), and multiphase clock outputs (e.g., for directly supporting multibeam antenna arrays). Normally, the RO-PLL cannot achieve the same jitter performance as an LC-PLL, but here a low value of $N$ in the wide-bandwidth integer-N configuration of PLL #2 makes this distinction less relevant.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"963 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80316030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731113
Sina Faraji Alamouti, Cem Yalcin, Jasmine Jan, Jonathan Ting, A. Arias, R. Muller
Low arterial blood oxygenation (SpO2) is a measure of hypoxemia and a sign of problems relating to breathing and circulation. Progressive drop in arterial SpO2 can be an early indicator of severe disease in COVID-19 patients [1]. A hypoxic state can occur rapidly and without a patient's knowledge; therefore, early detection of SpO2 decline can be lifesaving. In other respiratory system diseases such as COPD and sleep apnea, continuously monitoring of SpO2 with a pulse oximeter can enable timely diagnosis of oxygen desaturation. SpO2 is measured with Photoplethysmography (PPG) that uses a photodetector (PD) to detect either the transmission or reflection of light from the surface of the skin at two different light wavelengths. Commercial fingertip SpO2 sensors are not designed for chronic wear and require user intervention to trigger measurements. Alternatively, wearable SpO2 recording devices in the form of watches and rings can operate in the background with minimal user intervention. However, continuous acquisition of SpO2 can present a significant power burden to a wearable device since high-power LEDs must be powered on for each sample, dominating the power dissipation of the sensor. We present a low-power pulse oximeter sensor IC that utilizes sparse sampling to reduce the overall power by 70%.
{"title":"An SpO2 Sensor Using Reconstruction-Free Sparse Sampling for 70% System Power Reduction","authors":"Sina Faraji Alamouti, Cem Yalcin, Jasmine Jan, Jonathan Ting, A. Arias, R. Muller","doi":"10.1109/ISSCC42614.2022.9731113","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731113","url":null,"abstract":"Low arterial blood oxygenation (SpO2) is a measure of hypoxemia and a sign of problems relating to breathing and circulation. Progressive drop in arterial SpO2 can be an early indicator of severe disease in COVID-19 patients [1]. A hypoxic state can occur rapidly and without a patient's knowledge; therefore, early detection of SpO2 decline can be lifesaving. In other respiratory system diseases such as COPD and sleep apnea, continuously monitoring of SpO2 with a pulse oximeter can enable timely diagnosis of oxygen desaturation. SpO2 is measured with Photoplethysmography (PPG) that uses a photodetector (PD) to detect either the transmission or reflection of light from the surface of the skin at two different light wavelengths. Commercial fingertip SpO2 sensors are not designed for chronic wear and require user intervention to trigger measurements. Alternatively, wearable SpO2 recording devices in the form of watches and rings can operate in the background with minimal user intervention. However, continuous acquisition of SpO2 can present a significant power burden to a wearable device since high-power LEDs must be powered on for each sample, dominating the power dissipation of the sensor. We present a low-power pulse oximeter sensor IC that utilizes sparse sampling to reduce the overall power by 70%.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"44 1","pages":"344-346"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78955280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：