Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731627
Shuji Yamamura, Yasunobu Akizuki, Hideyuki Sekiguchi, T. Maruyama, Tsutomu Sano, Hiroyuki Miyazaki, Toshio Yoshida
In supercomputing, high-performance computing (HPC) applications require large amounts of parallel-processing capability and high memory bandwidth. Recently, artificial intelligence (AI) applications, which have characteristics similar to HPC applications, have played an important role in supercomputers. The supercomputer Fugaku [1] has a large number of general-purpose processors for a high-performance, high-density, and high-reliability implementation, as well as low power consumption to realize a massively parallel system for multiple applications targeting HPC and AI.
{"title":"A64FX: 52-Core Processor Designed for the 442PetaFLOPS Supercomputer Fugaku","authors":"Shuji Yamamura, Yasunobu Akizuki, Hideyuki Sekiguchi, T. Maruyama, Tsutomu Sano, Hiroyuki Miyazaki, Toshio Yoshida","doi":"10.1109/ISSCC42614.2022.9731627","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731627","url":null,"abstract":"In supercomputing, high-performance computing (HPC) applications require large amounts of parallel-processing capability and high memory bandwidth. Recently, artificial intelligence (AI) applications, which have characteristics similar to HPC applications, have played an important role in supercomputers. The supercomputer Fugaku [1] has a large number of general-purpose processors for a high-performance, high-density, and high-reliability implementation, as well as low power consumption to realize a massively parallel system for multiple applications targeting HPC and AI.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"65 1","pages":"352-354"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82246503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731620
{"title":"Session 19 Overview: Power Amplifiers and Building Blocks","authors":"","doi":"10.1109/isscc42614.2022.9731620","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731620","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83484346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731791
Wei-Hao Sun, Shih-Hsiung Chien, T. Kuo
Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power $(mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}})$ are desired. However, in mobile devices, the $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ is limited since Li-ion batteries operate at 3 to 4.2V. To increase $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$, prior publications [1]–[3] have developed embedded boost converters to regulate boosted supply voltage $mathrm{V}_{mathrm{P}mathrm{V}mathrm{D}mathrm{D}}$ to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency $mathrm{f}_{mathrm{S}mathrm{W},text{Class}}$) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ regions. In the $mathrm{l}mathrm{o}mathrm{w}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the $text{high}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region. As such, the maximum $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ with THD+N<1 % is decreased, which squanders the boosted $mathrm{V}_{mathrm{P}mathrm{V}mathrm{D}mathrm{D}}$. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the $mathrm{l}mathrm{o}mathrm{w}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region. As for the $text{medium}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.
{"title":"A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM","authors":"Wei-Hao Sun, Shih-Hsiung Chien, T. Kuo","doi":"10.1109/ISSCC42614.2022.9731791","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731791","url":null,"abstract":"Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power $(mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}})$ are desired. However, in mobile devices, the $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ is limited since Li-ion batteries operate at 3 to 4.2V. To increase $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$, prior publications [1]–[3] have developed embedded boost converters to regulate boosted supply voltage $mathrm{V}_{mathrm{P}mathrm{V}mathrm{D}mathrm{D}}$ to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency $mathrm{f}_{mathrm{S}mathrm{W},text{Class}}$) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ regions. In the $mathrm{l}mathrm{o}mathrm{w}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the $text{high}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region. As such, the maximum $mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ with THD+N<1 % is decreased, which squanders the boosted $mathrm{V}_{mathrm{P}mathrm{V}mathrm{D}mathrm{D}}$. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the $mathrm{l}mathrm{o}mathrm{w}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region. As for the $text{medium}-mathrm{P}_{mathrm{O}mathrm{U}mathrm{T}}$ region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"486-488"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79343137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731697
Data converters provide the gateway between the analog and digital worlds. They play a critical role in a vast range of systems, and integrated converters represent a central and growing element in high performance designs in applications from wireline to wireless and more. In this course, we start with an introduction to data converters, discussing key topologies, metrics, and the associated trade space. We continue with a discussion of ultra-high data rate converter design approaches before moving to high precision and low power converter topics. In our final session, we discuss emerging data converter concepts that will shape the future of research in this area.
{"title":"Short Course: High Speed/High Performance Data Converters: Metrics, Architectures, and Emerging Topics","authors":"","doi":"10.1109/ISSCC42614.2022.9731697","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731697","url":null,"abstract":"Data converters provide the gateway between the analog and digital worlds. They play a critical role in a vast range of systems, and integrated converters represent a central and growing element in high performance designs in applications from wireline to wireless and more. In this course, we start with an introduction to data converters, discussing key topologies, metrics, and the associated trade space. We continue with a discussion of ultra-high data rate converter design approaches before moving to high precision and low power converter topics. In our final session, we discuss emerging data converter concepts that will shape the future of research in this area.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"126 1","pages":"567-568"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79521228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731108
Linghan Zhang, M. Babaie
Digital beamforming receivers (RXs) support MIMO operation and offer great flexibility and accuracy in multi-beam formation and calibration. However, compared with analog phased-array and hybrid systems, due to the absence of any rejection for spatial in-band blockers, the $text{RX}/text{ADC}$ dynamic range and linearity should be high enough to prevent array saturation. Therefore, the use of self-steering spatial notch filters (SNFs) is necessary to aid the digital beamformers and reduce RX/ADC power consumption while strong blockers exist. To address that, the sub-6GHz RXs in [1], [2] synthesize a baseband spatial notch impedance and translate it to RF by passive mixers. However, this technique cannot be directly applied at mm-wave frequencies as the impedance translational performance of the passive mixers degrades significantly. Hence, the mm-wave beamformer in [3] realizes a cascadable SNF at an intermediate frequency (IF). However, the front-end mm-wave components like mixers and phase shifters have to tolerate strong blockers, thus degrading RX linearity. Besides, it uses multiple IF buffers and VGAs for signal scaling and combining, which could be power-hungry if a similar method is adopted to realize a mm-wave SNF. To improve on those limitations, we propose a scalable SNF structure, which (1) suppresses the strongest in-band blocker at mm-wave frequencies, (2) supports N-input-N-output MIMOs, and (3) requires no active blocks except the phase shifters. A two-step autonomous notch-steering technique is also developed to adjust the SNF notch direction power-efficiently and accurately.
{"title":"A 23-to-29GHz Receiver with mm-Wave N-Input-N-Output Spatial Notch Filtering and Autonomous Notch-Steering Achieving 20-to-40dB mm-Wave Spatial Rejection and -14dBm In-Notch IP1 dB","authors":"Linghan Zhang, M. Babaie","doi":"10.1109/ISSCC42614.2022.9731108","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731108","url":null,"abstract":"Digital beamforming receivers (RXs) support MIMO operation and offer great flexibility and accuracy in multi-beam formation and calibration. However, compared with analog phased-array and hybrid systems, due to the absence of any rejection for spatial in-band blockers, the $text{RX}/text{ADC}$ dynamic range and linearity should be high enough to prevent array saturation. Therefore, the use of self-steering spatial notch filters (SNFs) is necessary to aid the digital beamformers and reduce RX/ADC power consumption while strong blockers exist. To address that, the sub-6GHz RXs in [1], [2] synthesize a baseband spatial notch impedance and translate it to RF by passive mixers. However, this technique cannot be directly applied at mm-wave frequencies as the impedance translational performance of the passive mixers degrades significantly. Hence, the mm-wave beamformer in [3] realizes a cascadable SNF at an intermediate frequency (IF). However, the front-end mm-wave components like mixers and phase shifters have to tolerate strong blockers, thus degrading RX linearity. Besides, it uses multiple IF buffers and VGAs for signal scaling and combining, which could be power-hungry if a similar method is adopted to realize a mm-wave SNF. To improve on those limitations, we propose a scalable SNF structure, which (1) suppresses the strongest in-band blocker at mm-wave frequencies, (2) supports N-input-N-output MIMOs, and (3) requires no active blocks except the phase shifters. A two-step autonomous notch-steering technique is also developed to adjust the SNF notch direction power-efficiently and accurately.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"16 1 1","pages":"82-84"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78615468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731587
{"title":"F1: Compute-in-X (CiX): Overcoming the Data Bottleneck in AI Processing","authors":"","doi":"10.1109/isscc42614.2022.9731587","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731587","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"9 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80861139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731575
H. Shanan, D. Dalton, V. Chillara, P. Dato
At the center of autonomous driving and range and motion sensing in industrial and healthcare applications are FMCW RADARs, which provide the means for object range and velocity estimation. With future widespread use and availability of more bandwidth for RADAR systems, FMCW generators with short chirp duration and low phase noise will be important to reduce the RADAR doppler-induced range ambiguity and improve its resolution of close targets in multi-target environments. Due to the conflicting tradeoffs between bandwidth and low phase noise, PLLs with two-point modulation (TPM) are commonly used. The TPM architecture suffers from 2 main drawbacks: 1) In analog implementations [1, 2], it requires a low-noise DAC to inject a modulation signal in the sensitive tuning port of the VCO degrading phase noise, 2) Due to the finite matching between the high- and low-pass paths of the PLL, it introduces FM errors, which degrade the linearity of the generated chirps and require calibration. This is true for analog and digital implementations [3]. This work presents a FMCW modulator using an RTWO-based ADPLL to alleviate the phase-noise-versus-settling-time limitations of conventional PLL architectures. It generates sawtooth chirps with slopes up to 65MHz/μs, 2μs settling time, 12.5ns chirp retrace time, and 37kHz rms FM error. This is while achieving phase noise of -120dBc/Hz at a 1MHz offset from a 10GHz RF carrier.
{"title":"A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time","authors":"H. Shanan, D. Dalton, V. Chillara, P. Dato","doi":"10.1109/ISSCC42614.2022.9731575","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731575","url":null,"abstract":"At the center of autonomous driving and range and motion sensing in industrial and healthcare applications are FMCW RADARs, which provide the means for object range and velocity estimation. With future widespread use and availability of more bandwidth for RADAR systems, FMCW generators with short chirp duration and low phase noise will be important to reduce the RADAR doppler-induced range ambiguity and improve its resolution of close targets in multi-target environments. Due to the conflicting tradeoffs between bandwidth and low phase noise, PLLs with two-point modulation (TPM) are commonly used. The TPM architecture suffers from 2 main drawbacks: 1) In analog implementations [1, 2], it requires a low-noise DAC to inject a modulation signal in the sensitive tuning port of the VCO degrading phase noise, 2) Due to the finite matching between the high- and low-pass paths of the PLL, it introduces FM errors, which degrade the linearity of the generated chirps and require calibration. This is true for analog and digital implementations [3]. This work presents a FMCW modulator using an RTWO-based ADPLL to alleviate the phase-noise-versus-settling-time limitations of conventional PLL architectures. It generates sawtooth chirps with slopes up to 65MHz/μs, 2μs settling time, 12.5ns chirp retrace time, and 37kHz rms FM error. This is while achieving phase noise of -120dBc/Hz at a 1MHz offset from a 10GHz RF carrier.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"19 1","pages":"146-148"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75164059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731644
Yasuharu Ota, K. Morimoto, T. Sasago, Mahito Shinohara, Y. Kuroda, Wataru Endo, Y. Maehashi, Shintaro Maekawa, Hiroyuki Tsuchiya, Aymantarek Abdelahafar, Shingo Hikosaka, Masanao Motoyama, Kenzo Tojima, Kosei Uehira, Junji Iwata, F. Inui, Y. Matsuno, Katsuhito Sakurai, T. Ichikawa
Demands for single-photon-sensitive high-dynamic-range (HDR) imaging in security, automotive, and medical applications have driven development of scalable single-photon avalanche diode (SPAD)-based image sensors. In recent years, 3D-stacking technology combined with advanced CMOS processes has enabled pixel-parallel photon counting in sub-10µm SPAD pixels. A major technical challenge in realizing high-definition SPAD image sensors lies in a trade-off between power consumption and dynamic range (DR). SPAD pixels inherently consume a considerable amount of power due to the high-voltage operation and high current gain. Power consumption from the SPAD array (PSPAD) grows significantly with increasing incident photon flux, and often dominates over that from the readout circuit under high light conditions. Restricting maximum photon counts per frame could suppress the maximum PSPAD, at the expense of DR. To address this issue, a recharging circuit architecture must be carefully considered. Passive recharging has been widely employed for HDR imaging SPADs [1]–[3], but it is not a viable option for megapixel implementation due to the huge PSPAD, typically reaching tens of watts at excess illuminance. A clocked recharging architecture provides a scalable solution thanks to its compact circuitry and greatly reduced PSPAD at excess illuminance [4]–[6], but to date no existing SPAD sensor has simultaneously achieved megapixel resolution, sub-watt total power consumption, and > 120dB DR.
{"title":"A 0.37W 143dB-Dynamic-Range 1Mpixel Backside-Illuminated Charge-Focusing SPAD Image Sensor with Pixel-Wise Exposure Control and Adaptive Clocked Recharging","authors":"Yasuharu Ota, K. Morimoto, T. Sasago, Mahito Shinohara, Y. Kuroda, Wataru Endo, Y. Maehashi, Shintaro Maekawa, Hiroyuki Tsuchiya, Aymantarek Abdelahafar, Shingo Hikosaka, Masanao Motoyama, Kenzo Tojima, Kosei Uehira, Junji Iwata, F. Inui, Y. Matsuno, Katsuhito Sakurai, T. Ichikawa","doi":"10.1109/ISSCC42614.2022.9731644","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731644","url":null,"abstract":"Demands for single-photon-sensitive high-dynamic-range (HDR) imaging in security, automotive, and medical applications have driven development of scalable single-photon avalanche diode (SPAD)-based image sensors. In recent years, 3D-stacking technology combined with advanced CMOS processes has enabled pixel-parallel photon counting in sub-10µm SPAD pixels. A major technical challenge in realizing high-definition SPAD image sensors lies in a trade-off between power consumption and dynamic range (DR). SPAD pixels inherently consume a considerable amount of power due to the high-voltage operation and high current gain. Power consumption from the SPAD array (PSPAD) grows significantly with increasing incident photon flux, and often dominates over that from the readout circuit under high light conditions. Restricting maximum photon counts per frame could suppress the maximum PSPAD, at the expense of DR. To address this issue, a recharging circuit architecture must be carefully considered. Passive recharging has been widely employed for HDR imaging SPADs [1]–[3], but it is not a viable option for megapixel implementation due to the huge PSPAD, typically reaching tens of watts at excess illuminance. A clocked recharging architecture provides a scalable solution thanks to its compact circuitry and greatly reduced PSPAD at excess illuminance [4]–[6], but to date no existing SPAD sensor has simultaneously achieved megapixel resolution, sub-watt total power consumption, and > 120dB DR.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"13 1","pages":"94-96"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72690748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731716
Kodai Ueyoshi, I. Papistas, Pouya Houshmand, G. M. Sarda, V. Jain, Man Shi, Qilin Zheng, Sebastian Giraldo, Peter Vrancx, J. Doevenspeck, Debjyoti Bhattacharjee, S. Cosemans, A. Mallik, P. Debacker, D. Verkest, M. Verhelst
Energy-efficient matrix-vector multiplications (MVMs) are key to bringing neural network (NN) inference to edge devices. This has led to a wide range of state-of-the-art MVM acceleration chips, which fall into two categories: 1) Digital NN accelerators [1]–[2], constituting widely parallel multiply-accumulate (MAC) arrays at medium (typically 4-8b) precision. 2) Analog in-memory compute (AiMC) NN accelerators [3]–[4], which enable much higher energy efficiencies and throughput per unit area at the cost of a reduced computational precision, reduced dataflow flexibility, and resulting reduced mapping efficiency for some layer configurations. Neither of these approaches dominates the other, as it depends on the layer type which approach is the optimal. The ideal processor would enable exploiting both digital and AiMC NN acceleration concepts and select the best accelerator depending on the layer characteristics. Consequently, this work presents DIANA, a low-power NN processing SoC, comprising a precision-scalable digital NN accelerator, an AiMC core, an optimized shared-memory subsystem and a RISC-V host processor to achieve SOTA end-to-end inference at the edge. This SoC includes innovations in: a) its 16x16 digital NN core with flexible dataflow for fully connected and high-precision CONV layer execution, b) its 1152x512 AiMC core with SIMD digital post-processing and support for output unrolling for improving array utilization, and c) a shared memory system supporting efficient layer-fused execution schedules, controlled by the RISC-V. This allows simultaneous execution of subsequent layers across the digital and analog cores, assigning high-precision layers and layers with limited AiMC utilization (e.g. FC layers and layers with low channel count) to the digital core, and all other intermediate layers to the AiMC core. A top-level overview of the designed system and its highlights is depicted in Fig. 15.6.1.
{"title":"DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC","authors":"Kodai Ueyoshi, I. Papistas, Pouya Houshmand, G. M. Sarda, V. Jain, Man Shi, Qilin Zheng, Sebastian Giraldo, Peter Vrancx, J. Doevenspeck, Debjyoti Bhattacharjee, S. Cosemans, A. Mallik, P. Debacker, D. Verkest, M. Verhelst","doi":"10.1109/ISSCC42614.2022.9731716","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731716","url":null,"abstract":"Energy-efficient matrix-vector multiplications (MVMs) are key to bringing neural network (NN) inference to edge devices. This has led to a wide range of state-of-the-art MVM acceleration chips, which fall into two categories: 1) Digital NN accelerators [1]–[2], constituting widely parallel multiply-accumulate (MAC) arrays at medium (typically 4-8b) precision. 2) Analog in-memory compute (AiMC) NN accelerators [3]–[4], which enable much higher energy efficiencies and throughput per unit area at the cost of a reduced computational precision, reduced dataflow flexibility, and resulting reduced mapping efficiency for some layer configurations. Neither of these approaches dominates the other, as it depends on the layer type which approach is the optimal. The ideal processor would enable exploiting both digital and AiMC NN acceleration concepts and select the best accelerator depending on the layer characteristics. Consequently, this work presents DIANA, a low-power NN processing SoC, comprising a precision-scalable digital NN accelerator, an AiMC core, an optimized shared-memory subsystem and a RISC-V host processor to achieve SOTA end-to-end inference at the edge. This SoC includes innovations in: a) its 16x16 digital NN core with flexible dataflow for fully connected and high-precision CONV layer execution, b) its 1152x512 AiMC core with SIMD digital post-processing and support for output unrolling for improving array utilization, and c) a shared memory system supporting efficient layer-fused execution schedules, controlled by the RISC-V. This allows simultaneous execution of subsequent layers across the digital and analog cores, assigning high-precision layers and layers with limited AiMC utilization (e.g. FC layers and layers with low channel count) to the digital core, and all other intermediate layers to the AiMC core. A top-level overview of the designed system and its highlights is depicted in Fig. 15.6.1.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82108902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731764
Chen Chen, Jin Liu, Hoi Lee
With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conversion ratio (CR), the conventional buck (CB) converters suffer from extremely short switch on-time that limits high-frequency operation and incurs high power losses. Although the switched-capacitor (SC) converters with lower voltage rating devices can scale down the high input voltage, $mathsf{V}_{mathsf{lN}}$, high efficiency can only be achieved under fixed conversion ratios. Hybrid converters are thus emerged recently to combine the advantages of CB and SC converters. Converter topologies such as flying-capacitor multi-level (FCML) [1] and hybrid Dickson (HD) [2] adopt an external output LC filter after the SC network to realize continuous conversion range. However, since flying capacitor in [1] and [2] requires proper voltage balancing in the steady state, the switching frequency, $mathsf{f}_{mathsf{SW}}$, can be significantly slowed down when the converter needs to balance an increased number of the flying capacitor under small CR condition. Both double step-down (DSD) [3] and tri-state DSD [4] topologies can double $mathsf{f}_{mathsf{SW}}$ by using two inductors, but their CR is only $mathsf{D}/2$ that limits their capability to support 48V-to-1V conversions. Although the 12-level series-capacitor converter [5] topology significantly decreases the CR, it requires 11 flying capacitors and a $mathsf{GaN}$ FET as external components. The converter also has 24 on-chip power transistors to support 12-phase operation, resulting in a large chip area.
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