Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731613
{"title":"Session 15 Overview: ML Processors","authors":"","doi":"10.1109/isscc42614.2022.9731613","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731613","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"27 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89668000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731731
Sam Razavian, A. Babakhani
Efficient THz generation in silicon technologies has been of great interest over the recent years, as it enables an integrated low-cost solution for sensing, radar, communication, and spectroscopy [1]. Due to the limited $mathrm{f}_{mathrm{T}}/mathrm{f}_{max}$ of transistors, direct THz generation using a fundamental oscillator is not feasible; therefore, various approaches have been developed based on harmonic extraction and the frequency multiplication of a fundamental oscillator [2]. In these techniques, the nonlinearity of transistors is utilized to generate higher harmonics from a fundamental oscillator or frequency-multiplier cells; however, such systems have a poor efficiency and low radiated power due to device limitations. To compensate for the low generated power, a coherent array scheme is preferred to increase EI RP and radiated power. Adjusting the phase and locking the frequency of elements for coherent operation are important factors in array architectures, which can be performed through central LO distribution [3] and mutual coupling [4]. LO distribution can cause phase mismatch between elements and significantly increases the DC power consumption by adding more blocks. Mutual coupling through injection locking can maintain phase alignment. However, this type of coupling has low tuning range, which makes it challenging to synchronize elements over a broad frequency range. In this work, a technique for THz CW generation is presented, in which, instead of relying on transistor nonlinearity, a PIN diode is used in the reverse recovery mode for strong harmonic generation. A PIN diode, similar to a step recovery diode (SRD), benefits from a sharp reverse recovery and is highly nonlinear in the recovery mode, which enables efficient THz harmonic generation by upconverting the output of a mm-wave oscillator without requiring additional blocks and multipliers. The PIN-based array consists of 2x3 elements, where differential Colpitts oscillators are used as the core to push the PIN diodes into reverse recovery. Array elements are intercoupled using a collective coupling approach that enables wide tuning range and phase match between elements. The PIN-based array achieves a radiated power of 0.31 mW and 18.1dBm EIRP at 425GHz.
{"title":"A Highly Power Efficient 2×3 PIN-Diode-Based Intercoupled THz Radiating Array at 425GHz with 18.1dBm EIRP in 90nm SiGe BiCMOS","authors":"Sam Razavian, A. Babakhani","doi":"10.1109/ISSCC42614.2022.9731731","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731731","url":null,"abstract":"Efficient THz generation in silicon technologies has been of great interest over the recent years, as it enables an integrated low-cost solution for sensing, radar, communication, and spectroscopy [1]. Due to the limited $mathrm{f}_{mathrm{T}}/mathrm{f}_{max}$ of transistors, direct THz generation using a fundamental oscillator is not feasible; therefore, various approaches have been developed based on harmonic extraction and the frequency multiplication of a fundamental oscillator [2]. In these techniques, the nonlinearity of transistors is utilized to generate higher harmonics from a fundamental oscillator or frequency-multiplier cells; however, such systems have a poor efficiency and low radiated power due to device limitations. To compensate for the low generated power, a coherent array scheme is preferred to increase EI RP and radiated power. Adjusting the phase and locking the frequency of elements for coherent operation are important factors in array architectures, which can be performed through central LO distribution [3] and mutual coupling [4]. LO distribution can cause phase mismatch between elements and significantly increases the DC power consumption by adding more blocks. Mutual coupling through injection locking can maintain phase alignment. However, this type of coupling has low tuning range, which makes it challenging to synchronize elements over a broad frequency range. In this work, a technique for THz CW generation is presented, in which, instead of relying on transistor nonlinearity, a PIN diode is used in the reverse recovery mode for strong harmonic generation. A PIN diode, similar to a step recovery diode (SRD), benefits from a sharp reverse recovery and is highly nonlinear in the recovery mode, which enables efficient THz harmonic generation by upconverting the output of a mm-wave oscillator without requiring additional blocks and multipliers. The PIN-based array consists of 2x3 elements, where differential Colpitts oscillators are used as the core to push the PIN diodes into reverse recovery. Array elements are intercoupled using a collective coupling approach that enables wide tuning range and phase match between elements. The PIN-based array achieves a radiated power of 0.31 mW and 18.1dBm EIRP at 425GHz.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89676895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731557
Xi Fu, Yun Wang, Dongwon You, Xiaolin Wang, A. Fadila, Yi Zhang, Sena Kato, Chun Wang, Zheng Li, Jian Pang, A. Shirane, K. Okada
Low-Earth-Orbit (LEO) satellite constellations have been demonstrated as a ground breaking technology for providing low-cost low-latency global internet access. However, each satellite needs more than 200kg launch mass due to bulky wireless components and solar cells, which raises a serious cost issue. One possible solution is further minimizing satellite mass, such as cube satellites, by realizing an ultra-low-power Kaband phased-array transceiver. In this work, 1W power consumption is targeted for a 256-element Ka-band phased-array receiver, i.e. 4mW per element. In the conventional geostationary communication satellites, a parabolic antenna is utilized, and a transceiver module is placed inside a metallic cavity so it can tolerate cosmic radiation. On the other hand, LEO satellites need beam-steering functionality by using a phased-array antenna, and only a thin shield layer can be inserted between antennas and ICs for avoiding redundant mass and insertion loss. Thus, the radiation-hardening and low power consumption are key requirements for such cube satellite phased arrays. For RF building blocks in a phased array, the total ionizing dose (TID) is more critical than the single event effects (SEE). Figure 4.8.1 shows an estimated result for non-radiation-hardened design regarding TID degradation on beam pattern, resulting in 3.8dB main-lobe degradation. In this work, 2.7Mrad TID tolerance is considered adequate for a 3-year lifespan with a 24pm PCB copper shield. Figure 4.8.1 also summarizes the system requirements for a phased-array satellite receiver.
{"title":"A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation","authors":"Xi Fu, Yun Wang, Dongwon You, Xiaolin Wang, A. Fadila, Yi Zhang, Sena Kato, Chun Wang, Zheng Li, Jian Pang, A. Shirane, K. Okada","doi":"10.1109/ISSCC42614.2022.9731557","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731557","url":null,"abstract":"Low-Earth-Orbit (LEO) satellite constellations have been demonstrated as a ground breaking technology for providing low-cost low-latency global internet access. However, each satellite needs more than 200kg launch mass due to bulky wireless components and solar cells, which raises a serious cost issue. One possible solution is further minimizing satellite mass, such as cube satellites, by realizing an ultra-low-power Kaband phased-array transceiver. In this work, 1W power consumption is targeted for a 256-element Ka-band phased-array receiver, i.e. 4mW per element. In the conventional geostationary communication satellites, a parabolic antenna is utilized, and a transceiver module is placed inside a metallic cavity so it can tolerate cosmic radiation. On the other hand, LEO satellites need beam-steering functionality by using a phased-array antenna, and only a thin shield layer can be inserted between antennas and ICs for avoiding redundant mass and insertion loss. Thus, the radiation-hardening and low power consumption are key requirements for such cube satellite phased arrays. For RF building blocks in a phased array, the total ionizing dose (TID) is more critical than the single event effects (SEE). Figure 4.8.1 shows an estimated result for non-radiation-hardened design regarding TID degradation on beam pattern, resulting in 3.8dB main-lobe degradation. In this work, 2.7Mrad TID tolerance is considered adequate for a 3-year lifespan with a 24pm PCB copper shield. Figure 4.8.1 also summarizes the system requirements for a phased-array satellite receiver.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"6 1","pages":"90-92"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90301439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731688
N. Kocaman, U. Singh, Bharath Raghavan, Arvindh Lyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, J. Jeong, Heng Zhang, Anand Vasani, Y. Shim, Z. Huang, A. Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, M. Caresosa, Bo Zhang, A. Momtaz
With the COVID–19 pandemic, the faster and more reliable connectivity solutions in data centers became the critical enabler technology of our daily activities. The current 50G data center switches have more than 500 lanes within a single chip solution [1]. This massive integration puts strict restrictions on power/area consumption. Moreover, single-domain, low supply voltage operation is highly desirable for better package/board designs as well as improved silicon reliability with less aging impact. An ADC-based receiver with DSP equalization consumes higher power/area due to the time-interleaved ADC array and digital domain FFE/DFE taps [2]. An analog CTLE/DFE-based transceiver with a single supply level is highly suitable for low power/area operation for high density IOs in data center switches. The TX driver supply level can be adjusted based on the application.
{"title":"An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology","authors":"N. Kocaman, U. Singh, Bharath Raghavan, Arvindh Lyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, J. Jeong, Heng Zhang, Anand Vasani, Y. Shim, Z. Huang, A. Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, M. Caresosa, Bo Zhang, A. Momtaz","doi":"10.1109/ISSCC42614.2022.9731688","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731688","url":null,"abstract":"With the COVID–19 pandemic, the faster and more reliable connectivity solutions in data centers became the critical enabler technology of our daily activities. The current 50G data center switches have more than 500 lanes within a single chip solution [1]. This massive integration puts strict restrictions on power/area consumption. Moreover, single-domain, low supply voltage operation is highly desirable for better package/board designs as well as improved silicon reliability with less aging impact. An ADC-based receiver with DSP equalization consumes higher power/area due to the time-interleaved ADC array and digital domain FFE/DFE taps [2]. An analog CTLE/DFE-based transceiver with a single supply level is highly suitable for low power/area operation for high density IOs in data center switches. The TX driver supply level can be adjusted based on the application.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"120-122"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73560070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731793
Baibhab Chatterjee, Arunashish Datta, Mayukh Nath, K. G. Kumar, Nirmoy Modak, Shreyas Sen
Recent advances in audio-visual augmented reality (AR) and virtual reality (VR) demands 1) high speed (>10Mbps) data transfer among wearable devices around the human body with 2) low transceiver (TRX) power consumption for longer lifetime, especially as communication energy/b is often orders of magnitude higher than computation energy/switching. While WiFi can transmit compressed video (HD 30fps, compressed @6-12Mbps), it consumes 50-to-400mW power. Bluetooth, on the other hand, is not designed for video transfer. New mm-Wave links can support the required bandwidth but do not support ultra-low-power (<1mW). In recent years, Human-Body Communication (HBC) [1]–[6] has emerged as a promising low-power alternative to traditional wireless communication. However, previous implementations of HBC transmitters (Tx) suffer from a large plate-to-plate capacitance (Cp, between signal electrode and local ground of the transmitter) which results in a power consumption of aCpV2f (Fig. 16.6.1) in voltage-mode (VM) HBC. The recently proposed Resonant HBC [6] tries to overcome this problem by resonating Cp with a parallel inductor (L). However, the operating frequency is usually < a few 10's of MHz for low-power Electro-Quasistatic (EQS) operation, resulting in a large/bulky inductor. Moreover, the resonant LCp circuit has a large settling time (≈5Q2RCP, where R is the effective series resistance of the inductor) for EQS frequencies which will limit the maximum symbol rate to <1MSps for a 21MHz carrier (the IEEE 802.15.6 standard for HBC), making resonant HBC infeasible for> 10Mb/s applications.
{"title":"A 65nm 63.3µW 15Mbps Transceiver with Switched-Capacitor Adiabatic Signaling and Combinatorial-Pulse-Position Modulation for Body-Worn Video-Sensing AR Nodes","authors":"Baibhab Chatterjee, Arunashish Datta, Mayukh Nath, K. G. Kumar, Nirmoy Modak, Shreyas Sen","doi":"10.1109/ISSCC42614.2022.9731793","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731793","url":null,"abstract":"Recent advances in audio-visual augmented reality (AR) and virtual reality (VR) demands 1) high speed (>10Mbps) data transfer among wearable devices around the human body with 2) low transceiver (TRX) power consumption for longer lifetime, especially as communication energy/b is often orders of magnitude higher than computation energy/switching. While WiFi can transmit compressed video (HD 30fps, compressed @6-12Mbps), it consumes 50-to-400mW power. Bluetooth, on the other hand, is not designed for video transfer. New mm-Wave links can support the required bandwidth but do not support ultra-low-power (<1mW). In recent years, Human-Body Communication (HBC) [1]–[6] has emerged as a promising low-power alternative to traditional wireless communication. However, previous implementations of HBC transmitters (Tx) suffer from a large plate-to-plate capacitance (Cp, between signal electrode and local ground of the transmitter) which results in a power consumption of aCpV2f (Fig. 16.6.1) in voltage-mode (VM) HBC. The recently proposed Resonant HBC [6] tries to overcome this problem by resonating Cp with a parallel inductor (L). However, the operating frequency is usually < a few 10's of MHz for low-power Electro-Quasistatic (EQS) operation, resulting in a large/bulky inductor. Moreover, the resonant LCp circuit has a large settling time (≈5Q2RCP, where R is the effective series resistance of the inductor) for EQS frequencies which will limit the maximum symbol rate to <1MSps for a 21MHz carrier (the IEEE 802.15.6 standard for HBC), making resonant HBC infeasible for> 10Mb/s applications.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"7 1","pages":"276-278"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78570107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731668
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Jun Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
Since the advent of the Lottery Ticket Hypothesis [1], which advocates the existence of embedded sparse models that achieve accuracies equivalent to the original dense model, new algorithms to find such subnetworks have been attracting attention. In particular, Hidden Network (HNN) [2] proposed a training method that finds such accurate subnetworks (Fig. 15.4.1). HNN extracts the sparse subnetwork by taking a logical AND of an initial model's random weights and a binary mask that defines the selected connections - a supermask. The importance of each connection, quantified as a score, is evaluated in the training phase; a supermask is learned by picking the connections with the top-k% highest scores. Although similar to pruning, supermask training is clearly different in that it never updates the initial random weights.
{"title":"Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet","authors":"Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Jun Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura","doi":"10.1109/ISSCC42614.2022.9731668","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731668","url":null,"abstract":"Since the advent of the Lottery Ticket Hypothesis [1], which advocates the existence of embedded sparse models that achieve accuracies equivalent to the original dense model, new algorithms to find such subnetworks have been attracting attention. In particular, Hidden Network (HNN) [2] proposed a training method that finds such accurate subnetworks (Fig. 15.4.1). HNN extracts the sparse subnetwork by taking a logical AND of an initial model's random weights and a binary mask that defines the selected connections - a supermask. The importance of each connection, quantified as a score, is evaluated in the training phase; a supermask is learned by picking the connections with the top-k% highest scores. Although similar to pruning, supermask training is clearly different in that it never updates the initial random weights.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"28 4 Suppl 15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77859236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731702
Haoyi Zhao, F. Dai
The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requirement in subsequent stages. However, these amplifiers generally induce issues such as large power consumption, stringent linearity requirements, and PVT-sensitive gain errors [1], [4]. Moreover, reduced voltage dynamic range in deep submicron nodes presents challenges for the design of high-performance amplifiers and fine quantizers in voltage domain. Therefore, implementing the fine quantizer in time domain becomes attractive due to its better noise tolerance and lower power consumption. Nevertheless, the linearity and conversion speed of the time-to-digital converter (TDC) used as the fine quantizer degrades quickly with the increase of its resolution due to the exponentially increased hardware. Moreover, its full-scale and resolution are determined by the delay cells and are thus sensitive to PVT variations. In prior-art, the time-domain assisted SAR ADC [2] adopts a current-discharging-based inner-tracking technique in a voltage-to-time converter (VTC) and TDC to compensate PVT variations, yet the conversion speed is limited by slow conversions of the VTC and the TDC. The digital slope assisted SAR ADC [3] guarantees that the time full-scale is aligned with the LSB in the voltage-domain. However, the architecture doesn't fully exploit the benefits of time-domain conversion since the ADC resolution is still dependent on the unit-capacitor switching, leading to an enlarged MSB-to-LSB ratio in the CDAC
{"title":"A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment","authors":"Haoyi Zhao, F. Dai","doi":"10.1109/ISSCC42614.2022.9731702","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731702","url":null,"abstract":"The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requirement in subsequent stages. However, these amplifiers generally induce issues such as large power consumption, stringent linearity requirements, and PVT-sensitive gain errors [1], [4]. Moreover, reduced voltage dynamic range in deep submicron nodes presents challenges for the design of high-performance amplifiers and fine quantizers in voltage domain. Therefore, implementing the fine quantizer in time domain becomes attractive due to its better noise tolerance and lower power consumption. Nevertheless, the linearity and conversion speed of the time-to-digital converter (TDC) used as the fine quantizer degrades quickly with the increase of its resolution due to the exponentially increased hardware. Moreover, its full-scale and resolution are determined by the delay cells and are thus sensitive to PVT variations. In prior-art, the time-domain assisted SAR ADC [2] adopts a current-discharging-based inner-tracking technique in a voltage-to-time converter (VTC) and TDC to compensate PVT variations, yet the conversion speed is limited by slow conversions of the VTC and the TDC. The digital slope assisted SAR ADC [3] guarantees that the time full-scale is aligned with the LSB in the voltage-domain. However, the architecture doesn't fully exploit the benefits of time-domain conversion since the ADC resolution is still dependent on the unit-capacitor switching, leading to an enlarged MSB-to-LSB ratio in the CDAC","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"66 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77957358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731588
Renee James
From its emergence as a novel technology accessible to only a few experts, digital compute has developed into a pervasive tool in our daily lives. Explosive performance growth and dramatic cost reduction have unlocked access and enabled adoption by an expanding portion of the global populace. Today, compute is a utility: ubiquitous, woven into the fabric of our existence, and available as a scalable, metered resource.
{"title":"The Future of the High-Performance Semiconductor Industry and Design","authors":"Renee James","doi":"10.1109/ISSCC42614.2022.9731588","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731588","url":null,"abstract":"From its emergence as a novel technology accessible to only a few experts, digital compute has developed into a pervasive tool in our daily lives. Explosive performance growth and dramatic cost reduction have unlocked access and enabled adoption by an expanding portion of the global populace. Today, compute is a utility: ubiquitous, woven into the fabric of our existence, and available as a scalable, metered resource.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"37 2 1","pages":"32-35"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79388201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731633
Dragoljub Ignjatovic, Daniel W. Bailey, Ljubisa Bajić
Deep-Learning Artificial Intelligence is a hot and growing field, requiring a challenging mix of performance, power efficiency, programmability, scalability, and low price. Wormhole is an AI training processor directly targeted at this field, designed for high performance (TOPS and TFLOPS), software enablement, extreme scalability, and high performance-per-watt-per-dollar.
{"title":"The Wormhole AI Training Processor","authors":"Dragoljub Ignjatovic, Daniel W. Bailey, Ljubisa Bajić","doi":"10.1109/ISSCC42614.2022.9731633","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731633","url":null,"abstract":"Deep-Learning Artificial Intelligence is a hot and growing field, requiring a challenging mix of performance, power efficiency, programmability, scalability, and low price. Wormhole is an AI training processor directly targeted at this field, designed for high performance (TOPS and TFLOPS), software enablement, extreme scalability, and high performance-per-watt-per-dollar.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"12 1","pages":"356-358"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84320225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three major distortion sources in high-fidelity audio decoders are 1) DAC inter-symbol interference (ISI) [1], [2]; 2) 3rd-order harmonic distortion (HD3) due to the 2nd-order nonlinearity of poly resistors; and 3) Cross-over distortion (COD) arising from limited amplifier inner-loop gain due to high output load capacitance (CL) [3], [4]. First, to alleviate the ISI, [1] presents a Real-Time Dynamic-Element-Matching (RT-DEM) algorithm to realize mismatch shaping for DAC cells, achieving 115dB SFDR without complex digital hardware as in [2]. However, the constraint of 1-LSB change with the RT-DEM limits dynamic range (DR) of the $DeltaSigma$ modulator. Moreover, a high clock rate of 181 MHz causes a high power consumption. Second, with a large signal swing, the total harmonic distortion (THD) of current-to-voltage (I2V) amplifiers is frequently dominated by the HD3 in [1]–[5]. The potential cause of this HD3 is due to the velocity saturation effect (VSE) of poly resistors [6]. Lastly, for a large load capacitance, the damping-factor-control frequency compensation (DFCFC) is commonly applied in multi-stage amplifiers to enhance the stability [4], [5]. However, it degrades the amplifier inner-loop gain and causes severe COD. In [4], a compensation scheme inserts a gain stage inside the inner loop to boost the loop gain over the audio band (20Hz to 20kHz), suppressing the peak COD below −111 dBc. In this work, three techniques are presented to eliminate the aforementioned distortion sources: 1) a code-change-insensitive RT-DEM (CCI-RT-DEM) algorithm is introduced to dynamically select the new start index of rotated DAC cells for the next code, instead of the fixed index at the first one [1], thus allowing for more than 1-LSB change; 2) a poly-resistor linearization scheme is presented to suppress HD3 by mitigating the VSE of resistors; and 3) a 2nd-order DFCFC for multi-stage amplifiers is introduced that allows a high inner-loop gain to suppress the COD, thus enhancing the amplifier linearity even with a large CL. Combining these solutions, the DAC and amplifier together achieve −117dBc THD (−132dBc HD3) and 126dB DR.
{"title":"A −117dBc THD (−132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors","authors":"Shon-Hang Wen, C. Hsiao, Shih-Hsiung Chien, Ya-Chi Chen, Kuan-Hung Chen, Kuan-Dar Chen","doi":"10.1109/ISSCC42614.2022.9731634","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731634","url":null,"abstract":"Three major distortion sources in high-fidelity audio decoders are 1) DAC inter-symbol interference (ISI) [1], [2]; 2) 3rd-order harmonic distortion (HD3) due to the 2nd-order nonlinearity of poly resistors; and 3) Cross-over distortion (COD) arising from limited amplifier inner-loop gain due to high output load capacitance (CL) [3], [4]. First, to alleviate the ISI, [1] presents a Real-Time Dynamic-Element-Matching (RT-DEM) algorithm to realize mismatch shaping for DAC cells, achieving 115dB SFDR without complex digital hardware as in [2]. However, the constraint of 1-LSB change with the RT-DEM limits dynamic range (DR) of the $DeltaSigma$ modulator. Moreover, a high clock rate of 181 MHz causes a high power consumption. Second, with a large signal swing, the total harmonic distortion (THD) of current-to-voltage (I2V) amplifiers is frequently dominated by the HD3 in [1]–[5]. The potential cause of this HD3 is due to the velocity saturation effect (VSE) of poly resistors [6]. Lastly, for a large load capacitance, the damping-factor-control frequency compensation (DFCFC) is commonly applied in multi-stage amplifiers to enhance the stability [4], [5]. However, it degrades the amplifier inner-loop gain and causes severe COD. In [4], a compensation scheme inserts a gain stage inside the inner loop to boost the loop gain over the audio band (20Hz to 20kHz), suppressing the peak COD below −111 dBc. In this work, three techniques are presented to eliminate the aforementioned distortion sources: 1) a code-change-insensitive RT-DEM (CCI-RT-DEM) algorithm is introduced to dynamically select the new start index of rotated DAC cells for the next code, instead of the fixed index at the first one [1], thus allowing for more than 1-LSB change; 2) a poly-resistor linearization scheme is presented to suppress HD3 by mitigating the VSE of resistors; and 3) a 2nd-order DFCFC for multi-stage amplifiers is introduced that allows a high inner-loop gain to suppress the COD, thus enhancing the amplifier linearity even with a large CL. Combining these solutions, the DAC and amplifier together achieve −117dBc THD (−132dBc HD3) and 126dB DR.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"48 1","pages":"482-484"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84864998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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