Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731652
J. Steensgaard, R. Reay, Raymond T. Perry, Dave Thomas, Geoffrey Tu, G. Reitsma
This work aims at optimizing accuracy, noise, and power for low-to-medium speed applications. The ADC function accommodates a wide range of use, including Nyquist-rate data acquisition and oversampled signal applications. The noise spectral density (NSD) is uniform from 0Hz to $mathsf{Fs}/2=1 mathsf{MHz}$, and hence $mathsf{FoM}1= mathsf{DR} +10cdot log$ (BW/Power) is the same for any BW selected by decimation filtering or other DSP. The SNDR is within 1 dB of the DR for full-scale input tones at frequencies up to 100kHz, and hence $mathsf{FoM}2= mathsf{SNDR} +10cdotmathsf{log}$ (BW/Power) is similar to FoM1 for the primary use cases.
{"title":"A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS","authors":"J. Steensgaard, R. Reay, Raymond T. Perry, Dave Thomas, Geoffrey Tu, G. Reitsma","doi":"10.1109/ISSCC42614.2022.9731652","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731652","url":null,"abstract":"This work aims at optimizing accuracy, noise, and power for low-to-medium speed applications. The ADC function accommodates a wide range of use, including Nyquist-rate data acquisition and oversampled signal applications. The noise spectral density (NSD) is uniform from 0Hz to $mathsf{Fs}/2=1 mathsf{MHz}$, and hence $mathsf{FoM}1= mathsf{DR} +10cdot log$ (BW/Power) is the same for any BW selected by decimation filtering or other DSP. The SNDR is within 1 dB of the DR for full-scale input tones at frequencies up to 100kHz, and hence $mathsf{FoM}2= mathsf{SNDR} +10cdotmathsf{log}$ (BW/Power) is similar to FoM1 for the primary use cases.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"22 1","pages":"168-170"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78677476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731629
Adam Wang, Yuguo Sheng, Wanlu Li, Doohwan Jung, Gregory V. Junek, Jongseok Park, Dongwon Lee, Mian Wang, S. Maharjan, Sagar R. Kumashi, Jin Hao, Y. S. Zhang, K. Eggan, Hua Wang
With the recent pandemic, the necessity of digital physiology/pathology, a set of high-resolution cellular/tissue-level images uploaded to the cloud for remote analytics and diagnostics, has skyrocketed as in-person lab services are limited by processing throughputs and increased exposure risks to patients/medical professionals [1]–[2]. Presently, cellular physiology diagnoses rely on high-resolution medical imaging and when translated to a cellular/tissue-level, these images, albeit with different biomarkers, may not holistically characterize a pathogen's effect due to the cell's complex multi-physiological responses [3]. In particular, new pathogen/virus variants often exhibit unknown pathological effects on cellular physiological functions. Hence, desired digital physiology cellular platforms should support sensing a wide variety of cells under different conditions, including those with rapid physiological features, e.g., neuron/cardiac cells.
{"title":"A CMOS Cellular Interface Array for Digital Physiology Featuring High-Density Multi-Modal Pixels and Reconfigurable Sampling Rate","authors":"Adam Wang, Yuguo Sheng, Wanlu Li, Doohwan Jung, Gregory V. Junek, Jongseok Park, Dongwon Lee, Mian Wang, S. Maharjan, Sagar R. Kumashi, Jin Hao, Y. S. Zhang, K. Eggan, Hua Wang","doi":"10.1109/ISSCC42614.2022.9731629","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731629","url":null,"abstract":"With the recent pandemic, the necessity of digital physiology/pathology, a set of high-resolution cellular/tissue-level images uploaded to the cloud for remote analytics and diagnostics, has skyrocketed as in-person lab services are limited by processing throughputs and increased exposure risks to patients/medical professionals [1]–[2]. Presently, cellular physiology diagnoses rely on high-resolution medical imaging and when translated to a cellular/tissue-level, these images, albeit with different biomarkers, may not holistically characterize a pathogen's effect due to the cell's complex multi-physiological responses [3]. In particular, new pathogen/virus variants often exhibit unknown pathological effects on cellular physiological functions. Hence, desired digital physiology cellular platforms should support sensing a wide variety of cells under different conditions, including those with rapid physiological features, e.g., neuron/cardiac cells.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"231 1","pages":"202-204"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76437849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731606
C. Lee, U. Moon
Demands for battery-powered consumer electronics have driven the evolution of power-efficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery life and shrinking form-factors. Flicker noise poses an issue for such systems although the use of well-known techniques in state-of-the-art designs such as chopper stabilization [1]–[2] are often sufficient for its mitigation. Alternatively, the pseudo-pseudo-differential (PPD) architecture [3] has demonstrated flicker cancellation through the use of single-ended circuits although area and power savings promised by this technique remain undemonstrated. This paper presents a DT single-loop DSM audio ADC utilizing a single-ended ring-amplifier-based integrator to achieve 108.8dB DR with 203.5µW power consumption within a compact area of 0.0375mm2. The use of the PPD architecture with a merged adder contribute to this work's state-of-the-art power and area efficiency.
{"title":"A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS","authors":"C. Lee, U. Moon","doi":"10.1109/ISSCC42614.2022.9731606","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731606","url":null,"abstract":"Demands for battery-powered consumer electronics have driven the evolution of power-efficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery life and shrinking form-factors. Flicker noise poses an issue for such systems although the use of well-known techniques in state-of-the-art designs such as chopper stabilization [1]–[2] are often sufficient for its mitigation. Alternatively, the pseudo-pseudo-differential (PPD) architecture [3] has demonstrated flicker cancellation through the use of single-ended circuits although area and power savings promised by this technique remain undemonstrated. This paper presents a DT single-loop DSM audio ADC utilizing a single-ended ring-amplifier-based integrator to achieve 108.8dB DR with 203.5µW power consumption within a compact area of 0.0375mm2. The use of the PPD architecture with a merged adder contribute to this work's state-of-the-art power and area efficiency.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"65 1","pages":"412-414"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86849768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731736
Shoubhik Karmakar, M. Berkhout, K. Makinwa, Qinwen Fan
Piezoelectric speakers are gaining popularity on account of their improving form-factor and audio quality, making them a good fit for many audio applications such as in televisions, laptops, etc. Such speakers can be modelled as a large capacitive load, and so are typically driven by a Class-AB amplifier via a series resistor that ensures driver stability, and limits load current, but wastes power [1], [2]. In [3], the Class-AB amplifier is replaced by a more power-efficient Class-D amplifier (CDA) in series with an additional inductor. However, a series resistor is still required to damp the resulting LC resonant circuit, which could otherwise draw excessive currents when excited by large-signal distortion (e.g. clipping) harmonics around the LC resonance frequency. Alternatively, by using a feed-forward architecture based on LC filter diagnostics to limit overshoot currents, the series resistor can be replaced by a second inductor, at the expense of increased system complexity and cost [4].
{"title":"A -91 dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping","authors":"Shoubhik Karmakar, M. Berkhout, K. Makinwa, Qinwen Fan","doi":"10.1109/ISSCC42614.2022.9731736","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731736","url":null,"abstract":"Piezoelectric speakers are gaining popularity on account of their improving form-factor and audio quality, making them a good fit for many audio applications such as in televisions, laptops, etc. Such speakers can be modelled as a large capacitive load, and so are typically driven by a Class-AB amplifier via a series resistor that ensures driver stability, and limits load current, but wastes power [1], [2]. In [3], the Class-AB amplifier is replaced by a more power-efficient Class-D amplifier (CDA) in series with an additional inductor. However, a series resistor is still required to damp the resulting LC resonant circuit, which could otherwise draw excessive currents when excited by large-signal distortion (e.g. clipping) harmonics around the LC resonance frequency. Alternatively, by using a feed-forward architecture based on LC filter diagnostics to limit overshoot currents, the series resistor can be replaced by a second inductor, at the expense of increased system complexity and cost [4].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88355582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731561
Z. Gao, Jingchu He, M. Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, B. Eitel, Ken Yamamoto, R. Staszewski, M. Alavi, M. Babaie
In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although system-level techniques, e.g., background calibration [1], supply ripple reduction [2], and DTC code randomization [3], can partially alleviate these DTC issues, the overall system complexity worsens. The second method is to convert and cancel the predicted time offset in the voltage domain [4]. This arrangement is less sensitive to PVT variations. However, the accuracy of the time-to-voltage conversion relies on the strict trade-offs between the power consumption, noise, and linearity of a current source. In this work, we introduce a third solution based on a time-mode arithmetic unit (TAU), which outputs a weighted sum of time delays between the (falling) edges of FREF and CKV, as well as between two consecutive CKV edges. Compared with DTC-based solutions, it is less sensitive to PVT variations, as its output merely varies by the ratio of RC time constants, thus ensuring low fractional spurs with no extra system complexity. Compared to the voltage-domain solutions, the absence of a current source is beneficial for phase-noise optimization and migration to more advanced technology nodes. Moreover, TAU can implicitly provide a time-amplification (TA) gain, thus further suppressing the noise of subsequent blocks.
{"title":"A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs","authors":"Z. Gao, Jingchu He, M. Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, B. Eitel, Ken Yamamoto, R. Staszewski, M. Alavi, M. Babaie","doi":"10.1109/ISSCC42614.2022.9731561","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731561","url":null,"abstract":"In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although system-level techniques, e.g., background calibration [1], supply ripple reduction [2], and DTC code randomization [3], can partially alleviate these DTC issues, the overall system complexity worsens. The second method is to convert and cancel the predicted time offset in the voltage domain [4]. This arrangement is less sensitive to PVT variations. However, the accuracy of the time-to-voltage conversion relies on the strict trade-offs between the power consumption, noise, and linearity of a current source. In this work, we introduce a third solution based on a time-mode arithmetic unit (TAU), which outputs a weighted sum of time delays between the (falling) edges of FREF and CKV, as well as between two consecutive CKV edges. Compared with DTC-based solutions, it is less sensitive to PVT variations, as its output merely varies by the ratio of RC time constants, thus ensuring low fractional spurs with no extra system complexity. Compared to the voltage-domain solutions, the absence of a current source is beneficial for phase-noise optimization and migration to more advanced technology nodes. Moreover, TAU can implicitly provide a time-amplification (TA) gain, thus further suppressing the noise of subsequent blocks.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"29 1","pages":"380-382"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82677274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731799
{"title":"F4: Paving the Way to 200Gb/s Transceivers","authors":"","doi":"10.1109/isscc42614.2022.9731799","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731799","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"10 1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88192018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731607
Hirotaka Murakami, E. Bohannon, J. Childs, Grace Gui, E. Moule, Katsuhiko Hanzawa, Tomofumi Koda, Chiaki Takano, T. Shimizu, Yuki Takizawa, Adarsh Basavalingappa, R. Childs, Cody R. Cziesler, R. Jarnot, Kazumasa Nishimura, S. Rogerson, Y. Nitta
Today's mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a $2560(mathsf{H})times 1920(mathsf{V})$ pixel array that, at 1fps, consumes $790mumathsf{W}$ for full-color VGA and 120µW for motion-detection (MD) mode.
{"title":"A 4.9Mpixel Programmable-Resolution Multi-Purpose CMOS Image Sensor for Computer Vision","authors":"Hirotaka Murakami, E. Bohannon, J. Childs, Grace Gui, E. Moule, Katsuhiko Hanzawa, Tomofumi Koda, Chiaki Takano, T. Shimizu, Yuki Takizawa, Adarsh Basavalingappa, R. Childs, Cody R. Cziesler, R. Jarnot, Kazumasa Nishimura, S. Rogerson, Y. Nitta","doi":"10.1109/ISSCC42614.2022.9731607","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731607","url":null,"abstract":"Today's mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a $2560(mathsf{H})times 1920(mathsf{V})$ pixel array that, at 1fps, consumes $790mumathsf{W}$ for full-color VGA and 120µW for motion-detection (MD) mode.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"190 1","pages":"104-106"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79559563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731580
{"title":"SE5: Shifting Tides of Innovation – Where is Cutting-Edge Research Happening Today?","authors":"","doi":"10.1109/isscc42614.2022.9731580","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731580","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"60 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83652738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731611
Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, E. P. D. Silva, V. Sathe
SoCs in sensing and wearable applications are aggressively duty-cycled to minimize leakage energy losses. Such systems operate predominantly in Sleep mode, regularly marked by brief intervals of Active operation to perform sensing or communication actions. During Sleep, the considerable electrical energy stored in the domain-decoupling capacitor $(C_{0})$ leaks away, requiring the battery to deliver the energy $(E_{mathsf{wake}})$ needed to restore $C_{0}$ to $V_{mathsf{dd}}$ during the Wake phase ahead of Active mode operation (Fig. 13.7.1). Because of the relatively limited energy dissipation incurred during the brief Active duration, the overhead presented by $E_{mathsf{wake}}$ constitutes a significant fraction of total energy dissipation, which degrades battery life significantly.
{"title":"Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains","authors":"Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, E. P. D. Silva, V. Sathe","doi":"10.1109/ISSCC42614.2022.9731611","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731611","url":null,"abstract":"SoCs in sensing and wearable applications are aggressively duty-cycled to minimize leakage energy losses. Such systems operate predominantly in Sleep mode, regularly marked by brief intervals of Active operation to perform sensing or communication actions. During Sleep, the considerable electrical energy stored in the domain-decoupling capacitor $(C_{0})$ leaks away, requiring the battery to deliver the energy $(E_{mathsf{wake}})$ needed to restore $C_{0}$ to $V_{mathsf{dd}}$ during the Wake phase ahead of Active mode operation (Fig. 13.7.1). Because of the relatively limited energy dissipation incurred during the brief Active duration, the overhead presented by $E_{mathsf{wake}}$ constitutes a significant fraction of total energy dissipation, which degrades battery life significantly.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"8 1","pages":"222-224"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90918510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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