Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731752
Jiang Gong, B. Patra, Luc Enthoven, J. V. Staveren, F. Sebastiano, M. Babaie
LC VCOs with low phase noise (PN) and an octave frequency-tuning range (FTR) are required for multistandard communication devices, software-defined radios, and wireline data links. A viable popular approach is to exploit multicore mode-switching VCOs for two reasons: (1) their PN improves linearly by in-phase coupling of N identical VCOs; (2) the resonant-mode switching enhances the VCO FTR without degrading the tank quality factor (Q) as no RF current ideally flows through lossy mode-selection switches. However, it is still challenging for dual-mode VCOs to achieve a competitive FoM while covering an octave FTR at oscillation frequencies $(mathrm{F}_{text{OSC}})$ above 6GHz [1]. To enhance the number of oscillation modes to 3, [2] added a center-loop inductor $(mathrm{L}_{mathrm{C}})$ to a transformer, as shown in Fig. 9.2.1. However, a large FTR gap is measured, since the transformer windings should be strongly coupled to accommodate $mathrm{L}_{mathrm{C}}$, The authors of [3] and [4] realized a triple- and quad-mode operation, respectively, by coupling two individual transformer-based resonators (see Fig. 9.2.1). Apart from the large area penalty, the former needs an extra third winding $(mathrm{L}_{mathrm{T}})$ in each transformer that degrades the tank Q, while the latter used large, fixed coupling capacitors $(mathrm{C}_{mathrm{M}})$ that load the tank in two of the resonant modes, thus limiting the VCO FTR.
{"title":"A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB $mathbf{FoM}_{mathbf{A}}$ in 22nm FinFET","authors":"Jiang Gong, B. Patra, Luc Enthoven, J. V. Staveren, F. Sebastiano, M. Babaie","doi":"10.1109/ISSCC42614.2022.9731752","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731752","url":null,"abstract":"LC VCOs with low phase noise (PN) and an octave frequency-tuning range (FTR) are required for multistandard communication devices, software-defined radios, and wireline data links. A viable popular approach is to exploit multicore mode-switching VCOs for two reasons: (1) their PN improves linearly by in-phase coupling of N identical VCOs; (2) the resonant-mode switching enhances the VCO FTR without degrading the tank quality factor (Q) as no RF current ideally flows through lossy mode-selection switches. However, it is still challenging for dual-mode VCOs to achieve a competitive FoM while covering an octave FTR at oscillation frequencies $(mathrm{F}_{text{OSC}})$ above 6GHz [1]. To enhance the number of oscillation modes to 3, [2] added a center-loop inductor $(mathrm{L}_{mathrm{C}})$ to a transformer, as shown in Fig. 9.2.1. However, a large FTR gap is measured, since the transformer windings should be strongly coupled to accommodate $mathrm{L}_{mathrm{C}}$, The authors of [3] and [4] realized a triple- and quad-mode operation, respectively, by coupling two individual transformer-based resonators (see Fig. 9.2.1). Apart from the large area penalty, the former needs an extra third winding $(mathrm{L}_{mathrm{T}})$ in each transformer that degrades the tank Q, while the latter used large, fixed coupling capacitors $(mathrm{C}_{mathrm{M}})$ that load the tank in two of the resonant modes, thus limiting the VCO FTR.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91228414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731591
Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, S. Jia, Congcong Chen, Jiaqi Yu
The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1st-tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.
{"title":"A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS","authors":"Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, S. Jia, Congcong Chen, Jiaqi Yu","doi":"10.1109/ISSCC42614.2022.9731591","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731591","url":null,"abstract":"The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1st-tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"40 1","pages":"118-120"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73571719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731693
{"title":"F3: The Path to 6G: Architectures, Circuits, Technologies for Sub-THz Communications, Sensing and Imaging","authors":"","doi":"10.1109/isscc42614.2022.9731693","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731693","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"34 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73085080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731741
{"title":"ISSCC 2022 International Technical Program Committee","authors":"","doi":"10.1109/isscc42614.2022.9731741","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731741","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"24 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73441345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731578
Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang
With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers. As one of the widest-employed PLL structures, a charge-pump PLL (CPPLL) with a phase-frequency detector (PFD) is known for its excellent robust lock-acquisition performance due to the capability to detect phase and frequency error simultaneously. Recent research exhibited the great potential of the CPPLLs to achieve sub-100fsrms jitter [1]. However, a large current CP is adopted in [1] to minimize CP noise at the cost of high-power consumption. In this work, a 25.8GHz PLL with a time-amplifying phase-frequency detector (TAPFD) is implemented to suppress the CP noise by the high phase-error detection gain of the TAPFD and maintain the robust acquisition ability concurrently. The prototype is measured to achieve 60fsrms jitter and -252.8dB FoMJ.
{"title":"A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance","authors":"Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang","doi":"10.1109/ISSCC42614.2022.9731578","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731578","url":null,"abstract":"With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers. As one of the widest-employed PLL structures, a charge-pump PLL (CPPLL) with a phase-frequency detector (PFD) is known for its excellent robust lock-acquisition performance due to the capability to detect phase and frequency error simultaneously. Recent research exhibited the great potential of the CPPLLs to achieve sub-100fsrms jitter [1]. However, a large current CP is adopted in [1] to minimize CP noise at the cost of high-power consumption. In this work, a 25.8GHz PLL with a time-amplifying phase-frequency detector (TAPFD) is implemented to suppress the CP noise by the high phase-error detection gain of the TAPFD and maintain the robust acquisition ability concurrently. The prototype is measured to achieve 60fsrms jitter and -252.8dB FoMJ.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"79 1","pages":"388-390"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76644255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The era of AI computing brings significant challenges to traditional computer systems. As shown in Fig. 29.1.1, while the AI model computation requirement increases 750x every two years, we only observe a very slow-paced improvement of memory system capability in terms of both capacity and bandwidth. There are many memory-bound applications, such as natural language processing, recommendation systems, graph analytics, graph neural networks, as well as multi-task online inference, that become dominating AI applications in modern cloud datacenters. Current primary memory technologies that power AI systems and applications include on-chip memory (SRAM), 2.5D integrated memory (HBM [1]), and off-chip memory (DDR, LPDDR, or GDDR SDRAM). Although on-chip memory enjoys low energy access compared to off-chip memory, limited on-chip memory capacity prevents the efficient adoption of large AI models due to intensive and costly off-chip memory access. In addition, the energy consumption of data movement of off-chip memory solutions (HBM and DRAM) is several orders of magnitude larger than that of on-chip memory, bringing the well-known “memory wall [2]“problem to AI systems. Process-near-memory (PNM) and computing-in-memory (CIM) have become promising candidates to tackle the “memory wall” problem in recent years.
{"title":"184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System","authors":"Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, F. Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie","doi":"10.1109/ISSCC42614.2022.9731694","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731694","url":null,"abstract":"The era of AI computing brings significant challenges to traditional computer systems. As shown in Fig. 29.1.1, while the AI model computation requirement increases 750x every two years, we only observe a very slow-paced improvement of memory system capability in terms of both capacity and bandwidth. There are many memory-bound applications, such as natural language processing, recommendation systems, graph analytics, graph neural networks, as well as multi-task online inference, that become dominating AI applications in modern cloud datacenters. Current primary memory technologies that power AI systems and applications include on-chip memory (SRAM), 2.5D integrated memory (HBM [1]), and off-chip memory (DDR, LPDDR, or GDDR SDRAM). Although on-chip memory enjoys low energy access compared to off-chip memory, limited on-chip memory capacity prevents the efficient adoption of large AI models due to intensive and costly off-chip memory access. In addition, the energy consumption of data movement of off-chip memory solutions (HBM and DRAM) is several orders of magnitude larger than that of on-chip memory, bringing the well-known “memory wall [2]“problem to AI systems. Process-near-memory (PNM) and computing-in-memory (CIM) have become promising candidates to tackle the “memory wall” problem in recent years.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"117 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89410129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731567
T. Jung, M. Fujita, Jeong Cho, Kyung-Hoon Lee, D. Seol, Sung-Jin An, Chanhee Lee, Youjin Jeong, Minji Jung, Sachoun Park, Seungki Baek, Seungki Jung, Seunghwan Lee, Jungbin Yun, E. Shim, Heetak Han, Eunkyung Park, Haesick Sul, Se-Won Kang, Kyungho Lee, JungChak Ahn, Duckhyun Chang
As the strong demand for higher resolution and new functionality is rapidly increasing in the mobile CMOS Image Sensor (CIS) market, we have seen the emergence of: submicron pixels, >200M pixels, fast readout, global shutter, high dynamic range, and phase-detection autofocus (PDAF) [1 – 3]. Among these, PDAF is an essential feature of cutting-edge CIS for accurate autofocus at extremely low-light situations, and dual-pixel technology has been widely used for AF of the entire image area [4]. To implement high pixel resolution in a limited optical size, the pixel size has continued to shrink, and the pixel structure has evolved to maintain high image quality. However, for a dual pixel, integrating two photodiodes (PDs) in one pixel by backside deep trench isolation (BDTI) has technical limitations and causes degradation of image AF performance as well as image quality.
{"title":"A 1/1.57-inch 50Mpixel CMOS Image Sensor With 1.0μm All-Directional Dual Pixel by 0.5μm-Pitch Full-Depth Deep-Trench Isolation Technology","authors":"T. Jung, M. Fujita, Jeong Cho, Kyung-Hoon Lee, D. Seol, Sung-Jin An, Chanhee Lee, Youjin Jeong, Minji Jung, Sachoun Park, Seungki Baek, Seungki Jung, Seunghwan Lee, Jungbin Yun, E. Shim, Heetak Han, Eunkyung Park, Haesick Sul, Se-Won Kang, Kyungho Lee, JungChak Ahn, Duckhyun Chang","doi":"10.1109/ISSCC42614.2022.9731567","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731567","url":null,"abstract":"As the strong demand for higher resolution and new functionality is rapidly increasing in the mobile CMOS Image Sensor (CIS) market, we have seen the emergence of: submicron pixels, >200M pixels, fast readout, global shutter, high dynamic range, and phase-detection autofocus (PDAF) [1 – 3]. Among these, PDAF is an essential feature of cutting-edge CIS for accurate autofocus at extremely low-light situations, and dual-pixel technology has been widely used for AF of the entire image area [4]. To implement high pixel resolution in a limited optical size, the pixel size has continued to shrink, and the pixel structure has evolved to maintain high image quality. However, for a dual pixel, integrating two photodiodes (PDs) in one pixel by backside deep trench isolation (BDTI) has technical limitations and causes degradation of image AF performance as well as image quality.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"102-104"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90062057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731760
Luya Zhang, A. Niknejad
Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today's ever-growing wireless and wireline communication systems. To meet the stringent requirements on data-rate and modulation schemes, the phase noise of the frequency synthesizers must be minimized. On the other hand, since low-noise and low-cost crystal oscillators operate in the MHz range, a > 10GHz frequency synthesizer demands a very large multiplication factor M (typically 400–1000), which poses new challenges. Although cascading PLLs helps reduce M per stage, it causes a significant power overhead and unwanted coupling between the two VCOs. Therefore, direct high M-factor frequency synthesis with low phase noise and low power consumption becomes a compelling approach.
{"title":"A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump","authors":"Luya Zhang, A. Niknejad","doi":"10.1109/ISSCC42614.2022.9731760","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731760","url":null,"abstract":"Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today's ever-growing wireless and wireline communication systems. To meet the stringent requirements on data-rate and modulation schemes, the phase noise of the frequency synthesizers must be minimized. On the other hand, since low-noise and low-cost crystal oscillators operate in the MHz range, a > 10GHz frequency synthesizer demands a very large multiplication factor M (typically 400–1000), which poses new challenges. Although cascading PLLs helps reduce M per stage, it causes a significant power overhead and unwanted coupling between the two VCOs. Therefore, direct high M-factor frequency synthesis with low phase noise and low power consumption becomes a compelling approach.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"92 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83795268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：