Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731671
N. Monroe, Georgios C. Doqiamis, R.A. Stingel, Preston Myers, Xibi Chen, R. Han
Ultra-sharp beam forming and high-angular-resolution steering in both azimuth and elevation directions are required in high-performance imaging sensors, spatial-multiplexed wireless links and other applications. This poses great challenges due to the fundamental relationship between the beamwidth and the dimension of the antenna aperture. As shown in Fig. 4.5.1, the aperture size required to achieve 1 ° of 3dB beamwidth is $0.6times 0.6mathrm{m}^{2}$ and $0.2times 0.2mathrm{m}^{2}$ at 24GHz and 77GHz, respectively. In current radars, sparse MIMO antenna schemes are adopted to synthesize virtual arrays with the above size in one dimension. However, they require intensive signal processing of many channels. The complex signal routing and placement of active electronics also leads to challenges in the 2D scaling required for pencil beam forming. By increasing the wave frequency to 265GHz, the work in this paper significantly reduces the aperture area, allowing it to be fully realized by digitally controlled, reflective antennas in CMOS microelectronic chips (Fig. 4.5.1). Similar to a concave mirror, a reflectarray, when illuminated by a single radar source, applies incident-angle-dependent phase shifts (e.g. $varphi_{1}$ and $varphi_{2}$ in Fig. 4.5.1) to the wave and re-focuses it towards a desired direction. This quasi-optical spatial feed eliminates the high-frequency signal routing and complex processing inherent to MIMO arrays. Employing $98times 98$ antenna elements, we experimentally demonstrate the forming and electronic steering of a THz pencil beam with- 1 ° beamwidth in two dimensions. With under-antenna integration of dense memory cells, sidelobe reduction and squint correction are also achieved.
{"title":"Electronic THz Pencil Beam Forming and 2D Steering for High Angular-Resolution Operation: A 98 $times$ 98-Unit 265GHz CMOS Reflectarray with In-Unit Digital Beam Shaping and Squint Correction","authors":"N. Monroe, Georgios C. Doqiamis, R.A. Stingel, Preston Myers, Xibi Chen, R. Han","doi":"10.1109/ISSCC42614.2022.9731671","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731671","url":null,"abstract":"Ultra-sharp beam forming and high-angular-resolution steering in both azimuth and elevation directions are required in high-performance imaging sensors, spatial-multiplexed wireless links and other applications. This poses great challenges due to the fundamental relationship between the beamwidth and the dimension of the antenna aperture. As shown in Fig. 4.5.1, the aperture size required to achieve 1 ° of 3dB beamwidth is $0.6times 0.6mathrm{m}^{2}$ and $0.2times 0.2mathrm{m}^{2}$ at 24GHz and 77GHz, respectively. In current radars, sparse MIMO antenna schemes are adopted to synthesize virtual arrays with the above size in one dimension. However, they require intensive signal processing of many channels. The complex signal routing and placement of active electronics also leads to challenges in the 2D scaling required for pencil beam forming. By increasing the wave frequency to 265GHz, the work in this paper significantly reduces the aperture area, allowing it to be fully realized by digitally controlled, reflective antennas in CMOS microelectronic chips (Fig. 4.5.1). Similar to a concave mirror, a reflectarray, when illuminated by a single radar source, applies incident-angle-dependent phase shifts (e.g. $varphi_{1}$ and $varphi_{2}$ in Fig. 4.5.1) to the wave and re-focuses it towards a desired direction. This quasi-optical spatial feed eliminates the high-frequency signal routing and complex processing inherent to MIMO arrays. Employing $98times 98$ antenna elements, we experimentally demonstrate the forming and electronic steering of a THz pencil beam with- 1 ° beamwidth in two dimensions. With under-antenna integration of dense memory cells, sidelobe reduction and squint correction are also achieved.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84951892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731662
C. Hill, J. Buckwalter
Massive MIMO or digital-beamforming transceiver systems, shown in Fig. 19.7.1, offer flexibility for multiband, multi-user, and joint communication-and-sensing platforms. However, wideband MIMO applications increase the number of desired or interfering signals that impinge on each channel, creating higher input-power-compression $(mathrm{P}_{1text{dB}})$ or 3rd-order input-intercept-point (IIP3) linearity requirements in both the transmitting and receiving RF paths. In high-performance commercial and defense radios, CMOS mixers place critical limitations on receiver linearity as the LNA output typically compresses the mixer, leading to recent work on mixer-first approaches in CMOS to improve receiver linearity [1]. When highly linear microwave mixers are demanded, IIIV processes, such as GaAs, are favored for Schottky diodes, which offer lower $mathrm{R}_{text{on}}mathrm{C}_{text{off}}$ and high barrier voltages. Commercially available GaAs mixers offer IIP3s exceeding 30dBm. However, III-V mixers typically use a separate process for the driver amplifier, resulting in multiple chips with high driver power consumption (typically exceeding 1W) to deliver the required 15-to-30dBm LO power across a broad LO frequency range [2].
{"title":"A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI","authors":"C. Hill, J. Buckwalter","doi":"10.1109/ISSCC42614.2022.9731662","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731662","url":null,"abstract":"Massive MIMO or digital-beamforming transceiver systems, shown in Fig. 19.7.1, offer flexibility for multiband, multi-user, and joint communication-and-sensing platforms. However, wideband MIMO applications increase the number of desired or interfering signals that impinge on each channel, creating higher input-power-compression $(mathrm{P}_{1text{dB}})$ or 3rd-order input-intercept-point (IIP3) linearity requirements in both the transmitting and receiving RF paths. In high-performance commercial and defense radios, CMOS mixers place critical limitations on receiver linearity as the LNA output typically compresses the mixer, leading to recent work on mixer-first approaches in CMOS to improve receiver linearity [1]. When highly linear microwave mixers are demanded, IIIV processes, such as GaAs, are favored for Schottky diodes, which offer lower $mathrm{R}_{text{on}}mathrm{C}_{text{off}}$ and high barrier voltages. Commercially available GaAs mixers offer IIP3s exceeding 30dBm. However, III-V mixers typically use a separate process for the driver amplifier, resulting in multiple chips with high driver power consumption (typically exceeding 1W) to deliver the required 15-to-30dBm LO power across a broad LO frequency range [2].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87928547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731550
Xu Yang, Linhu Zhao, Menglian Zhao, Z. Tan, Lenian He, Yong Ding, Wuhua Li, W. Qu
For the battery- or USB-powered portable smart devices, which supply their computing cores with a wide-range sub-volt rail, the energy-efficient high and wide voltage-conversion-ratio (VCR) converters are crucially important. In addition, low form factor and decent transient responses are also favorable for such applications. Prior state-of-the-art designs either use single-stage hybrid designs using multi-level or Dickson converters [1 – 3], or adopt two-stage cascaded architectures with a highly efficient unregulated front (or rear) stage [4], as shown in Fig. 18.6.1 (left). The multi-level designs, which conduct the full inductor current through all the on-state switches, are suited to low-to-medium power levels with limited current density. The Dickson converters take advantage of a high conversion ratio, however, at the cost of reduced output voltage range. The two-stage designs which show decent output range and efficiency, however, can suffer from heavy load efficiency degradation considering that the efficiency of both stages degrade with increasing load and the overall efficiency which is the product of the efficiencies of the two stages is severely degraded. Inspired by the inductive-sigma converter [5] which shunts a highly efficient unregulated LLC with a regulated Buck, this work proposes a reconfigurable capacitive-sigma converter. By input-series and output-shunting a highly efficient unregulated switched-capacitor (SC) converter with a reconfigurable Dickson hybrid Buck stage, the power stage input current is reused and output currents are combined. Therefore, the overall efficiency is greatly improved in a wide continuous VCR range and with an enhanced loading capacity. Besides, as will be demonstrated, the proposed design shows inherently decent load transient and regulation performances.
{"title":"A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-Sigma Converter With Greater than 90% Peak Efficiency for the Entire 0.4~1.2V Output Range","authors":"Xu Yang, Linhu Zhao, Menglian Zhao, Z. Tan, Lenian He, Yong Ding, Wuhua Li, W. Qu","doi":"10.1109/ISSCC42614.2022.9731550","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731550","url":null,"abstract":"For the battery- or USB-powered portable smart devices, which supply their computing cores with a wide-range sub-volt rail, the energy-efficient high and wide voltage-conversion-ratio (VCR) converters are crucially important. In addition, low form factor and decent transient responses are also favorable for such applications. Prior state-of-the-art designs either use single-stage hybrid designs using multi-level or Dickson converters [1 – 3], or adopt two-stage cascaded architectures with a highly efficient unregulated front (or rear) stage [4], as shown in Fig. 18.6.1 (left). The multi-level designs, which conduct the full inductor current through all the on-state switches, are suited to low-to-medium power levels with limited current density. The Dickson converters take advantage of a high conversion ratio, however, at the cost of reduced output voltage range. The two-stage designs which show decent output range and efficiency, however, can suffer from heavy load efficiency degradation considering that the efficiency of both stages degrade with increasing load and the overall efficiency which is the product of the efficiencies of the two stages is severely degraded. Inspired by the inductive-sigma converter [5] which shunts a highly efficient unregulated LLC with a regulated Buck, this work proposes a reconfigurable capacitive-sigma converter. By input-series and output-shunting a highly efficient unregulated switched-capacitor (SC) converter with a reconfigurable Dickson hybrid Buck stage, the power stage input current is reused and output currents are combined. Therefore, the overall efficiency is greatly improved in a wide continuous VCR range and with an enhanced loading capacity. Besides, as will be demonstrated, the proposed design shows inherently decent load transient and regulation performances.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"41 1","pages":"108-110"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88466802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bioimpedance (BioZ) analysis has been recognized as a new paradigm to derive a number of body composition and hemodynamic measures in a non-invasive manner. Measuring the changes in electrical resistance of the thorax during a cardiac cycle, known as impedance cardiography (ICG), is beneficial in detecting early signs of heart failure deterioration [1]. This raises the need for power-efficient wearable BioZ sensors to enable long-term and user-friendly health monitoring, while state-of-the-art designs still suffer from a few drawbacks. First, conventional BioZ interfaces typically rely on gel electrodes (> 10cm2) for low-impedance contact between skin and electrodes [1]–[2]. This not only hampers the long-term recording but also causes user discomfort. However, it is very challenging to perform small-size dry-electrode BioZ sensing at the frequency range of 1kHz to 1MHz, where both the increased electrode-tissue impedance (ETI) (-10MΩII0.5nF) and input parasitic capacitance $mathrm{C}_{mathrm{p}}(> 10text{pF})$ play a dominating role in attenuating the input signal (Fig. 20.1.1), resulting in gain inaccuracy and a long settling time [3]. To solve this issue, a BioZ amplifier with calibrated positive feedback [3] was proposed for input impedance boosting, which enables 1cm2 dry-electrode BioZ sensing. Second, to identify small BioZ variation (0.01 to $1Omega$) over higher baseline impedance, i.e., ETI plus the static BioZ component, both the excitation current generator (CG) and the BioZ amplifier must feature low noise. Although dynamic element matching (DEM) is effective in alleviating the 1/f current noise of the CG [2], the input-signal-dependent noise of the amplifier remains a notable problem that severely reduces the measurement accuracy when the BioZ signal is large [4]. Furthermore, previous CGs employing complementary current sources suffer from current mismatch, resulting in low output impedance and limited voltage headroom [1]–[2]. A unipolar CG solves this problem, but both the sinusoidal CG and current sink amplifier are power-hungry [3]. Finally, state-of-the-art BioZ readouts [1]–[3] still require an extra electrode to bias the body and provide the input common-mode (CM) voltage, which further increases the system complexity.
{"title":"A 0.5mΩ/√Hz 106dB SNR 0.45cm2 Dry-Electrode Bioimpedance Interface with Current Mismatch Cancellation and Boosted Input Impedance of 100MΩ at 50kHz","authors":"Qinjing Pan, Tianxiang Qu, Biao Tang, Fei Shan, Zhiliang Hong, Jiawei Xu","doi":"10.1109/ISSCC42614.2022.9731787","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731787","url":null,"abstract":"Bioimpedance (BioZ) analysis has been recognized as a new paradigm to derive a number of body composition and hemodynamic measures in a non-invasive manner. Measuring the changes in electrical resistance of the thorax during a cardiac cycle, known as impedance cardiography (ICG), is beneficial in detecting early signs of heart failure deterioration [1]. This raises the need for power-efficient wearable BioZ sensors to enable long-term and user-friendly health monitoring, while state-of-the-art designs still suffer from a few drawbacks. First, conventional BioZ interfaces typically rely on gel electrodes (> 10cm2) for low-impedance contact between skin and electrodes [1]–[2]. This not only hampers the long-term recording but also causes user discomfort. However, it is very challenging to perform small-size dry-electrode BioZ sensing at the frequency range of 1kHz to 1MHz, where both the increased electrode-tissue impedance (ETI) (-10MΩII0.5nF) and input parasitic capacitance $mathrm{C}_{mathrm{p}}(> 10text{pF})$ play a dominating role in attenuating the input signal (Fig. 20.1.1), resulting in gain inaccuracy and a long settling time [3]. To solve this issue, a BioZ amplifier with calibrated positive feedback [3] was proposed for input impedance boosting, which enables 1cm2 dry-electrode BioZ sensing. Second, to identify small BioZ variation (0.01 to $1Omega$) over higher baseline impedance, i.e., ETI plus the static BioZ component, both the excitation current generator (CG) and the BioZ amplifier must feature low noise. Although dynamic element matching (DEM) is effective in alleviating the 1/f current noise of the CG [2], the input-signal-dependent noise of the amplifier remains a notable problem that severely reduces the measurement accuracy when the BioZ signal is large [4]. Furthermore, previous CGs employing complementary current sources suffer from current mismatch, resulting in low output impedance and limited voltage headroom [1]–[2]. A unipolar CG solves this problem, but both the sinusoidal CG and current sink amplifier are power-hungry [3]. Finally, state-of-the-art BioZ readouts [1]–[3] still require an extra electrode to bias the body and provide the input common-mode (CM) voltage, which further increases the system complexity.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"36 1","pages":"332-334"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87199133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731110
Jonghak Yuh, Jason Li, Heguang Li, Y. Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, S. Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex S. Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, J. Sohn, H. Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, I. V., C. G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, F. Moogat, In-Soo Yoon, K. Kanda, Takahiro Shimizu, N. Shibata, Takashi Shigeoka, K. Yanagidaira, T. Kodama, R. Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe
The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm2 which is 8.7% higher than prior work [1]. High-performance is the key enabler for 4b/cell NAND Flash to enter mainstream systems. This work delivers a 60MB/s programming throughput and a 65μs tR with an 8kB central WL stair architecture and contact-through-WL (CTW) region. 2.4Gb/s I/O speed is achieved with LTT and CTT combo drivers. A 45% reduction in the read and write data transfer energy is achieved by employing VCCQ domain design. A time-division peak-power-management (TD-PPM) feature effectively reduces system peak power while maximizing system performance. Cache DFT and I/O DFT functions enable a high-speed testing methodology at wafer level. These features are summarized and compared to previously reported 4b/cell Flash memories in Fig. 7.1.1.
{"title":"A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface","authors":"Jonghak Yuh, Jason Li, Heguang Li, Y. Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, S. Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex S. Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, J. Sohn, H. Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, I. V., C. G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, F. Moogat, In-Soo Yoon, K. Kanda, Takahiro Shimizu, N. Shibata, Takashi Shigeoka, K. Yanagidaira, T. Kodama, R. Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe","doi":"10.1109/ISSCC42614.2022.9731110","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731110","url":null,"abstract":"The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm2 which is 8.7% higher than prior work [1]. High-performance is the key enabler for 4b/cell NAND Flash to enter mainstream systems. This work delivers a 60MB/s programming throughput and a 65μs tR with an 8kB central WL stair architecture and contact-through-WL (CTW) region. 2.4Gb/s I/O speed is achieved with LTT and CTT combo drivers. A 45% reduction in the read and write data transfer energy is achieved by employing VCCQ domain design. A time-division peak-power-management (TD-PPM) feature effectively reduces system peak power while maximizing system performance. Cache DFT and I/O DFT functions enable a high-speed testing methodology at wafer level. These features are summarized and compared to previously reported 4b/cell Flash memories in Fig. 7.1.1.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"119 1","pages":"130-132"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88982474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731714
Hyojun Kim, H. Oh, W. Jung, Yoonho Song, Jonghyun Oh, D. Jeong
A ring oscillator (RO) generates a multi-phase clock with a large tuning range in a small area, enabling a per-lane implementation in multilane communication applications. However, a high-frequency RO suffers from inferior phase noise, which is exacerbated by its high flicker-noise corner [1], being unsuitable to be a precision-timing clock source for a high-throughput interface. While injection locking widens the noise-suppression bandwidth of an RO-based phase-locked loop (PLL) [2], its effectiveness to overall jitter is limited only to those with low multiplication factors. By exploiting the accumulation-free nature of jitter in delay-locked loops [3], the reference multiplier in [4] generates a clean mid-frequency clock and then is cascaded to a high-frequency PLL, achieving a low output jitter despite a high multiplication factor. However, the background calibration for the large delay errors in the reference multiplier due to process, supply voltage, and temperature (PVT) variations necessitates an excessive settling time, which is in the order of a few milliseconds at worst. While the reference multiplier in [5] achieves very low noise, its calibration, which also requires a long settling time, should be preceded by a post-fabrication trimming. In [6], another viable method for reference multiplication is presented. However, the long calibration time remains unsolved due to the required low noise contribution of its calibration PLL. In this paper, we present a 100MHz-reference, 8GHz/16GHz RO-based injection-locked all-digital PLL (IL-ADPLL) that incorporates a reference octupler (8xREF) with a probability-based adaptive calibration algorithm. The presented algorithm enables a fast, accurate phase-error calibration both under startup and after sudden environmental disturbance, e.g., a supply hop.
{"title":"A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration","authors":"Hyojun Kim, H. Oh, W. Jung, Yoonho Song, Jonghyun Oh, D. Jeong","doi":"10.1109/ISSCC42614.2022.9731714","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731714","url":null,"abstract":"A ring oscillator (RO) generates a multi-phase clock with a large tuning range in a small area, enabling a per-lane implementation in multilane communication applications. However, a high-frequency RO suffers from inferior phase noise, which is exacerbated by its high flicker-noise corner [1], being unsuitable to be a precision-timing clock source for a high-throughput interface. While injection locking widens the noise-suppression bandwidth of an RO-based phase-locked loop (PLL) [2], its effectiveness to overall jitter is limited only to those with low multiplication factors. By exploiting the accumulation-free nature of jitter in delay-locked loops [3], the reference multiplier in [4] generates a clean mid-frequency clock and then is cascaded to a high-frequency PLL, achieving a low output jitter despite a high multiplication factor. However, the background calibration for the large delay errors in the reference multiplier due to process, supply voltage, and temperature (PVT) variations necessitates an excessive settling time, which is in the order of a few milliseconds at worst. While the reference multiplier in [5] achieves very low noise, its calibration, which also requires a long settling time, should be preceded by a post-fabrication trimming. In [6], another viable method for reference multiplication is presented. However, the long calibration time remains unsolved due to the required low noise contribution of its calibration PLL. In this paper, we present a 100MHz-reference, 8GHz/16GHz RO-based injection-locked all-digital PLL (IL-ADPLL) that incorporates a reference octupler (8xREF) with a probability-based adaptive calibration algorithm. The presented algorithm enables a fast, accurate phase-error calibration both under startup and after sudden environmental disturbance, e.g., a supply hop.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88702841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731748
Junyao Tang, Lei Zhao, Cheng Huang
Galvanically isolated voltage regulators (GIVRs) are widely used in industrial automation, electric vehicles, and medical devices to deliver power to low-voltage circuits across isolated domains and ensure human safety and device reliability in hazardous environments. Traditional bulky transformer-based GIVRs can deliver 2W output power with 80% peak efficiency [1]. However, transformers are relatively expensive, and their size limits the overall physical size of the system from being further minimized. Inductive GIVRs using micro transformers have been introduced in [2]–[9] with a significantly reduced form factor; however, their efficiency is also significantly compromised to around 50% [2]–[4], or even lower in the 7-to-40% range [5]–[9]. This is mainly due to the much lower quality of the micro transformers compared to traditional ones, as well as the associated much higher switching frequency. In addition, the manufacturing/packaging may introduce extra cost due to the need for special processes [2], [3], [5], [6]. A capacitive GIVR has been introduced in [10]; however, the efficiency is also limited to 50.7%, with a maximum power capacity of only 62mW. Besides, common-mode transient (CMT) immunity (CMTI), which ensures the robustness of operation when fast and strong voltage transients happen between the isolated domains due to current/voltage spikes in motor drivers or other fast switching applications, is an important specification for galvanically isolated devices [2], [4], [8]. This is especially important for capacitive designs due to the direct capacitive links between the two domains. However, no discussions, mitigations, or measurements were provided in [10]. In addition, most state-of-the-art designs require an extra transformer [2], [3], [6] or a pair of capacitors [4], [10] to establish feedback links for voltage regulation, which also increase the cost and form factor, or they only work in open loop [5], [7], [9].
{"title":"A 68.3% Efficiency Reconfigurable 400-/800-mW Capacitive Isolated DC-DC Converter with Common-Mode Transient Immunity and Fast Dynamic Response by Through-Power-Link Hysteretic Control","authors":"Junyao Tang, Lei Zhao, Cheng Huang","doi":"10.1109/ISSCC42614.2022.9731748","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731748","url":null,"abstract":"Galvanically isolated voltage regulators (GIVRs) are widely used in industrial automation, electric vehicles, and medical devices to deliver power to low-voltage circuits across isolated domains and ensure human safety and device reliability in hazardous environments. Traditional bulky transformer-based GIVRs can deliver 2W output power with 80% peak efficiency [1]. However, transformers are relatively expensive, and their size limits the overall physical size of the system from being further minimized. Inductive GIVRs using micro transformers have been introduced in [2]–[9] with a significantly reduced form factor; however, their efficiency is also significantly compromised to around 50% [2]–[4], or even lower in the 7-to-40% range [5]–[9]. This is mainly due to the much lower quality of the micro transformers compared to traditional ones, as well as the associated much higher switching frequency. In addition, the manufacturing/packaging may introduce extra cost due to the need for special processes [2], [3], [5], [6]. A capacitive GIVR has been introduced in [10]; however, the efficiency is also limited to 50.7%, with a maximum power capacity of only 62mW. Besides, common-mode transient (CMT) immunity (CMTI), which ensures the robustness of operation when fast and strong voltage transients happen between the isolated domains due to current/voltage spikes in motor drivers or other fast switching applications, is an important specification for galvanically isolated devices [2], [4], [8]. This is especially important for capacitive designs due to the direct capacitive links between the two domains. However, no discussions, mitigations, or measurements were provided in [10]. In addition, most state-of-the-art designs require an extra transformer [2], [3], [6] or a pair of capacitors [4], [10] to establish feedback links for voltage regulation, which also increase the cost and form factor, or they only work in open loop [5], [7], [9].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"3 15","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91506360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731570
{"title":"SE4: The Bright and Dark Side of Artificial Intelligence (AI)","authors":"","doi":"10.1109/isscc42614.2022.9731570","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731570","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"245 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72943609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731562
Myeong-Jae Park, H. Cho, T. Yun, S. Byeon, Young Jun Koo, Sang-Sic Yoon, Dong-Uk Lee, Seokwoo Choi, Ji Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, B. Yoon, Y. Park, Sangmuk Oh, C. Lee, Tae-Kyun Kim, S. Lee, Hyunwoo Kim, Yucheon Ju, SeungGyeon Lim, S. Baek, Kyo Yun Lee, Sang Hun Lee, Woodward We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seungtaek Yang, Gunho Lee, In-Keun Kim, Y. Jeon, Jaewon Park, J. Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, T. Hwang, Junghyun Shin, Yu-Ri Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, J. Chun, Joohwan Cho
Ever since the introduction of high bandwidth memory (HBM DRAM) and its succeeding line-ups, HBM DRAM has been heralded as a prominent solution to tackle the memory wall problem. However, despite continual memory advancements the advent of high-end systems, including supercomputers, hyper-scale data centers and machine learning accelerators, are expediting requirements for higher-performance memory solutions. To accommodate the increasing system-level demands, we introduce HBM3 DRAM, which employs multiple new features and design schemes. Techniques such as an on-die ECC engine, internal NN-DFE I/O signaling, TSV auto-calibration, and layout optimization based on machine-learning algorithms are implemented to efficiently control timing skew margins and SI degradation trade-offs. Furthermore, reduced voltage swings allow for improved memory bandwidth, density, power efficiency and reliability.
{"title":"A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization","authors":"Myeong-Jae Park, H. Cho, T. Yun, S. Byeon, Young Jun Koo, Sang-Sic Yoon, Dong-Uk Lee, Seokwoo Choi, Ji Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, B. Yoon, Y. Park, Sangmuk Oh, C. Lee, Tae-Kyun Kim, S. Lee, Hyunwoo Kim, Yucheon Ju, SeungGyeon Lim, S. Baek, Kyo Yun Lee, Sang Hun Lee, Woodward We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seungtaek Yang, Gunho Lee, In-Keun Kim, Y. Jeon, Jaewon Park, J. Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, T. Hwang, Junghyun Shin, Yu-Ri Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, J. Chun, Joohwan Cho","doi":"10.1109/ISSCC42614.2022.9731562","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731562","url":null,"abstract":"Ever since the introduction of high bandwidth memory (HBM DRAM) and its succeeding line-ups, HBM DRAM has been heralded as a prominent solution to tackle the memory wall problem. However, despite continual memory advancements the advent of high-end systems, including supercomputers, hyper-scale data centers and machine learning accelerators, are expediting requirements for higher-performance memory solutions. To accommodate the increasing system-level demands, we introduce HBM3 DRAM, which employs multiple new features and design schemes. Techniques such as an on-die ECC engine, internal NN-DFE I/O signaling, TSV auto-calibration, and layout optimization based on machine-learning algorithms are implemented to efficiently control timing skew margins and SI degradation trade-offs. Furthermore, reduced voltage swings allow for improved memory bandwidth, density, power efficiency and reliability.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"15 1","pages":"444-446"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86049175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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