Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731718
I. Akita, Takeshi Kawano, H. Aoyama, S. Tatematsu, M. Hioki
Low-noise, $< 100text{pT}/sqrt{}text{Hz}$, and low-power magnetometers are indispensable in compact magnetomyography (MMG) measurement and can be utilized in devices involving human-computer interaction and prosthetic implants [1]. In addition, such applications require a high bandwidth of> 10kHz as fast neuronal magnetic activity should be acquired close to the skeletal muscle directly. This paper presents a 2.6mW magnetometer with $10text{pT}/sqrt{}text{Hz}$ input-referred noise and 33kHz signal bandwidth. The proposed magnetometer adopts a digital calibration scheme that automatically maximizes the loop gain and loop bandwidth with low power consumption for low-noise and high-bandwidth realization. The normalized energy of the proposed magnetometer reaches 1.6pJ, improving power efficiency compared with state-of-the-art designs [2]–[5], while maintaining a low noise characteristic.
{"title":"A 2.6mW 10pTI $sqrt{}$ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement","authors":"I. Akita, Takeshi Kawano, H. Aoyama, S. Tatematsu, M. Hioki","doi":"10.1109/ISSCC42614.2022.9731718","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731718","url":null,"abstract":"Low-noise, $< 100text{pT}/sqrt{}text{Hz}$, and low-power magnetometers are indispensable in compact magnetomyography (MMG) measurement and can be utilized in devices involving human-computer interaction and prosthetic implants [1]. In addition, such applications require a high bandwidth of> 10kHz as fast neuronal magnetic activity should be acquired close to the skeletal muscle directly. This paper presents a 2.6mW magnetometer with $10text{pT}/sqrt{}text{Hz}$ input-referred noise and 33kHz signal bandwidth. The proposed magnetometer adopts a digital calibration scheme that automatically maximizes the loop gain and loop bandwidth with low power consumption for low-noise and high-bandwidth realization. The normalized energy of the proposed magnetometer reaches 1.6pJ, improving power efficiency compared with state-of-the-art designs [2]–[5], while maintaining a low noise characteristic.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88748786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/isscc42614.2022.9731765
{"title":"Session 5 Overview: Imagers, Range Sensors and Displays","authors":"","doi":"10.1109/isscc42614.2022.9731765","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731765","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"26 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91011067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731648
Ajay Singhvi, Aidan Fitzpatrick, A. Arbabian
Oceans play a critical role in our ecosystem - they regulate weather and global temperature, serve as the largest carbon sink and the greatest source of oxygen. Maintaining ocean health is of paramount importance and has led to the emergence of the “Internet of Underwater Things (loUT)” with intelligent sensors being deployed for aquaculture, environmental monitoring, surveillance, and exploration. Given that RF and optical signals are heavily attenuated in water, and ultrasound (US) - which has favorable propagation underwater - faces a large water-air interface loss (~ 65dB), deep underwater sensing nodes most often communicate data via ultrasonic links to surface buoys, which then use RF to relay data to a remote station. However, such relay-based water-to-air networking solutions are cost and infrastructure intensive, with the inflexibility of anchored buoys prohibiting operation at scale. Wireless, cross-medium communication approaches that do not require intermediary relays would enable large-scale deployment of next-generation loUT sensors. Previously, laser Doppler vibrometers (LDV) [1] and mm-wave radars [2] have been used to remotely detect displacements on the water surface caused by impinging US waves but suffer from poor sensitivity and low data rates.
{"title":"An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air Interface","authors":"Ajay Singhvi, Aidan Fitzpatrick, A. Arbabian","doi":"10.1109/ISSCC42614.2022.9731648","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731648","url":null,"abstract":"Oceans play a critical role in our ecosystem - they regulate weather and global temperature, serve as the largest carbon sink and the greatest source of oxygen. Maintaining ocean health is of paramount importance and has led to the emergence of the “Internet of Underwater Things (loUT)” with intelligent sensors being deployed for aquaculture, environmental monitoring, surveillance, and exploration. Given that RF and optical signals are heavily attenuated in water, and ultrasound (US) - which has favorable propagation underwater - faces a large water-air interface loss (~ 65dB), deep underwater sensing nodes most often communicate data via ultrasonic links to surface buoys, which then use RF to relay data to a remote station. However, such relay-based water-to-air networking solutions are cost and infrastructure intensive, with the inflexibility of anchored buoys prohibiting operation at scale. Wireless, cross-medium communication approaches that do not require intermediary relays would enable large-scale deployment of next-generation loUT sensors. Previously, laser Doppler vibrometers (LDV) [1] and mm-wave radars [2] have been used to remotely detect displacements on the water surface caused by impinging US waves but suffer from poor sensitivity and low data rates.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"21 1","pages":"498-500"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84682820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, computing-in-memory (CIM) macros, originally designed to reduce the intensive memory accesses of Al tasks, have been employed in low-power machine learning SoCs due to their ultra-high computing efficiency [1]–[3]. These CIM macros still access weight data through on/off-chip memories, similar to processing elements in near-memory-computing architectures. The implementation poses challenges when counting the overall SoC energy efficiency (Fig. 15.3.1). First, the memory wall issue is unsolved. The weight updates affect overall system performance when large networks are deployed and massive off-chip weight data transfer occurs. Even for tiny machine learning tasks, power consumption and latency of constant weight updates cannot be neglected, because MAC computing efficiency is optimized and closely matches the efficiency of on-chip memory access (2pJ/b vs. 1pJ/b). Second, the viability of structured and coarse-grained sparsity optimization is highly algorithm dependent and requires explicit zero-detection blocks. Power optimization schemes for fine-grained or even arbitrary-sparsity patterns are lacking. Third, edge machine learning chips are cost sensitive. The conventional monolithic SoC design strategy, fabricating one specific SoC for each application, is not affordable in terms of NRE costs.
最近，内存计算宏(computing-in-memory, CIM)由于其超高的计算效率，被用于低功耗机器学习soc中[1]-[3]。CIM宏最初是为了减少人工智能任务对内存的密集访问而设计的。这些CIM宏仍然通过片上/片外存储器访问权重数据，类似于近内存计算体系结构中的处理元素。在计算整体SoC能效时，实现带来了挑战(图15.3.1)。首先，内存墙问题没有得到解决。当部署大型网络并发生大量片外权重数据传输时，权重更新会影响系统的整体性能。即使对于微小的机器学习任务，也不能忽视恒定权重更新的功耗和延迟，因为MAC计算效率经过优化，并且与片上存储器访问的效率(2pJ/b vs. 1pJ/b)非常匹配。其次，结构化和粗粒度稀疏性优化的可行性是高度依赖算法的，需要明确的零检测块。缺乏针对细粒度甚至任意稀疏模式的功率优化方案。第三，边缘机器学习芯片对成本敏感。传统的单片SoC设计策略，为每个应用制造一个特定的SoC，在NRE成本方面是不可承受的。
{"title":"COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning","authors":"Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yu-Jin Xie, Meilin Liu","doi":"10.1109/ISSCC42614.2022.9731657","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731657","url":null,"abstract":"Recently, computing-in-memory (CIM) macros, originally designed to reduce the intensive memory accesses of Al tasks, have been employed in low-power machine learning SoCs due to their ultra-high computing efficiency [1]–[3]. These CIM macros still access weight data through on/off-chip memories, similar to processing elements in near-memory-computing architectures. The implementation poses challenges when counting the overall SoC energy efficiency (Fig. 15.3.1). First, the memory wall issue is unsolved. The weight updates affect overall system performance when large networks are deployed and massive off-chip weight data transfer occurs. Even for tiny machine learning tasks, power consumption and latency of constant weight updates cannot be neglected, because MAC computing efficiency is optimized and closely matches the efficiency of on-chip memory access (2pJ/b vs. 1pJ/b). Second, the viability of structured and coarse-grained sparsity optimization is highly algorithm dependent and requires explicit zero-detection blocks. Power optimization schemes for fine-grained or even arbitrary-sparsity patterns are lacking. Third, edge machine learning chips are cost sensitive. The conventional monolithic SoC design strategy, fabricating one specific SoC for each application, is not affordable in terms of NRE costs.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"31 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82456368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731664
Ashutosh Verma, V. Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick T. McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, A. Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, S. Son, T. B. Cho
The 5G NR frequency band 2 (FR2) standard has evolved to support mm-wave bands spanning from 24 to 40 GHz. Single-band phased-array beam-forming ICs (BFIC) [1]–[3] for 5G have been demonstrated, however, the die size is large. This paper describes a 5G BFIC that supports both N257/N258/N261 (24.25 to 29.5GHz or Low-Band) and N260 (37 to 40GHz or High-Band) FR2 bands, each with 16 antenna ports and concurrent dual polarization for RX/TX, and its corresponding quad-stream intermediate-frequency IC (IFIC), supporting non-contiguous intra-band carrier aggregation (CA) up to 1.6GHz total bandwidth (BW). Figure 27.1.1 shows a 5G mobile phone, where multiple (3 to 4) BFICs, integrated with antenna modules, are placed in parallel and perpendicular to the phone screen for enhanced spherical coverage. BFICs and the antenna module have a skewed aspect ratio to support phone thickness requirement. A power-management IC is integrated on the module, which further reduces area available for the BFIC. However, a traditional BFIC die-size increases in proportion to the number of bands supported, and the IFIC size grows in order to have dedicated signal paths to support multiple BFICs. This paper introduces architecture and circuits techniques to enable area-efficient design of 5G FR2 transceivers.
{"title":"A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW","authors":"Ashutosh Verma, V. Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick T. McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, A. Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, S. Son, T. B. Cho","doi":"10.1109/ISSCC42614.2022.9731664","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731664","url":null,"abstract":"The 5G NR frequency band 2 (FR2) standard has evolved to support mm-wave bands spanning from 24 to 40 GHz. Single-band phased-array beam-forming ICs (BFIC) [1]–[3] for 5G have been demonstrated, however, the die size is large. This paper describes a 5G BFIC that supports both N257/N258/N261 (24.25 to 29.5GHz or Low-Band) and N260 (37 to 40GHz or High-Band) FR2 bands, each with 16 antenna ports and concurrent dual polarization for RX/TX, and its corresponding quad-stream intermediate-frequency IC (IFIC), supporting non-contiguous intra-band carrier aggregation (CA) up to 1.6GHz total bandwidth (BW). Figure 27.1.1 shows a 5G mobile phone, where multiple (3 to 4) BFICs, integrated with antenna modules, are placed in parallel and perpendicular to the phone screen for enhanced spherical coverage. BFICs and the antenna module have a skewed aspect ratio to support phone thickness requirement. A power-management IC is integrated on the module, which further reduces area available for the BFIC. However, a traditional BFIC die-size increases in proportion to the number of bands supported, and the IFIC size grows in order to have dedicated signal paths to support multiple BFICs. This paper introduces architecture and circuits techniques to enable area-efficient design of 5G FR2 transceivers.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81346584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731659
Dewei Wang, Chuan Lin, Gregory K. Chen, Phil V. Knag, R. Krishnamurthy, Mingoo Seok
In-memory-computing (IMC) SRAM architecture has gained significant attention as it achieves high energy efficiency for computing a convolutional neural network (CNN) model [1]. Recent works investigated the use of analog-mixed-signal (AMS) hardware for high area and energy efficiency [2], [3]. However, AMS hardware output is well known to be susceptible to process, voltage, and temperature (PVT) variations, limiting the computing precision and ultimately the inference accuracy of a CNN. We reconfirmed, through the simulation of a capacitor-based IMC SRAM macro that computes a 256D binary dot product, that the AMS computing hardware has a significant root-mean-square error (RMSE) of 22.5% across the worst-case voltage, temperature (Fig. 16.1.1 top left) and 3-sigma process variations (Fig. 16.1.1 top right). On the other hand, we can implement an IMC SRAM macro using robust digital logic [4], which can virtually eliminate the variability issue (Fig. 16.1.1 top). However, digital circuits require more devices than AMS counterparts (e.g., 28 transistors for a mirror full adder [FA]). As a result, a recent digital IMC SRAM shows a lower area efficiency of 6368F2/b (22nm, 4b/4b weight/activation) [5] than the AMS counterpart (1170F2/b, 65nm, 1b/1b) [3]. In light of this, we aim to adopt approximate arithmetic hardware to improve area and power efficiency and present two digital IMC macros (DIMC) with different levels of approximation (Fig. 16.1.1 bottom left). Also, we propose an approximation-aware training algorithm and a number format to minimize inference accuracy degradation induced by approximate hardware (Fig. 16.1.1 bottom right). We prototyped a 28nm test chip: for a 1b/1b CNN model for CIFAR-10 and across 0.5-to-1.1V supply, the DIMC with double-approximate hardware (DIMC-D) achieves 2569F2/b, 932-2219TOPS/W, 475-20032GOPS, and 86.96% accuracy, while for a 4b/1b CNN model, the DIMC with the single-approximate hardware (DIMC-S) achieves 3814F2/b, 458-990TOPS/W (normalized to 1b/1b), 405-19215GOPS (normalized to 1b/1b), and 90.41% accuracy.
{"title":"DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware","authors":"Dewei Wang, Chuan Lin, Gregory K. Chen, Phil V. Knag, R. Krishnamurthy, Mingoo Seok","doi":"10.1109/ISSCC42614.2022.9731659","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731659","url":null,"abstract":"In-memory-computing (IMC) SRAM architecture has gained significant attention as it achieves high energy efficiency for computing a convolutional neural network (CNN) model [1]. Recent works investigated the use of analog-mixed-signal (AMS) hardware for high area and energy efficiency [2], [3]. However, AMS hardware output is well known to be susceptible to process, voltage, and temperature (PVT) variations, limiting the computing precision and ultimately the inference accuracy of a CNN. We reconfirmed, through the simulation of a capacitor-based IMC SRAM macro that computes a 256D binary dot product, that the AMS computing hardware has a significant root-mean-square error (RMSE) of 22.5% across the worst-case voltage, temperature (Fig. 16.1.1 top left) and 3-sigma process variations (Fig. 16.1.1 top right). On the other hand, we can implement an IMC SRAM macro using robust digital logic [4], which can virtually eliminate the variability issue (Fig. 16.1.1 top). However, digital circuits require more devices than AMS counterparts (e.g., 28 transistors for a mirror full adder [FA]). As a result, a recent digital IMC SRAM shows a lower area efficiency of 6368F2/b (22nm, 4b/4b weight/activation) [5] than the AMS counterpart (1170F2/b, 65nm, 1b/1b) [3]. In light of this, we aim to adopt approximate arithmetic hardware to improve area and power efficiency and present two digital IMC macros (DIMC) with different levels of approximation (Fig. 16.1.1 bottom left). Also, we propose an approximation-aware training algorithm and a number format to minimize inference accuracy degradation induced by approximate hardware (Fig. 16.1.1 bottom right). We prototyped a 28nm test chip: for a 1b/1b CNN model for CIFAR-10 and across 0.5-to-1.1V supply, the DIMC with double-approximate hardware (DIMC-D) achieves 2569F2/b, 932-2219TOPS/W, 475-20032GOPS, and 86.96% accuracy, while for a 4b/1b CNN model, the DIMC with the single-approximate hardware (DIMC-S) achieves 3814F2/b, 458-990TOPS/W (normalized to 1b/1b), 405-19215GOPS (normalized to 1b/1b), and 90.41% accuracy.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"55 1","pages":"266-268"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81416929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731742
Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun
High-resolution ($>$ 100dB SNDR), kHz-BW ADCs are required by emerging Io $top$ and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of integration are also required, especially to be compatible with the advanced CMOS processes that the loT processor prefers. The state-of-the-art solutions in this scenario, such as the zoom ADC [1], the DT or CT-DSM [2]–[3], and the SAR ADC [4] and its noise-shaping variants [5], have already achieved great energy efficiency with >180dB FOMs. However, most of them are large in area, and rely heavily on the analog performance of old CMOS technologies with high supply voltages. In this work, we propose a new architecture that combines the counting ADC and CT-incremental-DSM (CT-IDSM) in a zoom ADC framework. The proposed architecture is not only power efficient, but also compact in area, highly digital, and friendly to process down-scaling. It operates at Nyquist sampling, supporting single-shot conversion and channel multiplexing. Besides this, it provides a high-impedance input with full-scale common-mode rejection, allowing direct driving by many signal sources. Fabricated in 28nm CMOS, the prototype zoom-incremental-counting (ZIC) ADC is measured to have 103dB SNDR at 20kSa/s, consuming 475 $mu$ W from a 0.9V supply. The resulting 176dB FOMs is comparable to the state-of-the-art designs. It occupies only 0.014mm2, which is a magnitude or two smaller than most reported ADCs with $>$ 90dB SNR.
{"title":"A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR","authors":"Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun","doi":"10.1109/ISSCC42614.2022.9731742","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731742","url":null,"abstract":"High-resolution ($>$ 100dB SNDR), kHz-BW ADCs are required by emerging Io $top$ and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of integration are also required, especially to be compatible with the advanced CMOS processes that the loT processor prefers. The state-of-the-art solutions in this scenario, such as the zoom ADC [1], the DT or CT-DSM [2]–[3], and the SAR ADC [4] and its noise-shaping variants [5], have already achieved great energy efficiency with >180dB FOMs. However, most of them are large in area, and rely heavily on the analog performance of old CMOS technologies with high supply voltages. In this work, we propose a new architecture that combines the counting ADC and CT-incremental-DSM (CT-IDSM) in a zoom ADC framework. The proposed architecture is not only power efficient, but also compact in area, highly digital, and friendly to process down-scaling. It operates at Nyquist sampling, supporting single-shot conversion and channel multiplexing. Besides this, it provides a high-impedance input with full-scale common-mode rejection, allowing direct driving by many signal sources. Fabricated in 28nm CMOS, the prototype zoom-incremental-counting (ZIC) ADC is measured to have 103dB SNDR at 20kSa/s, consuming 475 $mu$ W from a 0.9V supply. The resulting 176dB FOMs is comparable to the state-of-the-art designs. It occupies only 0.014mm2, which is a magnitude or two smaller than most reported ADCs with $>$ 90dB SNR.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"43 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80059822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731654
Jin-O Seo, Mingoo Seok, Seonghwan Cho
One of the notable trends in convolutional neural network (CNN) processor architecture is to embrace analog hardware to improve energy efficiency in performing multiply-and-accumulate (MAC). Prior works investigated charge redistribution in a capacitor array [4], [5], phase accumulation in oscillators [2], [6], and the integrator in a delta-sigma modulator [3]. However, these works suffer from two critical challenges. First, they all need frequent use of ADCs and DACs to store and access the large intermediate computation results, i.e. feature maps, to and from the digital SRAM. The energy consumption of such data conversion severely limits the overall energy efficiency. To mitigate it, [1] uses analog memory but only for temporary data and it still requires a large amount of data conversion for computing multiple layers of a CNN model. Second, analog circuits including analog memory inherently exhibit non-negligible variability. Important parameters such as comparator threshold voltage, oscillator frequency, etc., vary across process, voltage, and temperature (PVT), limiting the computing precision of analog hardware. It is critical to increase the tolerance to these variations. In this work, aiming to address these challenges, we propose ARCHON, an analog CNN processor featuring an analog neuronal computation unit (ANU) and an analog memory (AMEM). Designed to tolerate a large amount of PVT variations, ANU and AMEM can perform computations needed for a CNN model in the analog domain, across layers, without data conversions. Fabricated in 28nm CMOS, the proposed processor achieves a state-of-the-art energy-efficiency of 332.7TOPS/W (analog datapath) and 19.9TOPS/W (processor level), while maintaining the inference accuracy across supply voltage and temperature variations.
{"title":"ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory","authors":"Jin-O Seo, Mingoo Seok, Seonghwan Cho","doi":"10.1109/ISSCC42614.2022.9731654","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731654","url":null,"abstract":"One of the notable trends in convolutional neural network (CNN) processor architecture is to embrace analog hardware to improve energy efficiency in performing multiply-and-accumulate (MAC). Prior works investigated charge redistribution in a capacitor array [4], [5], phase accumulation in oscillators [2], [6], and the integrator in a delta-sigma modulator [3]. However, these works suffer from two critical challenges. First, they all need frequent use of ADCs and DACs to store and access the large intermediate computation results, i.e. feature maps, to and from the digital SRAM. The energy consumption of such data conversion severely limits the overall energy efficiency. To mitigate it, [1] uses analog memory but only for temporary data and it still requires a large amount of data conversion for computing multiple layers of a CNN model. Second, analog circuits including analog memory inherently exhibit non-negligible variability. Important parameters such as comparator threshold voltage, oscillator frequency, etc., vary across process, voltage, and temperature (PVT), limiting the computing precision of analog hardware. It is critical to increase the tolerance to these variations. In this work, aiming to address these challenges, we propose ARCHON, an analog CNN processor featuring an analog neuronal computation unit (ANU) and an analog memory (AMEM). Designed to tolerate a large amount of PVT variations, ANU and AMEM can perform computations needed for a CNN model in the analog domain, across layers, without data conversions. Fabricated in 28nm CMOS, the proposed processor achieves a state-of-the-art energy-efficiency of 332.7TOPS/W (analog datapath) and 19.9TOPS/W (processor level), while maintaining the inference accuracy across supply voltage and temperature variations.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"147 1","pages":"258-260"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85608388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-20DOI: 10.1109/ISSCC42614.2022.9731590
Ji-Hyoung Cha, Jee-Ho Park, Yongjae Park, Hyogeun Shin, K. Hwang, Il-Joo Cho, Seong-Jin Kim
It is crucial to investigate electrical activities from a single neuron and neuronal synapses in electrophysiology for brain research. Conventional physiological tools such as imaging and labeling are insufficient to cope with neural signals from cells distributed over a large area [1]. Microelectrode array (MEA) systems featuring high-density electrodes and low-noise analog front-ends (AFE) have been representative solutions to acquire intracellular and extracellular potentials from in vitro multiple neurons [2 – 7]. Although the number of electrodes in MEA systems and their spatial resolution are increased thanks to advances in CMOS technology, they still suffer from area constraints in the low - noise AFE and connection complexity from electrodes to corresponding AFE channels. Since neurons are not fully activated and not evenly distributed after being cultivated on an MEA, a full scanning of electrodes in active pixel sensors (APS) is not efficient in terms of power consumption and noise performance [2 – 4]. A switch - matrix (SM) architecture offers high flexibility to select and record electrodes of interest through configuring the switches to randomly connect them to AFE channels, improving efficiency [5,6]. However, a large AFE channel dedicated to an electrode with a small pitch of a few pm limits the scalability in both APS and SM architectures. The more electrodes are integrated into the system, the more complicated the routing connections become, worsening scalability. In this paper, an MEA system with a sub-array multiplexing (SAM) architecture is presented for programmable electrode selection and readout speed to maximize the ratio of the number of recorded electrodes per frame to the total number of electrodes, called an electrode yield. A time-multiplexing scheme allows each AFE channel in a column to record multiple electrodes one-by-one in a given sampling time, alleviating the routing complexity and the number of AFE channels. The reconfigurable SAM provides a pseudo-random connection of electrodes, so that extracellular signals from a single neuron as well as neural synapses can be effectively recorded.
{"title":"A Reconfigurable Sub-Array Multiplexing Microelectrode Array System With 24,320 Electrodes and 380 Readout Channels for Investigating Neural Communication","authors":"Ji-Hyoung Cha, Jee-Ho Park, Yongjae Park, Hyogeun Shin, K. Hwang, Il-Joo Cho, Seong-Jin Kim","doi":"10.1109/ISSCC42614.2022.9731590","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731590","url":null,"abstract":"It is crucial to investigate electrical activities from a single neuron and neuronal synapses in electrophysiology for brain research. Conventional physiological tools such as imaging and labeling are insufficient to cope with neural signals from cells distributed over a large area [1]. Microelectrode array (MEA) systems featuring high-density electrodes and low-noise analog front-ends (AFE) have been representative solutions to acquire intracellular and extracellular potentials from in vitro multiple neurons [2 – 7]. Although the number of electrodes in MEA systems and their spatial resolution are increased thanks to advances in CMOS technology, they still suffer from area constraints in the low - noise AFE and connection complexity from electrodes to corresponding AFE channels. Since neurons are not fully activated and not evenly distributed after being cultivated on an MEA, a full scanning of electrodes in active pixel sensors (APS) is not efficient in terms of power consumption and noise performance [2 – 4]. A switch - matrix (SM) architecture offers high flexibility to select and record electrodes of interest through configuring the switches to randomly connect them to AFE channels, improving efficiency [5,6]. However, a large AFE channel dedicated to an electrode with a small pitch of a few pm limits the scalability in both APS and SM architectures. The more electrodes are integrated into the system, the more complicated the routing connections become, worsening scalability. In this paper, an MEA system with a sub-array multiplexing (SAM) architecture is presented for programmable electrode selection and readout speed to maximize the ratio of the number of recorded electrodes per frame to the total number of electrodes, called an electrode yield. A time-multiplexing scheme allows each AFE channel in a column to record multiple electrodes one-by-one in a given sampling time, alleviating the routing complexity and the number of AFE channels. The reconfigurable SAM provides a pseudo-random connection of electrodes, so that extracellular signals from a single neuron as well as neural synapses can be effectively recorded.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"2014 1","pages":"342-344"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87921333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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