This article reported the impact of mechanical bending on Indium gallium zinc oxide (IGZO) thin film transistor (TFT) with single gate electrode for wearable electrics devices for its reliability analysis. The deformation caused by mechanical bending caused a strain in the active layer of IGZO in TFTs. This strain is compressive and tensile in the parallel and perpendicular direction of current conduction. Mechanical bending is induced by a change in the radius of curvature (R$= 1~mu $ m to $10~mu $ m). For smaller radii (0 > R $gt 2~mu $ m), the strain is higher for IGZO TFTs. The radius of curvature also influences the electrical performance matrices. In this paper, the charge carrier mobility, electron concentration, drain current, and threshold voltage shift are also evaluated with variations in the radius of curvature. Furthermore, the compressive strain degrades mobility, and tensile strain enhances mobility depending on the radii of curvature. Thus, the radii less than $3~mu $ m, the degraded reliability for IGZO TFTs has been observed in terms of threshold voltage shift and I${}_{mathbf {ON}}$ /I${}_{mathbf {OFF}}$ ratio ($Delta $ V${}_{mathbf {th}} =-116.7$ % and I${}_{mathbf {ON}}$ /I${}_{mathbf {OFF}} =-132.9$ %), respectively.
{"title":"Reliability Analysis of IGZO Thin-Film Transistor for Wearable Biosensing Applications","authors":"Anchal Thakur;Samriti Sharma;Jaya Madan;Rahul Pandey","doi":"10.1109/TDMR.2026.3684091","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3684091","url":null,"abstract":"This article reported the impact of mechanical bending on Indium gallium zinc oxide (IGZO) thin film transistor (TFT) with single gate electrode for wearable electrics devices for its reliability analysis. The deformation caused by mechanical bending caused a strain in the active layer of IGZO in TFTs. This strain is compressive and tensile in the parallel and perpendicular direction of current conduction. Mechanical bending is induced by a change in the radius of curvature (R<inline-formula> <tex-math>$= 1~mu $ </tex-math></inline-formula>m to <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m). For smaller radii (0 > R <inline-formula> <tex-math>$gt 2~mu $ </tex-math></inline-formula>m), the strain is higher for IGZO TFTs. The radius of curvature also influences the electrical performance matrices. In this paper, the charge carrier mobility, electron concentration, drain current, and threshold voltage shift are also evaluated with variations in the radius of curvature. Furthermore, the compressive strain degrades mobility, and tensile strain enhances mobility depending on the radii of curvature. Thus, the radii less than <inline-formula> <tex-math>$3~mu $ </tex-math></inline-formula>m, the degraded reliability for IGZO TFTs has been observed in terms of threshold voltage shift and I<inline-formula> <tex-math>${}_{mathbf {ON}}$ </tex-math></inline-formula>/I<inline-formula> <tex-math>${}_{mathbf {OFF}}$ </tex-math></inline-formula> ratio (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}_{mathbf {th}} =-116.7$ </tex-math></inline-formula>% and I<inline-formula> <tex-math>${}_{mathbf {ON}}$ </tex-math></inline-formula>/I<inline-formula> <tex-math>${}_{mathbf {OFF}} =-132.9$ </tex-math></inline-formula>%), respectively.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"637-644"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel SiC MOSFET with hole compensation structure in edge termination (HC-MOS) is proposed with the intention of single-event burnout (SEB) hardening. The embedded N+ region beneath the metal electrode within edge termination suppresses the peak temperature of the metal electrode in the edge termination region by enlarging the hole recombination area and accelerating the process of hole recombination, which significantly reduces the electric field near the metal electrode and increases the recombination rate of holes. When heavy ions strike the device with a linear energy transfer (LET) of 80 MeV$cdot $ cm2/mg near the metal electrode under $V_{mathrm {DS}} =600$ V, the HC-MOS induces a 62% reduction in the peak temperature at the metal/SiC junction compared with the conventional SiC MOSFET (C-MOS). Furthermore, the peak temperature at metal/SiC junction decreases from 2219 K to 1464 K when heavy ions strike at the metal/SiO2/SiC intersection. These results indicate that HC-MOS provide a new insight for SEB hardening.
{"title":"Investigation of Single-Event Burnout in SiC MOSFET With Radiation-Hardened Edge Termination Structure","authors":"Gu Gong;Xiaochuan Deng;Xuke Yan;Xing Zeng;Haibo Wu;Xuan Li;Bo Zhang","doi":"10.1109/TDMR.2026.3692253","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3692253","url":null,"abstract":"A novel SiC MOSFET with hole compensation structure in edge termination (HC-MOS) is proposed with the intention of single-event burnout (SEB) hardening. The embedded N+ region beneath the metal electrode within edge termination suppresses the peak temperature of the metal electrode in the edge termination region by enlarging the hole recombination area and accelerating the process of hole recombination, which significantly reduces the electric field near the metal electrode and increases the recombination rate of holes. When heavy ions strike the device with a linear energy transfer (LET) of 80 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm<sup>2</sup>/mg near the metal electrode under <inline-formula> <tex-math>$V_{mathrm {DS}} =600$ </tex-math></inline-formula> V, the HC-MOS induces a 62% reduction in the peak temperature at the metal/SiC junction compared with the conventional SiC MOSFET (C-MOS). Furthermore, the peak temperature at metal/SiC junction decreases from 2219 K to 1464 K when heavy ions strike at the metal/SiO<sub>2</sub>/SiC intersection. These results indicate that HC-MOS provide a new insight for SEB hardening.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"616-622"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-04-22DOI: 10.1109/TDMR.2026.3686494
Ciro Scognamillo;Antonio Pio Catalano;Michael Schröter;Vincenzo d'Alessandro
This paper deals with compact electrothermal (ET) models accounting for nonlinear thermal effects in heterojunction bipolar transistors (HBTs). In a previous investigation, the Authors have demonstrated that the thermal resistance formulations embedded in advanced compact bipolar transistor models fall short in describing such nonlinear effects over wide ranges of operative conditions. Here, a formulation based on the single-semiconductor theory is proposed and implemented in HICUM/L2, the most adopted compact model in the radiofrequency (RF) industry. The accuracy of the proposed modeling approach is experimentally verified by comparison with measurements performed on a state-of-the-art InP/InGaAs HBT for RF applications. Once the accuracy of such a formulation is assessed, the improved HICUM/L2 is exploited to estimate the safe operating area (SOA) and the junction temperature of the HBT under test.
{"title":"Aiding Thermal-Aware Design of HBTs Through Nonlinear Electrothermal Modeling","authors":"Ciro Scognamillo;Antonio Pio Catalano;Michael Schröter;Vincenzo d'Alessandro","doi":"10.1109/TDMR.2026.3686494","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3686494","url":null,"abstract":"This paper deals with compact electrothermal (ET) models accounting for nonlinear thermal effects in heterojunction bipolar transistors (HBTs). In a previous investigation, the Authors have demonstrated that the thermal resistance formulations embedded in advanced compact bipolar transistor models fall short in describing such nonlinear effects over wide ranges of operative conditions. Here, a formulation based on the single-semiconductor theory is proposed and implemented in HICUM/L2, the most adopted compact model in the radiofrequency (RF) industry. The accuracy of the proposed modeling approach is experimentally verified by comparison with measurements performed on a state-of-the-art InP/InGaAs HBT for RF applications. Once the accuracy of such a formulation is assessed, the improved HICUM/L2 is exploited to estimate the safe operating area (SOA) and the junction temperature of the HBT under test.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"549-555"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, total-ionizing-dose (TID) radiation effect on current gain ($h_{mathrm {FE}}$ ) for bipolar junction transistor (BJT) based 18 V BCD technology is investigated. For post-irradiation, base current ($I_{mathrm {B}}$ ) is increased and collector current is almost unchanged, leading to $h_{mathrm {FE}}$ decreasing. Irradiation charge modulation mechanism is revealed by simulation and experiment. Irradiation charge in oxide layer would lower surface energy band, and promote surface depletion. Recombination of electron and hole is enhanced, which gives rise to $I_{mathrm {B}}$ increasing and $h_{mathrm {FE}}$ decreasing. Based on the mechanism, a radiation hardened structure with the P-top layer in PW region is proposed to suppress surface recombination rate. Experiment results show that TID tolerance exceeds 300 krad(Si) for the proposed radiation hardened BJT structure, beyond 10 times that for the conventional structure.
{"title":"Total-Ionizing-Dose Radiation Effect on Current Gain for Bipolar Junction Transistor Based 18 V BCD Technology","authors":"Xin Zhou;Hongze Chu;Yanfei Li;Shenghuai Liu;Hong Peng;Hao Jiang;Rubin Xie;Bo Zhang","doi":"10.1109/TDMR.2026.3669599","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3669599","url":null,"abstract":"In this article, total-ionizing-dose (TID) radiation effect on current gain (<inline-formula> <tex-math>$h_{mathrm {FE}}$ </tex-math></inline-formula>) for bipolar junction transistor (BJT) based 18 V BCD technology is investigated. For post-irradiation, base current (<inline-formula> <tex-math>$I_{mathrm {B}}$ </tex-math></inline-formula>) is increased and collector current is almost unchanged, leading to <inline-formula> <tex-math>$h_{mathrm {FE}}$ </tex-math></inline-formula> decreasing. Irradiation charge modulation mechanism is revealed by simulation and experiment. Irradiation charge in oxide layer would lower surface energy band, and promote surface depletion. Recombination of electron and hole is enhanced, which gives rise to <inline-formula> <tex-math>$I_{mathrm {B}}$ </tex-math></inline-formula> increasing and <inline-formula> <tex-math>$h_{mathrm {FE}}$ </tex-math></inline-formula> decreasing. Based on the mechanism, a radiation hardened structure with the P-top layer in PW region is proposed to suppress surface recombination rate. Experiment results show that TID tolerance exceeds 300 krad(Si) for the proposed radiation hardened BJT structure, beyond 10 times that for the conventional structure.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"510-515"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-14DOI: 10.1109/TDMR.2026.3693258
T. Takeshita;Y. Abe
The degradation and improvement of solar cells exhibiting small changes in the dark current during reverse bias and high-temperature (BT) aging were investigated using the laser-beam-induced current (LBIC) technique. The solar cell degraded over the entire surface near the p–n junction. In addition, we observed fewer recombination centers in the n-type Si layer than near the p–n junction. The dark current during aging gradually decreased and became saturated between 100 and 1000 h. Defects were supplied upward from the vicinity of the p–n junction to the n-type Si layer, which led to a reduction in the recombination centers near the p–n junction. Furthermore, the dark current increased slightly from 1000 h to 6500 h, which was attributed to defect multiplication near the p–n junction and defect migration to the n-type Si layer. We presume that an n-type Si layer with a low number of recombination centers acts as a blocking layer for defects on the surface. The LBIC technique is useful for analyzing the degradation of solar cells at several wavelengths.
{"title":"Analysis of Degradation and Improvement in Solar Cells Using Laser-Beam-Induced Current Technique","authors":"T. Takeshita;Y. Abe","doi":"10.1109/TDMR.2026.3693258","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3693258","url":null,"abstract":"The degradation and improvement of solar cells exhibiting small changes in the dark current during reverse bias and high-temperature (BT) aging were investigated using the laser-beam-induced current (LBIC) technique. The solar cell degraded over the entire surface near the p–n junction. In addition, we observed fewer recombination centers in the n-type Si layer than near the p–n junction. The dark current during aging gradually decreased and became saturated between 100 and 1000 h. Defects were supplied upward from the vicinity of the p–n junction to the n-type Si layer, which led to a reduction in the recombination centers near the p–n junction. Furthermore, the dark current increased slightly from 1000 h to 6500 h, which was attributed to defect multiplication near the p–n junction and defect migration to the n-type Si layer. We presume that an n-type Si layer with a low number of recombination centers acts as a blocking layer for defects on the surface. The LBIC technique is useful for analyzing the degradation of solar cells at several wavelengths.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"623-628"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper analyzes the effect of the trapping-state-trap at the $text {Si/SiO}_{2}$ interface from the perspective of leakage current reliability in Buried-Channel-Array Transistor(BCAT). This research reveals that BCAT is vulnerable to Gate Induced Drain Leakage(GIDL) caused by trapping-state-trap. When trapping-state-trap is located in the gate/drain overlap region, they increase Band-to-Band Tunneling(BTBT) because a strong local electric-field is formed, worsening GIDL. This paper defines the GIDL increase by this trapping-state-trap mechanism as Trapping-State-Trap Induced Drain Leakage(TTIDL), which causes the worst-case leakage current in BCAT and degrades DRAM reliability. To evaluate the TTIDL, this study proposes a BCAT TTIDL-optimized evaluation method, which is based on the TTIDL dominant generation mechanism, BTBT. Additionally, we propose Partial Insulator BCAT(Pi-BCAT) as a TTIDL reduction structure and compares its TTIDL characteristics with conventional BCAT using the proposed evaluation method. The results reveal that Pi-BCAT shows an approximately 50% reduction in TTIDL at the tail and temperature dependence compared to BCAT.
{"title":"Analysis and Structural Mitigation of Trapping-State-Trap Induced Drain Leakage Current in Buried-Channel-Array Transistor","authors":"Jeonghyeon Yun;Suyeon Kim;Dongyeong Kim;Jewon Park;Sinwook Kim;Ryun Kang;Chaehyuk Lim;Sowon Kim;Hyeona Seo;Hyerin Lee;Juwon Lee;Geon Kim;Myoungjin Lee","doi":"10.1109/TDMR.2026.3684027","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3684027","url":null,"abstract":"This paper analyzes the effect of the trapping-state-trap at the <inline-formula> <tex-math>$text {Si/SiO}_{2}$ </tex-math></inline-formula> interface from the perspective of leakage current reliability in Buried-Channel-Array Transistor(BCAT). This research reveals that BCAT is vulnerable to Gate Induced Drain Leakage(GIDL) caused by trapping-state-trap. When trapping-state-trap is located in the gate/drain overlap region, they increase Band-to-Band Tunneling(BTBT) because a strong local electric-field is formed, worsening GIDL. This paper defines the GIDL increase by this trapping-state-trap mechanism as Trapping-State-Trap Induced Drain Leakage(TTIDL), which causes the worst-case leakage current in BCAT and degrades DRAM reliability. To evaluate the TTIDL, this study proposes a BCAT TTIDL-optimized evaluation method, which is based on the TTIDL dominant generation mechanism, BTBT. Additionally, we propose Partial Insulator BCAT(Pi-BCAT) as a TTIDL reduction structure and compares its TTIDL characteristics with conventional BCAT using the proposed evaluation method. The results reveal that Pi-BCAT shows an approximately 50% reduction in TTIDL at the tail and temperature dependence compared to BCAT.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"594-603"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accurate lifetime prediction of power devices is critical for preventing unexpected converter failures and extending service life. However, existing methods often suffer from limited prediction accuracy, reliance on extensive experiments, and difficulties in practical implementation. This paper proposes a data-driven lifetime estimation method for silicon carbide (SiC) MOSFETs based on the prediction of a single aging precursor, i.e., the on-state drain-source voltage drop ($V_{mathrm {ds_on}}$ ). The proposed method integrates the local feature extraction capability of convolutional neural networks (CNNs) with the temporal modeling strength of long short-term memory (LSTM) networks, enabling effective capture of complex degradation trends and improved prediction accuracy. Moreover, it facilitates practical implementation, as $V_{mathrm {ds_on}}$ is easy to measure online during normal operation. A DC power cycling test setup with online $V_{mathrm {ds_on}}$ sampling is designed to accelerate device aging and collect degradation datasets. Multiple devices can be aged simultaneously under different operating conditions using the proposed setup, improving test efficiency. Experimental results under various aging conditions demonstrate that the proposed method achieves the highest prediction accuracy of 99.3%, outperforming the LSTM-based and exponential model-based approaches, which achieve average accuracies of 96.4% and 41.1%, respectively. These advancements are beneficial for enhancing system reliability and reducing operational costs in practical applications.
{"title":"A High Accuracy Lifetime Estimation Method for SiC MOSFETs Based on CNN-LSTM Networks","authors":"Xiaofeng Ding;Binbin Wang;Yanyong Yang;Mingbo Zhao;Kun Yang;Lyuzhang Peng","doi":"10.1109/TDMR.2026.3673635","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3673635","url":null,"abstract":"Accurate lifetime prediction of power devices is critical for preventing unexpected converter failures and extending service life. However, existing methods often suffer from limited prediction accuracy, reliance on extensive experiments, and difficulties in practical implementation. This paper proposes a data-driven lifetime estimation method for silicon carbide (SiC) MOSFETs based on the prediction of a single aging precursor, i.e., the on-state drain-source voltage drop (<inline-formula> <tex-math>$V_{mathrm {ds_on}}$ </tex-math></inline-formula>). The proposed method integrates the local feature extraction capability of convolutional neural networks (CNNs) with the temporal modeling strength of long short-term memory (LSTM) networks, enabling effective capture of complex degradation trends and improved prediction accuracy. Moreover, it facilitates practical implementation, as <inline-formula> <tex-math>$V_{mathrm {ds_on}}$ </tex-math></inline-formula> is easy to measure online during normal operation. A DC power cycling test setup with online <inline-formula> <tex-math>$V_{mathrm {ds_on}}$ </tex-math></inline-formula> sampling is designed to accelerate device aging and collect degradation datasets. Multiple devices can be aged simultaneously under different operating conditions using the proposed setup, improving test efficiency. Experimental results under various aging conditions demonstrate that the proposed method achieves the highest prediction accuracy of 99.3%, outperforming the LSTM-based and exponential model-based approaches, which achieve average accuracies of 96.4% and 41.1%, respectively. These advancements are beneficial for enhancing system reliability and reducing operational costs in practical applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"531-540"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-02-18DOI: 10.1109/TDMR.2026.3666023
Subhajit Roy Chowdhury;Sudipta Chakrabarty;Suman Santra;Saddam Khan;Syed Minhaz Hossain
This work explores the electroluminescence performance and long-term stability of silver contact nanostructured silicon Schottky junction LEDs under prolonged DC bias. Si-based LEDs are increasingly sought for all-silicon integrated photonic circuits due to their compatibility with monolithic CMOS integration technology. Although their external quantum efficiency remains lower than that of commercial LEDs, NSi-based LEDs show promise for applications in quantum optics, including quantum random number generation and high-speed on-chip optical communication systems. While numerous studies have addressed factors influencing electroluminescence in nanostructured silicon devices, such as work function and transparency of the contact, injection, radiative recombination, and light extraction efficiencies, long-term spectral stability remains largely unexplored. A key factor is the non-stoichiometric native oxide layer that forms on nanostructured silicon and gets modified due to Joule heating under prolonged electrical bias. This alteration influences charge injection dynamics and affects overall device performance over time. In this study, we systematically investigate how this oxide layer governs injection efficiency and temporal stability of EL emission, including peak energy and intensity. A simple equivalent circuit is employed to account for current components associated with injection and heating. Our results indicate that the oxide layer modulates carrier injection as well as plays a stabilizing role in the output spectrum over extended operation. The calculated luminescence characteristics of the LEDs qualitatively align with experimental findings that offer valuable insights into mechanisms affecting the performance and reliability of silicon nanodevices.
{"title":"Stability in Electroluminescence From Ag-NSi Schottky Junction LED: Role of Ambient Oxidation","authors":"Subhajit Roy Chowdhury;Sudipta Chakrabarty;Suman Santra;Saddam Khan;Syed Minhaz Hossain","doi":"10.1109/TDMR.2026.3666023","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3666023","url":null,"abstract":"This work explores the electroluminescence performance and long-term stability of silver contact nanostructured silicon Schottky junction LEDs under prolonged DC bias. Si-based LEDs are increasingly sought for all-silicon integrated photonic circuits due to their compatibility with monolithic CMOS integration technology. Although their external quantum efficiency remains lower than that of commercial LEDs, NSi-based LEDs show promise for applications in quantum optics, including quantum random number generation and high-speed on-chip optical communication systems. While numerous studies have addressed factors influencing electroluminescence in nanostructured silicon devices, such as work function and transparency of the contact, injection, radiative recombination, and light extraction efficiencies, long-term spectral stability remains largely unexplored. A key factor is the non-stoichiometric native oxide layer that forms on nanostructured silicon and gets modified due to Joule heating under prolonged electrical bias. This alteration influences charge injection dynamics and affects overall device performance over time. In this study, we systematically investigate how this oxide layer governs injection efficiency and temporal stability of EL emission, including peak energy and intensity. A simple equivalent circuit is employed to account for current components associated with injection and heating. Our results indicate that the oxide layer modulates carrier injection as well as plays a stabilizing role in the output spectrum over extended operation. The calculated luminescence characteristics of the LEDs qualitatively align with experimental findings that offer valuable insights into mechanisms affecting the performance and reliability of silicon nanodevices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"492-502"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-20DOI: 10.1109/TDMR.2026.3676003
Amit Sarkar;P. Srinivasan;Abhisek Dixit
This paper presents a Semi-empirical Reliability Model for Hot-Carrier Degradation (HCD) in FinFET LDMOS devices. Unlike planar LDMOS, FinFET LDMOS exhibits non-saturating HCD over prolonged operation, due to its distinct three-dimensional geometry, which affects electric field distribution and carrier transport mechanisms. Traditional degradation models, such as the time slope exponent and bond dissociation (BD) approaches do not adequately capture this unique degradation due to the 3D structural complexities of FinFET LDMOS. To address this limitation, an enhanced model to account for HCD in FinFET LDMOS is introduced in this paper, significantly improving predictive accuracy for device lifetime. Hot-carrier Degradation for FinFET LDMOS is also characterized with variation in drain to source stress bias and number of fins (NFIN). When all other design parameters remain same, HCD increases with an increase in the drain-to-source stress voltage and reduces with an increase in the number of fins (NFIN).
{"title":"Semi-Empirical Modeling of Hot Carrier Degradation in 12-nm FinFET LDMOS Devices","authors":"Amit Sarkar;P. Srinivasan;Abhisek Dixit","doi":"10.1109/TDMR.2026.3676003","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3676003","url":null,"abstract":"This paper presents a Semi-empirical Reliability Model for Hot-Carrier Degradation (HCD) in FinFET LDMOS devices. Unlike planar LDMOS, FinFET LDMOS exhibits non-saturating HCD over prolonged operation, due to its distinct three-dimensional geometry, which affects electric field distribution and carrier transport mechanisms. Traditional degradation models, such as the time slope exponent and bond dissociation (BD) approaches do not adequately capture this unique degradation due to the 3D structural complexities of FinFET LDMOS. To address this limitation, an enhanced model to account for HCD in FinFET LDMOS is introduced in this paper, significantly improving predictive accuracy for device lifetime. Hot-carrier Degradation for FinFET LDMOS is also characterized with variation in drain to source stress bias and number of fins (<bold>NFIN</b>). When all other design parameters remain same, HCD increases with an increase in the drain-to-source stress voltage and reduces with an increase in the number of fins (<bold>NFIN</b>).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"444-450"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-06-11DOI: 10.1109/TDMR.2026.3696480
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2026.3696480","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3696480","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11559149","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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