Pub Date : 2026-06-01Epub Date: 2026-02-26DOI: 10.1109/TDMR.2026.3668390
Ruma S. R.;Manish Gupta
Through well-calibrated simulations, this work presents a comprehensive analysis of process-induced variations in on-current ($I_{mathrm {ON}}$ ), off-current ($I_{mathrm {OFF}}$ ), and threshold voltage ($V_{mathrm {th}}$ ) for negative capacitance (NC) junctionless (JL) transistors designed on bulk substrate. The performance and variability metrics are benchmarked against SOI-based NCJL transistors. The results reveal a significant reduction in $sigma (I_{mathrm {ON}})$ , $sigma (I_{mathrm {OFF}})$ , and $sigma (V_{mathrm {th}})$ due to the variation in geometrical device parameters in bulk NCJL devices. The outperformance is primarily due to the shift in the conduction channel towards the front surface, which enhances the effectiveness of the negative capacitance effect in bulk NCJL device. In addition, the lower variability observed in bulk NCJL devices translates into improved noise margin (NM) and reduced process-induced NM fluctuations in inverter circuits. Results reported for the first time demonstrate the enhanced device- and circuit-level performance of bulk NCJL transistors in comparison to their SOI counterparts.
{"title":"Mitigating the Process Variations in Negative Capacitance Junctionless Device and Circuit","authors":"Ruma S. R.;Manish Gupta","doi":"10.1109/TDMR.2026.3668390","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3668390","url":null,"abstract":"Through well-calibrated simulations, this work presents a comprehensive analysis of process-induced variations in on-current (<inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula>), off-current (<inline-formula> <tex-math>$I_{mathrm {OFF}}$ </tex-math></inline-formula>), and threshold voltage (<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>) for negative capacitance (NC) junctionless (JL) transistors designed on bulk substrate. The performance and variability metrics are benchmarked against SOI-based NCJL transistors. The results reveal a significant reduction in <inline-formula> <tex-math>$sigma (I_{mathrm {ON}})$ </tex-math></inline-formula>, <inline-formula> <tex-math>$sigma (I_{mathrm {OFF}})$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$sigma (V_{mathrm {th}})$ </tex-math></inline-formula> due to the variation in geometrical device parameters in bulk NCJL devices. The outperformance is primarily due to the shift in the conduction channel towards the front surface, which enhances the effectiveness of the negative capacitance effect in bulk NCJL device. In addition, the lower variability observed in bulk NCJL devices translates into improved noise margin (<italic>NM</i>) and reduced process-induced <italic>NM</i> fluctuations in inverter circuits. Results reported for the first time demonstrate the enhanced device- and circuit-level performance of bulk NCJL transistors in comparison to their SOI counterparts.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"503-509"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flexible electronic substrates, as the critical constituent of flexible electronic devices and systems, are essential for component interconnection and overall structural flexibility. During service, they are routinely subjected to diverse temperature–humidity environments and static bending conditions. These external factors progressively induce material ageing and deterioration of electrical interconnect performance. The actual occurrence of ageing in flexible electronic substrates was experimentally confirmed by subjecting them to accelerated ageing tests. Electrical resistance was employed as the ageing indicator. The influence mechanisms of temperature–humidity conditions, bending radius, and specimen specifications on the ageing process were systematically quantified. A physics-based characterization model for the ageing effect was subsequently derived. A hybrid physics-informed neural network (PINN) was then constructed and trained to predict resistance evolution. The model achieved a mean relative error of 0.02% against measured data, demonstrating its validity and high accuracy. This work provides a direct quantitative basis for reliability assessment and performance-degradation prediction of flexible-substrate-based electronic devices. It thus potentially offers valuable support for ensuring and enhancing product quality and operational lifetime.
{"title":"Experimental Investigation Into Ageing Mechanisms and Behavior Prediction Model of Flexible Electronic Substrates Under Temperature–Humidity–Bending Conditions","authors":"Zhifeng He;Kaixuan Wang;Mingmin Zhu;Haibin Zhu;Hao-Miao Zhou","doi":"10.1109/TDMR.2026.3674172","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3674172","url":null,"abstract":"Flexible electronic substrates, as the critical constituent of flexible electronic devices and systems, are essential for component interconnection and overall structural flexibility. During service, they are routinely subjected to diverse temperature–humidity environments and static bending conditions. These external factors progressively induce material ageing and deterioration of electrical interconnect performance. The actual occurrence of ageing in flexible electronic substrates was experimentally confirmed by subjecting them to accelerated ageing tests. Electrical resistance was employed as the ageing indicator. The influence mechanisms of temperature–humidity conditions, bending radius, and specimen specifications on the ageing process were systematically quantified. A physics-based characterization model for the ageing effect was subsequently derived. A hybrid physics-informed neural network (PINN) was then constructed and trained to predict resistance evolution. The model achieved a mean relative error of 0.02% against measured data, demonstrating its validity and high accuracy. This work provides a direct quantitative basis for reliability assessment and performance-degradation prediction of flexible-substrate-based electronic devices. It thus potentially offers valuable support for ensuring and enhancing product quality and operational lifetime.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"475-484"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-04DOI: 10.1109/TDMR.2026.3689949
Guangjie Zhu;Xiangshun Li;Song Xiong;Cheng Wang
Silicon carbide power devices, representing third-generation semiconductors, are widely used in the areas of industrial control, rail transportation, electric vehicles, and renewable energy. As crucial components of power electronic systems, their reliability is vital to the safe operation of entire systems. Temperature is a critical factor affecting device reliability, and junction temperature serves as a key indicator reflecting the thermal state of the device. Accurate monitoring of junction temperature is therefore essential for tracking device conditions and assessing reliability. This paper provides a comparative review of advances in junction temperature monitoring for silicon carbide-based power devices, systematically analyzing four primary methods: thermal network model, temperature-sensitive electrical parameter, physical contact sensing, and non-contact optical methods. The principles, advantages and limitations as well as applicable situations of each method are analyzed in detail. Furthermore, the evolutionary trajectory of the estimation methods and associated validation techniques are summarized. Finally, challenges and future prospects for junction temperature monitoring for silicon carbide-based power devices are presented. This review concludes that temperature-sensitive electrical parameters method represent the most promising technique for future junction temperature monitoring. Nevertheless, significant challenges persist, particularly in relation to aging-induced coupling and the complexities of accurate parameter extraction. The purpose of this review is to provide helpful theoretical support and methodological guidance to researchers in related fields.
{"title":"A Comparative Review of Junction Temperature Monitoring for SiC-Based Power Semiconductor Devices","authors":"Guangjie Zhu;Xiangshun Li;Song Xiong;Cheng Wang","doi":"10.1109/TDMR.2026.3689949","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3689949","url":null,"abstract":"Silicon carbide power devices, representing third-generation semiconductors, are widely used in the areas of industrial control, rail transportation, electric vehicles, and renewable energy. As crucial components of power electronic systems, their reliability is vital to the safe operation of entire systems. Temperature is a critical factor affecting device reliability, and junction temperature serves as a key indicator reflecting the thermal state of the device. Accurate monitoring of junction temperature is therefore essential for tracking device conditions and assessing reliability. This paper provides a comparative review of advances in junction temperature monitoring for silicon carbide-based power devices, systematically analyzing four primary methods: thermal network model, temperature-sensitive electrical parameter, physical contact sensing, and non-contact optical methods. The principles, advantages and limitations as well as applicable situations of each method are analyzed in detail. Furthermore, the evolutionary trajectory of the estimation methods and associated validation techniques are summarized. Finally, challenges and future prospects for junction temperature monitoring for silicon carbide-based power devices are presented. This review concludes that temperature-sensitive electrical parameters method represent the most promising technique for future junction temperature monitoring. Nevertheless, significant challenges persist, particularly in relation to aging-induced coupling and the complexities of accurate parameter extraction. The purpose of this review is to provide helpful theoretical support and methodological guidance to researchers in related fields.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"409-434"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-12DOI: 10.1109/TDMR.2026.3673394
Pengkai Wang;Yuan Chen;Yangtao Long;Hu He;Junhui Li
As promising candidates for high-performance power system applications, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have garnered significant attention from the market. However, reliability challenges, particularly under real-world operating conditions involving multi-stress scenarios, remained to be thoroughly investigated. This study systematically examined the impact of varying levels of power cycling (PCT) degradation on the short-circuit (SC) ruggedness of 1.2 kV SiC MOSFET power modules. The changes in DC parameters and defect density during the multi-stresses were quantitatively analyzed, and the failure mechanism was validated through simulations. Additionally, the results revealed that the short-circuit withstand time (SCWT) decreased significantly with progressive levels of PCT aging. This work provides insights into the reliability and operational lifespan of SiC MOSFET under real-world operating conditions.
作为高性能电力系统应用的有前途的候选者，碳化硅（SiC）金属氧化物半导体场效应晶体管（mosfet）已经引起了市场的极大关注。然而，可靠性方面的挑战，特别是在涉及多应力场景的实际操作条件下，仍有待深入研究。本研究系统地研究了不同水平的功率循环（PCT）退化对1.2 kV SiC MOSFET功率模块短路（SC）坚固性的影响。定量分析了多应力作用下直流参数和缺陷密度的变化，并通过仿真验证了失效机理。此外，研究结果显示，随着PCT老化水平的提高，抗短路时间（SCWT）显著降低。这项工作为SiC MOSFET在实际工作条件下的可靠性和使用寿命提供了见解。
{"title":"Influence of Varying Degrees of Power Cycling Aging on Short-Circuit Ruggedness in 1.2-kV SiC MOSFET","authors":"Pengkai Wang;Yuan Chen;Yangtao Long;Hu He;Junhui Li","doi":"10.1109/TDMR.2026.3673394","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3673394","url":null,"abstract":"As promising candidates for high-performance power system applications, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have garnered significant attention from the market. However, reliability challenges, particularly under real-world operating conditions involving multi-stress scenarios, remained to be thoroughly investigated. This study systematically examined the impact of varying levels of power cycling (PCT) degradation on the short-circuit (SC) ruggedness of 1.2 kV SiC MOSFET power modules. The changes in DC parameters and defect density during the multi-stresses were quantitatively analyzed, and the failure mechanism was validated through simulations. Additionally, the results revealed that the short-circuit withstand time (SCWT) decreased significantly with progressive levels of PCT aging. This work provides insights into the reliability and operational lifespan of SiC MOSFET under real-world operating conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"435-443"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study systematically investigates the degradation mechanisms of 1200-V/40-A 4H-SiC junction barrier schottky (JBS) diodes under repetitive avalanche stress. Experimental results reveal a universal rise-then-fall evolution in breakdown voltage, governed by competing effects between interface charge accumulation and material degradation. It is found that failure mode strongly depends on avalanche energy: high-energy pulses induce catastrophic package failure through pin detachment, while low-energy stress causes gradual degradation primarily via transformation of basal plane dislocations, identified as the most critical defects. The study establishes that avalanche robustness constitutes a system-level property, necessitating co-optimization of epitaxial quality, interface stability, and package resilience.
{"title":"Avalanche Failure Mechanisms of 1200-V/40-A 4H-SiC Junction Barrier Schottky Diodes With Various Epilayer Defects","authors":"Jinlan Li;Yan Xu;Huaren Sheng;Quanzhi Chen;Ling Dong;Yiming Shi;Yulin Wang;Liming Zhou;Yuan Xu","doi":"10.1109/TDMR.2026.3676812","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3676812","url":null,"abstract":"This study systematically investigates the degradation mechanisms of 1200-V/40-A 4H-SiC junction barrier schottky (JBS) diodes under repetitive avalanche stress. Experimental results reveal a universal rise-then-fall evolution in breakdown voltage, governed by competing effects between interface charge accumulation and material degradation. It is found that failure mode strongly depends on avalanche energy: high-energy pulses induce catastrophic package failure through pin detachment, while low-energy stress causes gradual degradation primarily via transformation of basal plane dislocations, identified as the most critical defects. The study establishes that avalanche robustness constitutes a system-level property, necessitating co-optimization of epitaxial quality, interface stability, and package resilience.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"467-474"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates the trap-induced degradation in p-GaN gate HEMTs under gate pulse stress via transient current analysis. Electrical measurements demonstrate a positive threshold voltage shift and a reduction in drain current with prolonged bipolar pulse stress. Using the transient current method combined with Bayesian deconvolution, three distinct trap levels designated DP1 to DP3 are identified, whose amplitudes grow consistently with stress time. To clarify the underlying mechanism, bipolar and unipolar pulse stresses are compared at varying frequencies. The threshold voltage shift increases with frequency under bipolar stress but decreases under unipolar stress, confirming that bipolar stress enhances trap density rather than causes transient trap filling. Furthermore, DP1 and DP3 exhibit the significant enhancement in amplitudes, indicating their location near the gate interface where they are vulnerable to pulse-induced carrier injection. Temperature-dependent measurements further confirm that the degradation stems from the density increase of pre-existing traps, with no new trap levels generated. These findings provide critical insight into trap-induced degradation in p-GaN HEMTs, supporting reliability optimization in switching applications.
{"title":"Study of the Degradation in p-GaN Gate HEMTs Under Gate Pulse Stress by Transient Current Analysis","authors":"Shijie Pan;Shanhai Gu;Shiwei Feng;Yamin Zhang;Xuan Li;Xiaozhuang Lu;Maran Wu","doi":"10.1109/TDMR.2026.3671275","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3671275","url":null,"abstract":"This work investigates the trap-induced degradation in p-GaN gate HEMTs under gate pulse stress via transient current analysis. Electrical measurements demonstrate a positive threshold voltage shift and a reduction in drain current with prolonged bipolar pulse stress. Using the transient current method combined with Bayesian deconvolution, three distinct trap levels designated DP1 to DP3 are identified, whose amplitudes grow consistently with stress time. To clarify the underlying mechanism, bipolar and unipolar pulse stresses are compared at varying frequencies. The threshold voltage shift increases with frequency under bipolar stress but decreases under unipolar stress, confirming that bipolar stress enhances trap density rather than causes transient trap filling. Furthermore, DP1 and DP3 exhibit the significant enhancement in amplitudes, indicating their location near the gate interface where they are vulnerable to pulse-induced carrier injection. Temperature-dependent measurements further confirm that the degradation stems from the density increase of pre-existing traps, with no new trap levels generated. These findings provide critical insight into trap-induced degradation in p-GaN HEMTs, supporting reliability optimization in switching applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"541-548"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-11DOI: 10.1109/TDMR.2026.3673011
D. Tierno;H. Bana;M. H. van der Veen;Y. Jeong;S. Decoster;G. Van den Bosch;J. W. Maes;M. Rosmeulen
Post-metallization annealing (PMA) offers significant resistivity improvements for molybdenum word lines (WLs) in 3D NAND Flash, but its impact on device reliability remains unclear. This work systematically evaluates PMA effects using planar capacitors designed for high-temperature processing, comparing Mo deposited by PVD and ALD on PECVD and PEALD SiO2 under H2 ($650~^{circ }$ C) and N2 ($750~^{circ }$ C) annealing. Our electrical characterization reveals trap-assisted Fowler-Nordheim tunneling as the dominant conduction mechanism, with barrier heights significantly influenced by annealing conditions in PEALD SiO2. Time-dependent dielectric breakdown (TDDB) measurements at elevated temperatures confirm that no metal drift occurs even after high-temperature annealing. Failure is caused by a field-driven intrinsic dielectric breakdown, with no evidence of Mo-induced degradation. H2 annealing provides an optimal balance between resistivity improvement and interface quality. These findings establish a pathway for implementing barrierless Mo metallization in sub-30nm z-pitch 3D NAND devices, enabling further vertical scaling while maintaining reliability requirements for both programming and reading operations.
金属化后退火（PMA）可以显著提高3D NAND闪存中钼字线（WLs）的电阻率，但其对器件可靠性的影响尚不清楚。本文系统地评价了PMA对高温处理平面电容器的影响，比较了在H2 （$650~^{circ}$ C）和N2 （$750~^{circ}$ C）退火条件下PVD和ALD沉积Mo在PECVD和PEALD SiO2上的影响。我们的电学表征表明，陷阱辅助的Fowler-Nordheim隧道是主要的传导机制，PEALD SiO2中的势垒高度受退火条件的显著影响。高温下的随时间介电击穿（TDDB）测量证实，即使经过高温退火，也不会发生金属漂移。故障是由场驱动的本征介电击穿引起的，没有证据表明钼引起的退化。H2退火在电阻率改善和界面质量之间提供了最佳平衡。这些发现为在30nm以下z-pitch 3D NAND器件中实现无障碍Mo金属化开辟了一条途径，在保持编程和读取操作可靠性要求的同时，实现了进一步的垂直缩放。
{"title":"Impact of Post-Metallization Annealing on the Reliability of Barrierless Mo Word Lines","authors":"D. Tierno;H. Bana;M. H. van der Veen;Y. Jeong;S. Decoster;G. Van den Bosch;J. W. Maes;M. Rosmeulen","doi":"10.1109/TDMR.2026.3673011","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3673011","url":null,"abstract":"Post-metallization annealing (PMA) offers significant resistivity improvements for molybdenum word lines (WLs) in 3D NAND Flash, but its impact on device reliability remains unclear. This work systematically evaluates PMA effects using planar capacitors designed for high-temperature processing, comparing Mo deposited by PVD and ALD on PECVD and PEALD SiO<sub>2</sub> under H2 (<inline-formula> <tex-math>$650~^{circ }$ </tex-math></inline-formula>C) and N2 (<inline-formula> <tex-math>$750~^{circ }$ </tex-math></inline-formula>C) annealing. Our electrical characterization reveals trap-assisted Fowler-Nordheim tunneling as the dominant conduction mechanism, with barrier heights significantly influenced by annealing conditions in PEALD SiO<sub>2</sub>. Time-dependent dielectric breakdown (TDDB) measurements at elevated temperatures confirm that no metal drift occurs even after high-temperature annealing. Failure is caused by a field-driven intrinsic dielectric breakdown, with no evidence of Mo-induced degradation. H2 annealing provides an optimal balance between resistivity improvement and interface quality. These findings establish a pathway for implementing barrierless Mo metallization in sub-30nm z-pitch 3D NAND devices, enabling further vertical scaling while maintaining reliability requirements for both programming and reading operations.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"451-458"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The degradation of threshold voltage ($V_{text {th}}$ ) induced by gate switching stress (GSS) in Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) is a critical reliability concern in power applications. Locally enhanced electric field and recombination-enhanced defect reactions (REDRs) are the two main mechanisms proposed to explain this degradation. This paper analyzes the degradation behavior of SiC MOSFETs subjected to GSS after total ionizing dose irradiation to gain deeper insight into these degradation mechanisms. By extracting the interface state density ($D_{text {it}}$ ) and separating the interface trapped charge ($N_{text {it}}$ ) and oxide trapped charge ($N_{text {ot}}$ ) from the subthreshold characteristics, it is found that the degradation mechanism under pure GSS is mainly governed by locally enhanced electric field, whereas GSS applied after +15 V gate-bias TID irradiation activates REDRs, generating new interface traps. The main reason is that irradiation-induced interface trapped charges assist electron-hole recombination during GSS, releasing more energy to trigger REDRs. This work contributes to the understanding of $V_{text {th}}$ degradation in SiC MOSFETs under high-frequency switching and provides important guidance for improving their long-term reliability.
{"title":"Irradiation-Induced Charges Assist SiC/SiO2 Interface Trap Generation Under Gate Switching Stress in SiC MOSFETs","authors":"Jiahao Hu;Xiaochuan Deng;Chunhua Li;Xuan Li;Bo Zhang","doi":"10.1109/TDMR.2026.3687417","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3687417","url":null,"abstract":"The degradation of threshold voltage (<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>) induced by gate switching stress (GSS) in Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) is a critical reliability concern in power applications. Locally enhanced electric field and recombination-enhanced defect reactions (REDRs) are the two main mechanisms proposed to explain this degradation. This paper analyzes the degradation behavior of SiC MOSFETs subjected to GSS after total ionizing dose irradiation to gain deeper insight into these degradation mechanisms. By extracting the interface state density (<inline-formula> <tex-math>$D_{text {it}}$ </tex-math></inline-formula>) and separating the interface trapped charge (<inline-formula> <tex-math>$N_{text {it}}$ </tex-math></inline-formula>) and oxide trapped charge (<inline-formula> <tex-math>$N_{text {ot}}$ </tex-math></inline-formula>) from the subthreshold characteristics, it is found that the degradation mechanism under pure GSS is mainly governed by locally enhanced electric field, whereas GSS applied after +15 V gate-bias TID irradiation activates REDRs, generating new interface traps. The main reason is that irradiation-induced interface trapped charges assist electron-hole recombination during GSS, releasing more energy to trigger REDRs. This work contributes to the understanding of <inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula> degradation in SiC MOSFETs under high-frequency switching and provides important guidance for improving their long-term reliability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"629-636"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-03-05DOI: 10.1109/TDMR.2026.3690502
Zhongyuan Chen;Hongji Li;Meiting Cui;Rui Jin;Li Ran
Bond wire failure is the dominant failure mode in TO (transistor outline) packaged SiC (silicon carbide) power MOSFETs (metal oxide semiconductor field effect transistors) but there is a lack of understanding about the degradation process. To fill in the knowledge gap, it is necessary to quantify the degradation before the final lift-off or breakage, from external measurements without resorting to scanning microscopy or decapsulation. This paper reports such a study by monitoring the change of device resistance during power cycling (PC). The effect of gate threshold voltage drift can be compensated but is found to be small for the samples selected, and the resistance measurement is used to indicate the gradual development of the foot heel crack. The stresses in two different types of discrete SiC power MOSFETs are compared. The study leads to an experimental procedure of extracting the lifetime model for system design and operational management.
{"title":"Measurement and Modeling of Bond Wire Degradation in TO-Packaged SiC MOSFETs","authors":"Zhongyuan Chen;Hongji Li;Meiting Cui;Rui Jin;Li Ran","doi":"10.1109/TDMR.2026.3690502","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3690502","url":null,"abstract":"Bond wire failure is the dominant failure mode in TO (transistor outline) packaged SiC (silicon carbide) power MOSFETs (metal oxide semiconductor field effect transistors) but there is a lack of understanding about the degradation process. To fill in the knowledge gap, it is necessary to quantify the degradation before the final lift-off or breakage, from external measurements without resorting to scanning microscopy or decapsulation. This paper reports such a study by monitoring the change of device resistance during power cycling (PC). The effect of gate threshold voltage drift can be compensated but is found to be small for the samples selected, and the resistance measurement is used to indicate the gradual development of the foot heel crack. The stresses in two different types of discrete SiC power MOSFETs are compared. The study leads to an experimental procedure of extracting the lifetime model for system design and operational management.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"459-466"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, we investigate the dynamic-RON drift of monolithic Bidirectional AlGaN/GaN HEMTs. To this end, a novel measurement setup is proposed to evaluate the impact of the substrate connection. Particularly, (i) grounded and (ii) floating substrate configurations are compared. The partial recovery of the RON-degradation at high stress voltage is demonstrated, for the first time, on Bidirectional GaN devices with grounded substrate. Conversely, a higher RON-drift is observed with floating substrate configuration, due to the negative back-bias effect experienced during on-state time interval. This extends the knowledge on this topic, providing physical insights into the large degradation observed in previous work by highlighting the detrimental effect of leaving the substrate floating in Bidirectional power switches.
{"title":"Impact of Substrate Connection on Dynamic-RON Drift of 650 V Normally-Off Monolithic Bidirectional AlGaN/GaN HEMT","authors":"Marcello Cioni;Alessandro Chini;Giacomo Cappellini;Giovanni Giorgino;Nuri Said;Maurizio Moschetti;Cristina Miccoli;Tariq Wakrim;Alessandro Contarino;Adriano Abbisogni;Antonio Pizzardi;Santo Smerzi;Maria Eloisa Castagna;Aurore Constant;Ferdinando Iucolano","doi":"10.1109/TDMR.2026.3671620","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3671620","url":null,"abstract":"In this letter, we investigate the dynamic-R<sub>ON</sub> drift of monolithic Bidirectional AlGaN/GaN HEMTs. To this end, a novel measurement setup is proposed to evaluate the impact of the substrate connection. Particularly, (i) grounded and (ii) floating substrate configurations are compared. The partial recovery of the R<sub>ON</sub>-degradation at high stress voltage is demonstrated, for the first time, on Bidirectional GaN devices with grounded substrate. Conversely, a higher R<sub>ON</sub>-drift is observed with floating substrate configuration, due to the negative back-bias effect experienced during on-state time interval. This extends the knowledge on this topic, providing physical insights into the large degradation observed in previous work by highlighting the detrimental effect of leaving the substrate floating in Bidirectional power switches.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"645-647"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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