Pub Date : 2026-06-01Epub Date: 2026-03-13DOI: 10.1109/TDMR.2026.3673951
Swastik Kumar Sahu;Kaushik Mazumdar
Dynamic reliability remains a major barrier to large scale deployment of GaN based high-electron-mobility transistors (HEMTs) in demanding RF and power applications. In this paper we analyse recent experimental and modeling advances that link microscopic trap physics to macroscopic, application-level failure modes such as current collapse, gate/drain lag, dynamic on resistance increase, and threshold-voltage shift. We compare characterization methods (pulsed I–V, DLTS variants, charge-pumping, RF large-signal testing, and optical mapping) in terms of temporal and spatial resolution and practical relevance. Mitigation approaches at device, material, and circuit/system levels are analysed including surface passivation, field-plate design, buffer engineering, gate-stack optimization, thermal management, and cascode/circuit solutions.
{"title":"Key Factors Affecting Dynamic Reliability in GaN HEMTs and How Can They Be Mitigated?","authors":"Swastik Kumar Sahu;Kaushik Mazumdar","doi":"10.1109/TDMR.2026.3673951","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3673951","url":null,"abstract":"Dynamic reliability remains a major barrier to large scale deployment of GaN based high-electron-mobility transistors (HEMTs) in demanding RF and power applications. In this paper we analyse recent experimental and modeling advances that link microscopic trap physics to macroscopic, application-level failure modes such as current collapse, gate/drain lag, dynamic on resistance increase, and threshold-voltage shift. We compare characterization methods (pulsed I–V, DLTS variants, charge-pumping, RF large-signal testing, and optical mapping) in terms of temporal and spatial resolution and practical relevance. Mitigation approaches at device, material, and circuit/system levels are analysed including surface passivation, field-plate design, buffer engineering, gate-stack optimization, thermal management, and cascode/circuit solutions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"388-408"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2025-12-08DOI: 10.1109/TDMR.2025.3641286
Bo Yi;Gaolei Zhang;Xinyi Wu;Huan Li;Junji Cheng;Haimeng Huang;Moufu Kong;Hongqiang Yang
This paper investigated a novel silicon carbide (SiC) trench MOSFET with integrated N+-PolySi/SiC HeteroJunction diode (nHJ-TMOS) on the trench sidewalls to realize low power loss and high temperature stability. Compared to the conventional double-trench MOSFET (DT-MOS), simulation results indicate that the nHJ-TMOS significantly reduces the reverse on-state voltage drop $(V_{mathrm { R_on}})$ from 3.7 to 1.6 V, due to the integration of the N+-PolySi/SiC heterojunction diode (nHJD), which features a low barrier height of ~0.70 eV. By reducing the depth of the gate trench, nHJ-TMOS effectively mitigates the electric field crowding effect at the corners of the gate oxide, obtaining a low electric field of only 2.1 MV/cm. Besides, this shallow gate trench reduces the gate-to-drain capacitance $(C_{mathrm { GD}})$ by 30.9%. Moreover, due to unipolar conductivity of the nHJD, the reverse recovery charges $(Q_{mathrm { rr}})$ of nHJD is reduced by 26.7% and 59.5% under 25°C and 175°C, respectively. Consequently, the turning-on power loss of the nearby switch is reduced by 27.3% and 38.1%, respectively. This provides distinguished advantages for the SiC MOSFET in high power applications.
{"title":"TCAD Investigation on a Novel SiC Trench MOSFET With Integrated N+-PolySi/SiC Heterojunction Diode for Improved Third-Quadrant and High-Temperature Performances","authors":"Bo Yi;Gaolei Zhang;Xinyi Wu;Huan Li;Junji Cheng;Haimeng Huang;Moufu Kong;Hongqiang Yang","doi":"10.1109/TDMR.2025.3641286","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3641286","url":null,"abstract":"This paper investigated a novel silicon carbide (SiC) trench MOSFET with integrated N+-PolySi/SiC HeteroJunction diode (nHJ-TMOS) on the trench sidewalls to realize low power loss and high temperature stability. Compared to the conventional double-trench MOSFET (DT-MOS), simulation results indicate that the nHJ-TMOS significantly reduces the reverse on-state voltage drop <inline-formula> <tex-math>$(V_{mathrm { R_on}})$ </tex-math></inline-formula> from 3.7 to 1.6 V, due to the integration of the N+-PolySi/SiC heterojunction diode (nHJD), which features a low barrier height of ~0.70 eV. By reducing the depth of the gate trench, nHJ-TMOS effectively mitigates the electric field crowding effect at the corners of the gate oxide, obtaining a low electric field of only 2.1 MV/cm. Besides, this shallow gate trench reduces the gate-to-drain capacitance <inline-formula> <tex-math>$(C_{mathrm { GD}})$ </tex-math></inline-formula> by 30.9%. Moreover, due to unipolar conductivity of the nHJD, the reverse recovery charges <inline-formula> <tex-math>$(Q_{mathrm { rr}})$ </tex-math></inline-formula> of nHJD is reduced by 26.7% and 59.5% under 25°C and 175°C, respectively. Consequently, the turning-on power loss of the nearby switch is reduced by 27.3% and 38.1%, respectively. This provides distinguished advantages for the SiC MOSFET in high power applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"17-23"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2025-11-17DOI: 10.1109/TDMR.2025.3633876
Andreas Zippelius;Zubair Mohd;Maximilian Schmid;Gordon Elger
Scarcity of raw data is a major issue for applying data driven methods to reliability prediction, so making the best use of what is available is critical. This paper studies how different aspects of measurement data can be used best. Specifically, the reliability of the solder joint of LED packages is predicted based on Transient Thermal Analysis and Scanning Acoustic Microscopy data from a large measurement campaign. The impact of using full temporal information vs measurements at individual datapoints is investigated as well as the benefit of including the SAM data, and different ways of presenting the TTA information, either as a full curve or as expert-selected features. The impact of formatting categorical information of solder and LED package type as one-hot encoding or using embeddings is considered. Finally, the performance for Pass/Fail predictions of the best identified model with a model architecture developed on a similar dataset is compared. We identified the most relevant sources of information for predicting the behavior and the best format for the data, which helps guide the choice for future model architectures.
{"title":"Comparison of Different Input Data for the Prediction of LED Solder Joints Using Artificial Neural Networks","authors":"Andreas Zippelius;Zubair Mohd;Maximilian Schmid;Gordon Elger","doi":"10.1109/TDMR.2025.3633876","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3633876","url":null,"abstract":"Scarcity of raw data is a major issue for applying data driven methods to reliability prediction, so making the best use of what is available is critical. This paper studies how different aspects of measurement data can be used best. Specifically, the reliability of the solder joint of LED packages is predicted based on Transient Thermal Analysis and Scanning Acoustic Microscopy data from a large measurement campaign. The impact of using full temporal information vs measurements at individual datapoints is investigated as well as the benefit of including the SAM data, and different ways of presenting the TTA information, either as a full curve or as expert-selected features. The impact of formatting categorical information of solder and LED package type as one-hot encoding or using embeddings is considered. Finally, the performance for Pass/Fail predictions of the best identified model with a model architecture developed on a similar dataset is compared. We identified the most relevant sources of information for predicting the behavior and the best format for the data, which helps guide the choice for future model architectures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"157-166"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11250977","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the progress of semiconductor technology, transistor dimensions are continuously shrinking, and thus the sensitivity of static random-access memories (SRAMs) to radiation induced soft errors is increasingly severe. Single-node upsets (SNUs) as well as double-node upsets (DNUs) caused by high-energy radiative particles are typical soft errors. In order to solve this problem, this paper presents two radiation-hardened robust SRAM cells, i.e., RH33T and RH29T, based on multi-input inverters. They primarily use nine multi-input inverters to form the cross-coupled feedback mechanism for enabling the cells to recover quickly when impacted by SNUs or DNUs. HSPICE-based simulation results confirm that the RH29T and RH33T cells can fully tolerate SNUs and DNUs with good reliability and have moderate read/write access speeds and power overhead. In addition, Virtuoso-based simulation results show that the RH29T and RH33T have a moderate tolerance for static noise margin (SNM).
{"title":"Radiation-Hardened SRAM Designs for Self-Recovery From all Single- and Double-Node Upsets","authors":"Aibin Yan;Jinpeng Li;Kun Li;Wenhao Wang;Zhengfeng Huang;Tianming Ni;Qijun Wang;Patrick Girard;Xiaoqing Wen","doi":"10.1109/TDMR.2025.3641827","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3641827","url":null,"abstract":"With the progress of semiconductor technology, transistor dimensions are continuously shrinking, and thus the sensitivity of static random-access memories (SRAMs) to radiation induced soft errors is increasingly severe. Single-node upsets (SNUs) as well as double-node upsets (DNUs) caused by high-energy radiative particles are typical soft errors. In order to solve this problem, this paper presents two radiation-hardened robust SRAM cells, i.e., RH33T and RH29T, based on multi-input inverters. They primarily use nine multi-input inverters to form the cross-coupled feedback mechanism for enabling the cells to recover quickly when impacted by SNUs or DNUs. HSPICE-based simulation results confirm that the RH29T and RH33T cells can fully tolerate SNUs and DNUs with good reliability and have moderate read/write access speeds and power overhead. In addition, Virtuoso-based simulation results show that the RH29T and RH33T have a moderate tolerance for static noise margin (SNM).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"167-177"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2026-03-19DOI: 10.1109/TDMR.2026.3672759
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2026.3672759","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3672759","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11447369","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148515677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2025-12-19DOI: 10.1109/TDMR.2025.3646343
H. Aziza;H. Xun;M. Fieback;M. Taouil;S. Hamdioui
Resistive RAM (RRAM) design optimization and error monitoring is crucial for memory storage applications but also to enable future brain-inspired systems beyond the capabilities of today’s hardware. The figure-of-merit confirming the presence of resistive switching in RRAM devices is its resistance window expressed by the HRS/LRS ratio (High Resistance State over the Low Resistance State). This ratio guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell becomes in storing and retrieving data. From this perspective, this paper proposes an analysis of RRAM intermittent errors with respect to the RRAM resistance ratio. The impact of intermittent errors on the HRS/LRS ratio is analyzed at the RRAM cell electrical level using a dedicated test chip. Silicon measurements show that all detected RRAM intermittent errors directly result from resistance drifts due to ineffective programming operations. In view of these findings, intermittent error mitigation schemes are proposed to address these errors at the circuit level.
{"title":"Experimental Analysis and Circuit-Level Mitigation Strategies for Intermittent Errors in Resistive RAMs","authors":"H. Aziza;H. Xun;M. Fieback;M. Taouil;S. Hamdioui","doi":"10.1109/TDMR.2025.3646343","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3646343","url":null,"abstract":"Resistive RAM (RRAM) design optimization and error monitoring is crucial for memory storage applications but also to enable future brain-inspired systems beyond the capabilities of today’s hardware. The figure-of-merit confirming the presence of resistive switching in RRAM devices is its resistance window expressed by the HRS/LRS ratio (High Resistance State over the Low Resistance State). This ratio guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell becomes in storing and retrieving data. From this perspective, this paper proposes an analysis of RRAM intermittent errors with respect to the RRAM resistance ratio. The impact of intermittent errors on the HRS/LRS ratio is analyzed at the RRAM cell electrical level using a dedicated test chip. Silicon measurements show that all detected RRAM intermittent errors directly result from resistance drifts due to ineffective programming operations. In view of these findings, intermittent error mitigation schemes are proposed to address these errors at the circuit level.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"93-101"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work comprehensively investigates the effects of drain field plate (FP) configurations on the dynamic breakdown and reliability of $650~{V}$ Schottky p-GaN gate HEMTs under single and repetitive surge voltage stresses. Both extended and floating drain FPs lead to improvements in dynamic breakdown voltage and output capacitance $(C_{OSS})$ , thereby enhancing the maximum surge energy handling capability. Through a combination of Deep-Level Transient Spectroscopy (DLTS) for localized trap characterization, analysis of post-stress exponential recovery kinetics, Arrhenius-based activation energy analysis, and TCAD electric field simulations, the underlying physical mechanisms are revealed. The extended drain FP is found to intensify the vertical electric field, which aggravates hot electron trapping in deep-level buffer traps. This leads to significant degradation in threshold voltage $(V_{th})$ stability and on-state conduction characteristics during $650~{V}$ surge voltage hard switching. In contrast, the floating drain FP optimizes the drain-side field distribution, effectively mitigating these trapping effects. Consequently, the floating FP configuration demonstrates superior device stability and an enhanced recovery capability after repetitive surge stresses, providing a critical design guideline for robust power switching applications.
{"title":"Drain Field Plate Effects in p-GaN HEMTs During Surge Voltage Hard Switching","authors":"Jinggui Zhou;Juan Lei;Yuqi Liu;Xuan Li;Qi Zhou;Bo Zhang","doi":"10.1109/TDMR.2026.3652854","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3652854","url":null,"abstract":"This work comprehensively investigates the effects of drain field plate (FP) configurations on the dynamic breakdown and reliability of <inline-formula> <tex-math>$650~{V}$ </tex-math></inline-formula> Schottky p-GaN gate HEMTs under single and repetitive surge voltage stresses. Both extended and floating drain FPs lead to improvements in dynamic breakdown voltage and output capacitance <inline-formula> <tex-math>$(C_{OSS})$ </tex-math></inline-formula>, thereby enhancing the maximum surge energy handling capability. Through a combination of Deep-Level Transient Spectroscopy (DLTS) for localized trap characterization, analysis of post-stress exponential recovery kinetics, Arrhenius-based activation energy analysis, and TCAD electric field simulations, the underlying physical mechanisms are revealed. The extended drain FP is found to intensify the vertical electric field, which aggravates hot electron trapping in deep-level buffer traps. This leads to significant degradation in threshold voltage <inline-formula> <tex-math>$(V_{th})$ </tex-math></inline-formula> stability and on-state conduction characteristics during <inline-formula> <tex-math>$650~{V}$ </tex-math></inline-formula> surge voltage hard switching. In contrast, the floating drain FP optimizes the drain-side field distribution, effectively mitigating these trapping effects. Consequently, the floating FP configuration demonstrates superior device stability and an enhanced recovery capability after repetitive surge stresses, providing a critical design guideline for robust power switching applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"309-314"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2025-12-05DOI: 10.1109/TDMR.2025.3640583
Al Tiba;Andres Torres;Juan Ruiz;Jerry Miller;Chris Michon;Jason Jones
Fault isolation methodologies critically impact the reliability database required for robust semiconductor device qualification. Over the last decade, electron beam induced resistance change (EBIRCH) has been the primary nanoProbing method for isolating shorts in circuits and device structures. However, its material-dependent thermal sensitivity, dual-probe requirement, and biasing-induced failure risks compromise reliability during root cause analysis. This study demonstrates how electron beam induced current (EBIC) significantly improves failure analysis (FA) reliability in logic devices through superior spatial resolution and predictable signal generation. By leveraging its reliance on electron-hole pair generation in a pn junction, EBIC eliminates uncontrolled Seebeck effects, reduces sample blowout risks, and enables single-probe operation without biasing. EBIC is versatile and more easily controlled by the e-beam parameters. The method was reproduced on several different samples with improved FA success rate and quality, and reduced turnaround time compared to EBIRCH.
{"title":"Junction-Level Fault Isolation in Logic Devices Using Electron Beam Induced Current","authors":"Al Tiba;Andres Torres;Juan Ruiz;Jerry Miller;Chris Michon;Jason Jones","doi":"10.1109/TDMR.2025.3640583","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3640583","url":null,"abstract":"Fault isolation methodologies critically impact the reliability database required for robust semiconductor device qualification. Over the last decade, electron beam induced resistance change (EBIRCH) has been the primary nanoProbing method for isolating shorts in circuits and device structures. However, its material-dependent thermal sensitivity, dual-probe requirement, and biasing-induced failure risks compromise reliability during root cause analysis. This study demonstrates how electron beam induced current (EBIC) significantly improves failure analysis (FA) reliability in logic devices through superior spatial resolution and predictable signal generation. By leveraging its reliance on electron-hole pair generation in a pn junction, EBIC eliminates uncontrolled Seebeck effects, reduces sample blowout risks, and enables single-probe operation without biasing. EBIC is versatile and more easily controlled by the e-beam parameters. The method was reproduced on several different samples with improved FA success rate and quality, and reduced turnaround time compared to EBIRCH.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"194-200"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2026-02-19DOI: 10.1109/TDMR.2026.3666272
Hyeun Woo Shin;Namju Kim;Chae Eun Kim;Suk-Kang Sung;Byung Chul Jang
3-D NAND Flash memory has advanced bit-density by word-line (WL) stacking and adopting the cell-over-peripheral (COP) architecture. However, further scaling is constrained by the limitations of planar high-voltage (HV) pass transistors used for WL drivers, which suffer from gate-induced drain leakage (GIDL), punch-through, and poor short-channel control. In this work, we propose the buried channel array transistor (BCAT) as a scalable alternative. While widely adopted in DRAM, its application as an HV pass transistor in NAND Flash remains unexplored. After calibration with measured planar HV transistor data, the same physical parameters were applied to BCAT structures in TCAD simulation to isolate geometry-dependent effects. Through physics-based TCAD analysis, we evaluate the structural and electrostatic suitability of BCAT for HV pass transistor applications. BCAT shows improved off-state robustness due to its extended effective channel and confined electric field distribution, but suffers from increased threshold voltage ($V_{mathrm {T}}$ ) shift induced by body effect. To mitigate the body effect, we propose vertical channel length and body doping concentration as a design knob to balance leakage suppression and $V_{mathrm {T}}$ control. These results highlight BCAT as a promising candidate for future HV pass transistors in high-density 3-D NAND Flash.
{"title":"Investigation of Buried Channel Array Transistor as a Scalable High-Voltage Pass Transistor for 3-D NAND Flash Memory","authors":"Hyeun Woo Shin;Namju Kim;Chae Eun Kim;Suk-Kang Sung;Byung Chul Jang","doi":"10.1109/TDMR.2026.3666272","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3666272","url":null,"abstract":"3-D NAND Flash memory has advanced bit-density by word-line (WL) stacking and adopting the cell-over-peripheral (COP) architecture. However, further scaling is constrained by the limitations of planar high-voltage (HV) pass transistors used for WL drivers, which suffer from gate-induced drain leakage (GIDL), punch-through, and poor short-channel control. In this work, we propose the buried channel array transistor (BCAT) as a scalable alternative. While widely adopted in DRAM, its application as an HV pass transistor in NAND Flash remains unexplored. After calibration with measured planar HV transistor data, the same physical parameters were applied to BCAT structures in TCAD simulation to isolate geometry-dependent effects. Through physics-based TCAD analysis, we evaluate the structural and electrostatic suitability of BCAT for HV pass transistor applications. BCAT shows improved off-state robustness due to its extended effective channel and confined electric field distribution, but suffers from increased threshold voltage (<inline-formula> <tex-math>$V_{mathrm {T}}$ </tex-math></inline-formula>) shift induced by body effect. To mitigate the body effect, we propose vertical channel length and body doping concentration as a design knob to balance leakage suppression and <inline-formula> <tex-math>$V_{mathrm {T}}$ </tex-math></inline-formula> control. These results highlight BCAT as a promising candidate for future HV pass transistors in high-density 3-D NAND Flash.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"328-333"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work proposes a Layered Trench Gate (LTG) architecture to suppress leakage current as well as enhance process variation immunity in gate-all-around field-effect transistors (GAAFETs) without requiring punch-through stopper (PTS) doping. By eliminating PTS doping, the LTG avoids drawbacks such as increased band-to-band tunneling and random dopant fluctuations while maintaining strong gate-to-channel electrostatics through a layered trench design. We benchmark the LTG against conventional leakage control methods—PTS, bottom dielectric isolation (BDI), local BDI (LBDI), and trench gate (TG)—under realistic fabrication variations, particularly a 6 nm source/drain over-etch. Under these conditions, the PTS structure suffers a 2,840-fold increase in off-current and a $3.84times 10^{{-3}}$ -fold reduction in on/off ratio, whereas the LTG shows only 21.5-fold and $4.69times 10^{{-2}}$ -fold changes, respectively, demonstrating significantly improved robustness. A 3-stage ring oscillator simulation reveals that the LTG achieves 1.9% shorter delay and 2.4% lower dynamic power under identical conditions. These results highlight the LTG’s enhanced gate-to-channel control and minimized parasitic capacitance, establishing it as a strong candidate for future nanoscale devices demanding superior variation immunity and power-performance efficiency.
{"title":"Layered Trench Gate Exhibiting Source/Drain Over-Etch Immunity Without Punch-Through Stopper","authors":"Seungjoon Jeong;Myongjin Kim;Subin Lim;Huiseong Shin;Changhwan Shin","doi":"10.1109/TDMR.2025.3642316","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3642316","url":null,"abstract":"This work proposes a Layered Trench Gate (LTG) architecture to suppress leakage current as well as enhance process variation immunity in gate-all-around field-effect transistors (GAAFETs) without requiring punch-through stopper (PTS) doping. By eliminating PTS doping, the LTG avoids drawbacks such as increased band-to-band tunneling and random dopant fluctuations while maintaining strong gate-to-channel electrostatics through a layered trench design. We benchmark the LTG against conventional leakage control methods—PTS, bottom dielectric isolation (BDI), local BDI (LBDI), and trench gate (TG)—under realistic fabrication variations, particularly a 6 nm source/drain over-etch. Under these conditions, the PTS structure suffers a 2,840-fold increase in off-current and a <inline-formula> <tex-math>$3.84times 10^{{-3}}$ </tex-math></inline-formula>-fold reduction in on/off ratio, whereas the LTG shows only 21.5-fold and <inline-formula> <tex-math>$4.69times 10^{{-2}}$ </tex-math></inline-formula>-fold changes, respectively, demonstrating significantly improved robustness. A 3-stage ring oscillator simulation reveals that the LTG achieves 1.9% shorter delay and 2.4% lower dynamic power under identical conditions. These results highlight the LTG’s enhanced gate-to-channel control and minimized parasitic capacitance, establishing it as a strong candidate for future nanoscale devices demanding superior variation immunity and power-performance efficiency.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"209-214"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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